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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32l4xx_hal_tim_ex.h\r
   4   * @author  MCD Application Team\r
   5   * @brief   Header file of TIM HAL Extended module.\r
   6   ******************************************************************************\r
   7   * @attention\r
   8   *\r
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
  10   * All rights reserved.</center></h2>\r
  11   *\r
  12   * This software component is licensed by ST under BSD 3-Clause license,\r
  13   * the "License"; You may not use this file except in compliance with the\r
  14   * License. You may obtain a copy of the License at:\r
  15   *                        opensource.org/licenses/BSD-3-Clause\r
  16   *\r
  17   ******************************************************************************\r
  18   */\r
  19 \r
  20 /* Define to prevent recursive inclusion -------------------------------------*/\r
  21 #ifndef STM32L4xx_HAL_TIM_EX_H\r
  22 #define STM32L4xx_HAL_TIM_EX_H\r
  23 \r
  24 #ifdef __cplusplus\r
  25 extern "C" {\r
  26 #endif\r
  27 \r
  28 /* Includes ------------------------------------------------------------------*/\r
  29 #include "stm32l4xx_hal_def.h"\r
  30 \r
  31 /** @addtogroup STM32L4xx_HAL_Driver\r
  32   * @{\r
  33   */\r
  34 \r
  35 /** @addtogroup TIMEx\r
  36   * @{\r
  37   */\r
  38 \r
  39 /* Exported types ------------------------------------------------------------*/\r
  40 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
  41   * @{\r
  42   */\r
  43 \r
  44 /**\r
  45   * @brief  TIM Hall sensor Configuration Structure definition\r
  46   */\r
  47 \r
  48 typedef struct\r
  49 {\r
  50   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.\r
  51                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
  52 \r
  53   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r
  54                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
  55 \r
  56   uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r
  57                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
  58 \r
  59   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
  60                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
  61 } TIM_HallSensor_InitTypeDef;\r
  62 \r
  63 /**\r
  64   * @brief  TIM Break/Break2 input configuration\r
  65   */\r
  66 typedef struct\r
  67 {\r
  68   uint32_t Source;         /*!< Specifies the source of the timer break input.\r
  69                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */\r
  70   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.\r
  71                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r
  72   uint32_t Polarity;       /*!< Specifies the break input source polarity.\r
  73                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r
  74                                 Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r
  75 }\r
  76 TIMEx_BreakInputConfigTypeDef;\r
  77 \r
  78 /**\r
  79   * @}\r
  80   */\r
  81 /* End of exported types -----------------------------------------------------*/\r
  82 \r
  83 /* Exported constants --------------------------------------------------------*/\r
  84 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
  85   * @{\r
  86   */\r
  87 \r
  88 /** @defgroup TIMEx_Remap TIM Extended Remapping\r
  89   * @{\r
  90   */\r
  91 #define TIM_TIM1_ETR_ADC1_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
  92 #define TIM_TIM1_ETR_ADC1_AWD1      TIM1_OR1_ETR_ADC1_RMP_0                               /* !< TIM1_ETR is connected to ADC1 AWD1 */\r
  93 #define TIM_TIM1_ETR_ADC1_AWD2      TIM1_OR1_ETR_ADC1_RMP_1                               /* !< TIM1_ETR is connected to ADC1 AWD2 */\r
  94 #define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */\r
  95 #if defined (ADC3)\r
  96 #define TIM_TIM1_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
  97 #define TIM_TIM1_ETR_ADC3_AWD1      TIM1_OR1_ETR_ADC3_RMP_0                               /* !< TIM1_ETR is connected to ADC3 AWD1 */\r
  98 #define TIM_TIM1_ETR_ADC3_AWD2      TIM1_OR1_ETR_ADC3_RMP_1                               /* !< TIM1_ETR is connected to ADC3 AWD2 */\r
  99 #define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */\r
 100 #endif /* ADC3 */\r
 101 #define TIM_TIM1_TI1_GPIO           0x00000000U                                           /* !< TIM1 TI1 is connected to GPIO */\r
 102 #define TIM_TIM1_TI1_COMP1          TIM1_OR1_TI1_RMP                                      /* !< TIM1 TI1 is connected to COMP1 */\r
 103 #define TIM_TIM1_ETR_GPIO           0x00000000U                                           /* !< TIM1_ETR is connected to GPIO */\r
 104 #define TIM_TIM1_ETR_COMP1          TIM1_OR2_ETRSEL_0                                     /* !< TIM1_ETR is connected to COMP1 output */\r
 105 #if defined(COMP2)\r
 106 #define TIM_TIM1_ETR_COMP2          TIM1_OR2_ETRSEL_1                                     /* !< TIM1_ETR is connected to COMP2 output */\r
 107 #endif /* COMP2 */\r
 108 \r
 109 #if defined (USB_OTG_FS)\r
 110 #define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
 111 #define TIM_TIM2_ITR1_OTG_FS_SOF    TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to OTG_FS SOF */\r
 112 #else\r
 113 #if defined(STM32L471xx)\r
 114 #define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
 115 #define TIM_TIM2_ITR1_NONE          TIM2_OR1_ITR1_RMP                                     /* !< No internal trigger on TIM2_ITR1 */\r
 116 #else\r
 117 #define TIM_TIM2_ITR1_NONE          0x00000000U                                           /* !< No internal trigger on TIM2_ITR1 */\r
 118 #define TIM_TIM2_ITR1_USB_SOF       TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to USB SOF */\r
 119 #endif /* STM32L471xx */\r
 120 #endif /* USB_OTG_FS */\r
 121 #define TIM_TIM2_ETR_GPIO           0x00000000U                                           /* !< TIM2_ETR is connected to GPIO */\r
 122 #define TIM_TIM2_ETR_LSE            TIM2_OR1_ETR1_RMP                                     /* !< TIM2_ETR is connected to LSE */\r
 123 #define TIM_TIM2_ETR_COMP1          TIM2_OR2_ETRSEL_0                                     /* !< TIM2_ETR is connected to COMP1 output */\r
 124 #if defined(COMP2)\r
 125 #define TIM_TIM2_ETR_COMP2          TIM2_OR2_ETRSEL_1                                     /* !< TIM2_ETR is connected to COMP2 output */\r
 126 #endif /* COMP2 */\r
 127 #define TIM_TIM2_TI4_GPIO           0x00000000U                                           /* !< TIM2 TI4 is connected to GPIO */\r
 128 #define TIM_TIM2_TI4_COMP1          TIM2_OR1_TI4_RMP_0                                    /* !< TIM2 TI4 is connected to COMP1 output */\r
 129 #if defined(COMP2)\r
 130 #define TIM_TIM2_TI4_COMP2          TIM2_OR1_TI4_RMP_1                                    /* !< TIM2 TI4 is connected to COMP2 output */\r
 131 #define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */\r
 132 #endif /* COMP2 */\r
 133 \r
 134 #if defined (TIM3)\r
 135 #define TIM_TIM3_TI1_GPIO           0x00000000U                                           /* !< TIM3 TI1 is connected to GPIO */\r
 136 #define TIM_TIM3_TI1_COMP1          TIM3_OR1_TI1_RMP_0                                    /* !< TIM3 TI1 is connected to COMP1 output */\r
 137 #define TIM_TIM3_TI1_COMP2          TIM3_OR1_TI1_RMP_1                                    /* !< TIM3 TI1 is connected to COMP2 output */\r
 138 #define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */\r
 139 #define TIM_TIM3_ETR_GPIO           0x00000000U                                           /* !< TIM3_ETR is connected to GPIO */\r
 140 #define TIM_TIM3_ETR_COMP1          TIM3_OR2_ETRSEL_0                                     /* !< TIM3_ETR is connected to COMP1 output */\r
 141 #endif /* TIM3 */\r
 142 \r
 143 #if defined (TIM8)\r
 144 #if defined(ADC2) && defined(ADC3)\r
 145 #define TIM_TIM8_ETR_ADC2_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
 146 #define TIM_TIM8_ETR_ADC2_AWD1      TIM8_OR1_ETR_ADC2_RMP_0                               /* !< TIM8_ETR is connected to ADC2 AWD1 */\r
 147 #define TIM_TIM8_ETR_ADC2_AWD2      TIM8_OR1_ETR_ADC2_RMP_1                               /* !< TIM8_ETR is connected to ADC2 AWD2 */\r
 148 #define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */\r
 149 #define TIM_TIM8_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
 150 #define TIM_TIM8_ETR_ADC3_AWD1      TIM8_OR1_ETR_ADC3_RMP_0                               /* !< TIM8_ETR is connected to ADC3 AWD1 */\r
 151 #define TIM_TIM8_ETR_ADC3_AWD2      TIM8_OR1_ETR_ADC3_RMP_1                               /* !< TIM8_ETR is connected to ADC3 AWD2 */\r
 152 #define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */\r
 153 #endif /* ADC2 && ADC3 */\r
 154 \r
 155 #define TIM_TIM8_TI1_GPIO           0x00000000U                                           /* !< TIM8 TI1 is connected to GPIO */\r
 156 #define TIM_TIM8_TI1_COMP2          TIM8_OR1_TI1_RMP                                      /* !< TIM8 TI1 is connected to COMP1 */\r
 157 #define TIM_TIM8_ETR_GPIO           0x00000000U                                           /* !< TIM8_ETR is connected to GPIO */\r
 158 #define TIM_TIM8_ETR_COMP1          TIM8_OR2_ETRSEL_0                                     /* !< TIM8_ETR is connected to COMP1 output */\r
 159 #define TIM_TIM8_ETR_COMP2          TIM8_OR2_ETRSEL_1                                     /* !< TIM8_ETR is connected to COMP2 output */\r
 160 #endif /* TIM8 */\r
 161 \r
 162 #define TIM_TIM15_TI1_GPIO          0x00000000U                                           /* !< TIM15 TI1 is connected to GPIO */\r
 163 #define TIM_TIM15_TI1_LSE           TIM15_OR1_TI1_RMP                                     /* !< TIM15 TI1 is connected to LSE */\r
 164 #define TIM_TIM15_ENCODERMODE_NONE  0x00000000U                                           /* !< No redirection */\r
 165 #define TIM_TIM15_ENCODERMODE_TIM2  TIM15_OR1_ENCODER_MODE_0                              /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
 166 #if defined (TIM3)\r
 167 #define TIM_TIM15_ENCODERMODE_TIM3  TIM15_OR1_ENCODER_MODE_1                              /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
 168 #endif /* TIM3 */\r
 169 #if defined (TIM4)\r
 170 #define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
 171 #endif /* TIM4 */\r
 172 \r
 173 #define TIM_TIM16_TI1_GPIO          0x00000000U                                           /* !< TIM16 TI1 is connected to GPIO */\r
 174 #define TIM_TIM16_TI1_LSI           TIM16_OR1_TI1_RMP_0                                   /* !< TIM16 TI1 is connected to LSI */\r
 175 #define TIM_TIM16_TI1_LSE           TIM16_OR1_TI1_RMP_1                                   /* !< TIM16 TI1 is connected to LSE */\r
 176 #define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */\r
 177 #if defined (TIM16_OR1_TI1_RMP_2)\r
 178 #define TIM_TIM16_TI1_MSI           TIM16_OR1_TI1_RMP_2                                   /* !< TIM16 TI1 is connected to MSI */\r
 179 #define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */\r
 180 #define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */\r
 181 #endif /* TIM16_OR1_TI1_RMP_2 */\r
 182 \r
 183 #if defined (TIM17)\r
 184 #define TIM_TIM17_TI1_GPIO          0x00000000U                                           /* !< TIM17 TI1 is connected to GPIO */\r
 185 #define TIM_TIM17_TI1_MSI           TIM17_OR1_TI1_RMP_0                                   /* !< TIM17 TI1 is connected to MSI */\r
 186 #define TIM_TIM17_TI1_HSE_32        TIM17_OR1_TI1_RMP_1                                   /* !< TIM17 TI1 is connected to HSE div 32 */\r
 187 #define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */\r
 188 #endif /* TIM17 */\r
 189 /**\r
 190   * @}\r
 191   */\r
 192 \r
 193 /** @defgroup TIMEx_Break_Input TIM Extended Break input\r
 194   * @{\r
 195   */\r
 196 #define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */\r
 197 #define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */\r
 198 /**\r
 199   * @}\r
 200   */\r
 201 \r
 202 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source\r
 203   * @{\r
 204   */\r
 205 #define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */\r
 206 #define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */\r
 207 #define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */\r
 208 #if defined (DFSDM1_Channel0)\r
 209 #define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r
 210 #endif /* DFSDM1_Channel0 */\r
 211 /**\r
 212   * @}\r
 213   */\r
 214 \r
 215 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r
 216   * @{\r
 217   */\r
 218 #define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */\r
 219 #define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */\r
 220 /**\r
 221   * @}\r
 222   */\r
 223 \r
 224 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity\r
 225   * @{\r
 226   */\r
 227 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */\r
 228 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */\r
 229 /**\r
 230   * @}\r
 231   */\r
 232 \r
 233 /**\r
 234   * @}\r
 235   */\r
 236 /* End of exported constants -------------------------------------------------*/\r
 237 \r
 238 /* Exported macro ------------------------------------------------------------*/\r
 239 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
 240   * @{\r
 241   */\r
 242 \r
 243 /**\r
 244   * @}\r
 245   */\r
 246 /* End of exported macro -----------------------------------------------------*/\r
 247 \r
 248 /* Private macro -------------------------------------------------------------*/\r
 249 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
 250   * @{\r
 251   */\r
 252 #define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))\r
 253 \r
 254 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \\r
 255                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r
 256 \r
 257 #if defined (DFSDM1_Channel0)\r
 258 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
 259                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
 260                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \\r
 261                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))\r
 262 #else\r
 263 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
 264                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
 265                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))\r
 266 #endif /* DFSDM1_Channel0 */\r
 267 \r
 268 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \\r
 269                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r
 270 \r
 271 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \\r
 272                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r
 273 \r
 274 /**\r
 275   * @}\r
 276   */\r
 277 /* End of private macro ------------------------------------------------------*/\r
 278 \r
 279 /* Exported functions --------------------------------------------------------*/\r
 280 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
 281   * @{\r
 282   */\r
 283 \r
 284 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
 285   *  @brief    Timer Hall Sensor functions\r
 286   * @{\r
 287   */\r
 288 /*  Timer Hall Sensor functions  **********************************************/\r
 289 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\r
 290 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
 291 \r
 292 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
 293 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
 294 \r
 295 /* Blocking mode: Polling */\r
 296 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
 297 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
 298 /* Non-Blocking mode: Interrupt */\r
 299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
 300 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
 301 /* Non-Blocking mode: DMA */\r
 302 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
 303 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
 304 /**\r
 305   * @}\r
 306   */\r
 307 \r
 308 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
 309   *  @brief   Timer Complementary Output Compare functions\r
 310   * @{\r
 311   */\r
 312 /*  Timer Complementary Output Compare functions  *****************************/\r
 313 /* Blocking mode: Polling */\r
 314 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 315 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 316 \r
 317 /* Non-Blocking mode: Interrupt */\r
 318 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 319 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 320 \r
 321 /* Non-Blocking mode: DMA */\r
 322 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
 323 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 324 /**\r
 325   * @}\r
 326   */\r
 327 \r
 328 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
 329   *  @brief    Timer Complementary PWM functions\r
 330   * @{\r
 331   */\r
 332 /*  Timer Complementary PWM functions  ****************************************/\r
 333 /* Blocking mode: Polling */\r
 334 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 335 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 336 \r
 337 /* Non-Blocking mode: Interrupt */\r
 338 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 339 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 340 /* Non-Blocking mode: DMA */\r
 341 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
 342 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
 343 /**\r
 344   * @}\r
 345   */\r
 346 \r
 347 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
 348   *  @brief    Timer Complementary One Pulse functions\r
 349   * @{\r
 350   */\r
 351 /*  Timer Complementary One Pulse functions  **********************************/\r
 352 /* Blocking mode: Polling */\r
 353 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
 354 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
 355 \r
 356 /* Non-Blocking mode: Interrupt */\r
 357 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
 358 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
 359 /**\r
 360   * @}\r
 361   */\r
 362 \r
 363 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
 364   *  @brief    Peripheral Control functions\r
 365   * @{\r
 366   */\r
 367 /* Extended Control functions  ************************************************/\r
 368 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
 369                                               uint32_t  CommutationSource);\r
 370 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
 371                                                  uint32_t  CommutationSource);\r
 372 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
 373                                                   uint32_t  CommutationSource);\r
 374 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
 375                                                         TIM_MasterConfigTypeDef *sMasterConfig);\r
 376 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
 377                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
 378 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,\r
 379                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r
 380 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);\r
 381 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
 382 /**\r
 383   * @}\r
 384   */\r
 385 \r
 386 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
 387   * @brief    Extended Callbacks functions\r
 388   * @{\r
 389   */\r
 390 /* Extended Callback **********************************************************/\r
 391 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\r
 392 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\r
 393 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
 394 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);\r
 395 /**\r
 396   * @}\r
 397   */\r
 398 \r
 399 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
 400   * @brief    Extended Peripheral State functions\r
 401   * @{\r
 402   */\r
 403 /* Extended Peripheral State functions  ***************************************/\r
 404 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
 405 /**\r
 406   * @}\r
 407   */\r
 408 \r
 409 /**\r
 410   * @}\r
 411   */\r
 412 /* End of exported functions -------------------------------------------------*/\r
 413 \r
 414 /* Private functions----------------------------------------------------------*/\r
 415 /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions\r
 416   * @{\r
 417   */\r
 418 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
 419 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\r
 420 /**\r
 421   * @}\r
 422   */\r
 423 /* End of private functions --------------------------------------------------*/\r
 424 \r
 425 /**\r
 426   * @}\r
 427   */\r
 428 \r
 429 /**\r
 430   * @}\r
 431   */\r
 432 \r
 433 #ifdef __cplusplus\r
 434 }\r
 435 #endif\r
 436 \r
 437 \r
 438 #endif /* STM32L4xx_HAL_TIM_EX_H */\r
 439 \r
 440 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r