git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/startup_stm32l475xx.s

   1 ;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************\r
   2 ;* File Name          : startup_stm32l475xx.s\r
   3 ;* Author             : MCD Application Team\r
   4 ;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.\r
   5 ;*                      This module performs:\r
   6 ;*                      - Set the initial SP\r
   7 ;*                      - Set the initial PC == Reset_Handler\r
   8 ;*                      - Set the vector table entries with the exceptions ISR address\r
   9 ;*                      - Branches to __main in the C library (which eventually\r
  10 ;*                        calls main()).\r
  11 ;*                      After Reset the Cortex-M4 processor is in Thread mode,\r
  12 ;*                      priority is Privileged, and the Stack is set to Main.\r
  13 ;* <<< Use Configuration Wizard in Context Menu >>>\r
  14 ;*******************************************************************************\r
  15 ;*\r
  16 ;* Redistribution and use in source and binary forms, with or without modification,\r
  17 ;* are permitted provided that the following conditions are met:\r
  18 ;*   1. Redistributions of source code must retain the above copyright notice,\r
  19 ;*      this list of conditions and the following disclaimer.\r
  20 ;*   2. Redistributions in binary form must reproduce the above copyright notice,\r
  21 ;*      this list of conditions and the following disclaimer in the documentation\r
  22 ;*      and/or other materials provided with the distribution.\r
  23 ;*   3. Neither the name of STMicroelectronics nor the names of its contributors\r
  24 ;*      may be used to endorse or promote products derived from this software\r
  25 ;*      without specific prior written permission.\r
  26 ;*\r
  27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
  28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
  29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
  30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
  31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
  33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
  34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
  35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  37 ;*\r
  38 ;*******************************************************************************\r
  39 ;\r
  40 ; Amount of memory (in bytes) allocated for Stack\r
  41 ; Tailor this value to your application needs\r
  42 ; <h> Stack Configuration\r
  43 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  44 ; </h>\r
  45 \r
  46 Stack_Size              EQU     0x400\r
  47 \r
  48                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  49 Stack_Mem       SPACE   Stack_Size\r
  50 __initial_sp\r
  51 \r
  52 \r
  53 ; <h> Heap Configuration\r
  54 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  55 ; </h>\r
  56 \r
  57 Heap_Size      EQU     0x200\r
  58 \r
  59                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  60 __heap_base\r
  61 Heap_Mem        SPACE   Heap_Size\r
  62 __heap_limit\r
  63 \r
  64                 PRESERVE8\r
  65                 THUMB\r
  66 \r
  67 \r
  68 ; Vector Table Mapped to Address 0 at Reset\r
  69                 AREA    RESET, DATA, READONLY\r
  70                 EXPORT  __Vectors\r
  71                 EXPORT  __Vectors_End\r
  72                 EXPORT  __Vectors_Size\r
  73 \r
  74 __Vectors       DCD     __initial_sp               ; Top of Stack\r
  75                 DCD     Reset_Handler              ; Reset Handler\r
  76                 DCD     NMI_Handler                ; NMI Handler\r
  77                 DCD     HardFault_Handler          ; Hard Fault Handler\r
  78                 DCD     MemManage_Handler          ; MPU Fault Handler\r
  79                 DCD     BusFault_Handler           ; Bus Fault Handler\r
  80                 DCD     UsageFault_Handler         ; Usage Fault Handler\r
  81                 DCD     0                          ; Reserved\r
  82                 DCD     0                          ; Reserved\r
  83                 DCD     0                          ; Reserved\r
  84                 DCD     0                          ; Reserved\r
  85                 DCD     SVC_Handler                ; SVCall Handler\r
  86                 DCD     DebugMon_Handler           ; Debug Monitor Handler\r
  87                 DCD     0                          ; Reserved\r
  88                 DCD     PendSV_Handler             ; PendSV Handler\r
  89                 DCD     SysTick_Handler            ; SysTick Handler\r
  90 \r
  91                 ; External Interrupts\r
  92                 DCD     WWDG_IRQHandler                   ; Window WatchDog\r
  93                 DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
  94                 DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line\r
  95                 DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line\r
  96                 DCD     FLASH_IRQHandler                  ; FLASH\r
  97                 DCD     RCC_IRQHandler                    ; RCC\r
  98                 DCD     EXTI0_IRQHandler                  ; EXTI Line0\r
  99                 DCD     EXTI1_IRQHandler                  ; EXTI Line1\r
 100                 DCD     EXTI2_IRQHandler                  ; EXTI Line2\r
 101                 DCD     EXTI3_IRQHandler                  ; EXTI Line3\r
 102                 DCD     EXTI4_IRQHandler                  ; EXTI Line4\r
 103                 DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1\r
 104                 DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2\r
 105                 DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3\r
 106                 DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4\r
 107                 DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5\r
 108                 DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6\r
 109                 DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7\r
 110                 DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2\r
 111                 DCD     CAN1_TX_IRQHandler                ; CAN1 TX\r
 112                 DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0\r
 113                 DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1\r
 114                 DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE\r
 115                 DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s\r
 116                 DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15\r
 117                 DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16\r
 118                 DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17\r
 119                 DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare\r
 120                 DCD     TIM2_IRQHandler                   ; TIM2\r
 121                 DCD     TIM3_IRQHandler                   ; TIM3\r
 122                 DCD     TIM4_IRQHandler                   ; TIM4\r
 123                 DCD     I2C1_EV_IRQHandler                ; I2C1 Event\r
 124                 DCD     I2C1_ER_IRQHandler                ; I2C1 Error\r
 125                 DCD     I2C2_EV_IRQHandler                ; I2C2 Event\r
 126                 DCD     I2C2_ER_IRQHandler                ; I2C2 Error\r
 127                 DCD     SPI1_IRQHandler                   ; SPI1\r
 128                 DCD     SPI2_IRQHandler                   ; SPI2\r
 129                 DCD     USART1_IRQHandler                 ; USART1\r
 130                 DCD     USART2_IRQHandler                 ; USART2\r
 131                 DCD     USART3_IRQHandler                 ; USART3\r
 132                 DCD     EXTI15_10_IRQHandler              ; External Line[15:10]\r
 133                 DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line\r
 134                 DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt\r
 135                 DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt\r
 136                 DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt\r
 137                 DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt\r
 138                 DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt\r
 139                 DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt\r
 140                 DCD     FMC_IRQHandler                    ; FMC\r
 141                 DCD     SDMMC1_IRQHandler                 ; SDMMC1\r
 142                 DCD     TIM5_IRQHandler                   ; TIM5\r
 143                 DCD     SPI3_IRQHandler                   ; SPI3\r
 144                 DCD     UART4_IRQHandler                  ; UART4\r
 145                 DCD     UART5_IRQHandler                  ; UART5\r
 146                 DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors\r
 147                 DCD     TIM7_IRQHandler                   ; TIM7\r
 148                 DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1\r
 149                 DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2\r
 150                 DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3\r
 151                 DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4\r
 152                 DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5\r
 153                 DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt\r
 154                 DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt\r
 155                 DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt\r
 156                 DCD     COMP_IRQHandler                   ; COMP Interrupt\r
 157                 DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt\r
 158                 DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt\r
 159                 DCD     OTG_FS_IRQHandler                 ; USB OTG FS\r
 160                 DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6\r
 161                 DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7\r
 162                 DCD     LPUART1_IRQHandler                ; LP UART1 interrupt\r
 163                 DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt\r
 164                 DCD     I2C3_EV_IRQHandler                ; I2C3 event\r
 165                 DCD     I2C3_ER_IRQHandler                ; I2C3 error\r
 166                 DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt\r
 167                 DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt\r
 168                 DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt\r
 169                 DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt\r
 170                 DCD     0                                 ; Reserved                \r
 171                 DCD     0                                 ; Reserved                \r
 172                 DCD     RNG_IRQHandler                    ; RNG global interrupt\r
 173                 DCD     FPU_IRQHandler                    ; FPU\r
 174 \r
 175 __Vectors_End\r
 176 \r
 177 __Vectors_Size  EQU  __Vectors_End - __Vectors\r
 178 \r
 179                 AREA    |.text|, CODE, READONLY\r
 180 \r
 181 ; Reset handler\r
 182 Reset_Handler    PROC\r
 183                  EXPORT  Reset_Handler             [WEAK]\r
 184         IMPORT  SystemInit\r
 185         IMPORT  __main\r
 186 \r
 187                  LDR     R0, =SystemInit\r
 188                  BLX     R0\r
 189                  LDR     R0, =__main\r
 190                  BX      R0\r
 191                  ENDP\r
 192 \r
 193 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 194 \r
 195 NMI_Handler     PROC\r
 196                 EXPORT  NMI_Handler                [WEAK]\r
 197                 B       .\r
 198                 ENDP\r
 199 HardFault_Handler\\r
 200                 PROC\r
 201                 EXPORT  HardFault_Handler          [WEAK]\r
 202                 B       .\r
 203                 ENDP\r
 204 MemManage_Handler\\r
 205                 PROC\r
 206                 EXPORT  MemManage_Handler          [WEAK]\r
 207                 B       .\r
 208                 ENDP\r
 209 BusFault_Handler\\r
 210                 PROC\r
 211                 EXPORT  BusFault_Handler           [WEAK]\r
 212                 B       .\r
 213                 ENDP\r
 214 UsageFault_Handler\\r
 215                 PROC\r
 216                 EXPORT  UsageFault_Handler         [WEAK]\r
 217                 B       .\r
 218                 ENDP\r
 219 SVC_Handler     PROC\r
 220                 EXPORT  SVC_Handler                [WEAK]\r
 221                 B       .\r
 222                 ENDP\r
 223 DebugMon_Handler\\r
 224                 PROC\r
 225                 EXPORT  DebugMon_Handler           [WEAK]\r
 226                 B       .\r
 227                 ENDP\r
 228 PendSV_Handler  PROC\r
 229                 EXPORT  PendSV_Handler             [WEAK]\r
 230                 B       .\r
 231                 ENDP\r
 232 SysTick_Handler PROC\r
 233                 EXPORT  SysTick_Handler            [WEAK]\r
 234                 B       .\r
 235                 ENDP\r
 236 \r
 237 Default_Handler PROC\r
 238 \r
 239         EXPORT     WWDG_IRQHandler                   [WEAK]\r
 240         EXPORT     PVD_PVM_IRQHandler                [WEAK]\r
 241         EXPORT     TAMP_STAMP_IRQHandler             [WEAK]\r
 242         EXPORT     RTC_WKUP_IRQHandler               [WEAK]\r
 243         EXPORT     FLASH_IRQHandler                  [WEAK]\r
 244         EXPORT     RCC_IRQHandler                    [WEAK]\r
 245         EXPORT     EXTI0_IRQHandler                  [WEAK]\r
 246         EXPORT     EXTI1_IRQHandler                  [WEAK]\r
 247         EXPORT     EXTI2_IRQHandler                  [WEAK]\r
 248         EXPORT     EXTI3_IRQHandler                  [WEAK]\r
 249         EXPORT     EXTI4_IRQHandler                  [WEAK]\r
 250         EXPORT     DMA1_Channel1_IRQHandler          [WEAK]\r
 251         EXPORT     DMA1_Channel2_IRQHandler          [WEAK]\r
 252         EXPORT     DMA1_Channel3_IRQHandler          [WEAK]\r
 253         EXPORT     DMA1_Channel4_IRQHandler          [WEAK]\r
 254         EXPORT     DMA1_Channel5_IRQHandler          [WEAK]\r
 255         EXPORT     DMA1_Channel6_IRQHandler          [WEAK]\r
 256         EXPORT     DMA1_Channel7_IRQHandler          [WEAK]\r
 257         EXPORT     ADC1_2_IRQHandler                 [WEAK]\r
 258         EXPORT     CAN1_TX_IRQHandler                [WEAK]\r
 259         EXPORT     CAN1_RX0_IRQHandler               [WEAK]\r
 260         EXPORT     CAN1_RX1_IRQHandler               [WEAK]\r
 261         EXPORT     CAN1_SCE_IRQHandler               [WEAK]\r
 262         EXPORT     EXTI9_5_IRQHandler                [WEAK]\r
 263         EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]\r
 264         EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]\r
 265         EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]\r
 266         EXPORT     TIM1_CC_IRQHandler                [WEAK]\r
 267         EXPORT     TIM2_IRQHandler                   [WEAK]\r
 268         EXPORT     TIM3_IRQHandler                   [WEAK]\r
 269         EXPORT     TIM4_IRQHandler                   [WEAK]\r
 270         EXPORT     I2C1_EV_IRQHandler                [WEAK]\r
 271         EXPORT     I2C1_ER_IRQHandler                [WEAK]\r
 272         EXPORT     I2C2_EV_IRQHandler                [WEAK]\r
 273         EXPORT     I2C2_ER_IRQHandler                [WEAK]\r
 274         EXPORT     SPI1_IRQHandler                   [WEAK]\r
 275         EXPORT     SPI2_IRQHandler                   [WEAK]\r
 276         EXPORT     USART1_IRQHandler                 [WEAK]\r
 277         EXPORT     USART2_IRQHandler                 [WEAK]\r
 278         EXPORT     USART3_IRQHandler                 [WEAK]\r
 279         EXPORT     EXTI15_10_IRQHandler              [WEAK]\r
 280         EXPORT     RTC_Alarm_IRQHandler              [WEAK]\r
 281         EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]\r
 282         EXPORT     TIM8_BRK_IRQHandler               [WEAK]\r
 283         EXPORT     TIM8_UP_IRQHandler                [WEAK]\r
 284         EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]\r
 285         EXPORT     TIM8_CC_IRQHandler                [WEAK]\r
 286         EXPORT     ADC3_IRQHandler                   [WEAK]\r
 287         EXPORT     FMC_IRQHandler                    [WEAK]\r
 288         EXPORT     SDMMC1_IRQHandler                 [WEAK]\r
 289         EXPORT     TIM5_IRQHandler                   [WEAK]\r
 290         EXPORT     SPI3_IRQHandler                   [WEAK]\r
 291         EXPORT     UART4_IRQHandler                  [WEAK]\r
 292         EXPORT     UART5_IRQHandler                  [WEAK]\r
 293         EXPORT     TIM6_DAC_IRQHandler               [WEAK]\r
 294         EXPORT     TIM7_IRQHandler                   [WEAK]\r
 295         EXPORT     DMA2_Channel1_IRQHandler          [WEAK]\r
 296         EXPORT     DMA2_Channel2_IRQHandler          [WEAK]\r
 297         EXPORT     DMA2_Channel3_IRQHandler          [WEAK]\r
 298         EXPORT     DMA2_Channel4_IRQHandler          [WEAK]\r
 299         EXPORT     DMA2_Channel5_IRQHandler          [WEAK]\r
 300         EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]\r
 301         EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]\r
 302         EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]\r
 303         EXPORT     COMP_IRQHandler                   [WEAK]\r
 304         EXPORT     LPTIM1_IRQHandler                 [WEAK]\r
 305         EXPORT     LPTIM2_IRQHandler                 [WEAK]\r
 306         EXPORT     OTG_FS_IRQHandler                 [WEAK]\r
 307         EXPORT     DMA2_Channel6_IRQHandler          [WEAK]\r
 308         EXPORT     DMA2_Channel7_IRQHandler          [WEAK]\r
 309         EXPORT     LPUART1_IRQHandler                [WEAK]\r
 310         EXPORT     QUADSPI_IRQHandler                [WEAK]\r
 311         EXPORT     I2C3_EV_IRQHandler                [WEAK]\r
 312         EXPORT     I2C3_ER_IRQHandler                [WEAK]\r
 313         EXPORT     SAI1_IRQHandler                   [WEAK]\r
 314         EXPORT     SAI2_IRQHandler                   [WEAK]\r
 315         EXPORT     SWPMI1_IRQHandler                 [WEAK]\r
 316         EXPORT     TSC_IRQHandler                    [WEAK]\r
 317         EXPORT     RNG_IRQHandler                    [WEAK]\r
 318         EXPORT     FPU_IRQHandler                    [WEAK]\r
 319 \r
 320 WWDG_IRQHandler\r
 321 PVD_PVM_IRQHandler\r
 322 TAMP_STAMP_IRQHandler\r
 323 RTC_WKUP_IRQHandler\r
 324 FLASH_IRQHandler\r
 325 RCC_IRQHandler\r
 326 EXTI0_IRQHandler\r
 327 EXTI1_IRQHandler\r
 328 EXTI2_IRQHandler\r
 329 EXTI3_IRQHandler\r
 330 EXTI4_IRQHandler\r
 331 DMA1_Channel1_IRQHandler\r
 332 DMA1_Channel2_IRQHandler\r
 333 DMA1_Channel3_IRQHandler\r
 334 DMA1_Channel4_IRQHandler\r
 335 DMA1_Channel5_IRQHandler\r
 336 DMA1_Channel6_IRQHandler\r
 337 DMA1_Channel7_IRQHandler\r
 338 ADC1_2_IRQHandler\r
 339 CAN1_TX_IRQHandler\r
 340 CAN1_RX0_IRQHandler\r
 341 CAN1_RX1_IRQHandler\r
 342 CAN1_SCE_IRQHandler\r
 343 EXTI9_5_IRQHandler\r
 344 TIM1_BRK_TIM15_IRQHandler\r
 345 TIM1_UP_TIM16_IRQHandler\r
 346 TIM1_TRG_COM_TIM17_IRQHandler\r
 347 TIM1_CC_IRQHandler\r
 348 TIM2_IRQHandler\r
 349 TIM3_IRQHandler\r
 350 TIM4_IRQHandler\r
 351 I2C1_EV_IRQHandler\r
 352 I2C1_ER_IRQHandler\r
 353 I2C2_EV_IRQHandler\r
 354 I2C2_ER_IRQHandler\r
 355 SPI1_IRQHandler\r
 356 SPI2_IRQHandler\r
 357 USART1_IRQHandler\r
 358 USART2_IRQHandler\r
 359 USART3_IRQHandler\r
 360 EXTI15_10_IRQHandler\r
 361 RTC_Alarm_IRQHandler\r
 362 DFSDM1_FLT3_IRQHandler\r
 363 TIM8_BRK_IRQHandler\r
 364 TIM8_UP_IRQHandler\r
 365 TIM8_TRG_COM_IRQHandler\r
 366 TIM8_CC_IRQHandler\r
 367 ADC3_IRQHandler\r
 368 FMC_IRQHandler\r
 369 SDMMC1_IRQHandler\r
 370 TIM5_IRQHandler\r
 371 SPI3_IRQHandler\r
 372 UART4_IRQHandler\r
 373 UART5_IRQHandler\r
 374 TIM6_DAC_IRQHandler\r
 375 TIM7_IRQHandler\r
 376 DMA2_Channel1_IRQHandler\r
 377 DMA2_Channel2_IRQHandler\r
 378 DMA2_Channel3_IRQHandler\r
 379 DMA2_Channel4_IRQHandler\r
 380 DMA2_Channel5_IRQHandler\r
 381 DFSDM1_FLT0_IRQHandler\r
 382 DFSDM1_FLT1_IRQHandler\r
 383 DFSDM1_FLT2_IRQHandler\r
 384 COMP_IRQHandler\r
 385 LPTIM1_IRQHandler\r
 386 LPTIM2_IRQHandler\r
 387 OTG_FS_IRQHandler\r
 388 DMA2_Channel6_IRQHandler\r
 389 DMA2_Channel7_IRQHandler\r
 390 LPUART1_IRQHandler\r
 391 QUADSPI_IRQHandler\r
 392 I2C3_EV_IRQHandler\r
 393 I2C3_ER_IRQHandler\r
 394 SAI1_IRQHandler\r
 395 SAI2_IRQHandler\r
 396 SWPMI1_IRQHandler\r
 397 TSC_IRQHandler\r
 398 RNG_IRQHandler\r
 399 FPU_IRQHandler\r
 400 \r
 401                 B       .\r
 402 \r
 403                 ENDP\r
 404 \r
 405                 ALIGN\r
 406 \r
 407 ;*******************************************************************************\r
 408 ; User Stack and Heap initialization\r
 409 ;*******************************************************************************\r
 410                  IF      :DEF:__MICROLIB\r
 411 \r
 412                  EXPORT  __initial_sp\r
 413                  EXPORT  __heap_base\r
 414                  EXPORT  __heap_limit\r
 415 \r
 416                  ELSE\r
 417 \r
 418                  IMPORT  __use_two_region_memory\r
 419                  EXPORT  __user_initial_stackheap\r
 420 \r
 421 __user_initial_stackheap\r
 422 \r
 423                  LDR     R0, =  Heap_Mem\r
 424                  LDR     R1, =(Stack_Mem + Stack_Size)\r
 425                  LDR     R2, = (Heap_Mem +  Heap_Size)\r
 426                  LDR     R3, = Stack_Mem\r
 427                  BX      LR\r
 428 \r
 429                  ALIGN\r
 430 \r
 431                  ENDIF\r
 432 \r
 433                  END\r
 434 \r
 435 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****\r