1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
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5 * @date 22. June 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__clang__)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef __CORE_CM23_H_GENERIC
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32 #define __CORE_CM23_H_GENERIC
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41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 CMSIS violates the following MISRA-C:2004 rules:
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44 \li Required Rule 8.5, object/function definition in header file.<br>
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45 Function definitions in header files are used to allow 'inlining'.
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47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 Unions are used for effective representation of core registers.
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50 \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 Function-like macros are used to allow more efficient code.
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55 /*******************************************************************************
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57 ******************************************************************************/
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63 #include "cmsis_version.h"
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65 /* CMSIS definitions */
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66 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
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67 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
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68 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
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69 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
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71 #define __CORTEX_M (23U) /*!< Cortex-M Core */
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73 /** __FPU_USED indicates whether an FPU is used or not.
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74 This core does not support an FPU at all
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76 #define __FPU_USED 0U
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78 #if defined ( __CC_ARM )
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79 #if defined __TARGET_FPU_VFP
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80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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84 #if defined __ARM_PCS_VFP
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85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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88 #elif defined ( __GNUC__ )
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89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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93 #elif defined ( __ICCARM__ )
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94 #if defined __ARMVFP__
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95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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98 #elif defined ( __TI_ARM__ )
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99 #if defined __TI_VFP_SUPPORT__
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100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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103 #elif defined ( __TASKING__ )
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104 #if defined __FPU_VFP__
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105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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108 #elif defined ( __CSMC__ )
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109 #if ( __CSMC__ & 0x400U)
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110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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122 #endif /* __CORE_CM23_H_GENERIC */
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124 #ifndef __CMSIS_GENERIC
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126 #ifndef __CORE_CM23_H_DEPENDANT
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127 #define __CORE_CM23_H_DEPENDANT
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133 /* check device defines and use defaults */
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134 #if defined __CHECK_DEVICE_DEFINES
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136 #define __CM23_REV 0x0000U
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137 #warning "__CM23_REV not defined in device header file; using default!"
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140 #ifndef __FPU_PRESENT
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141 #define __FPU_PRESENT 0U
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142 #warning "__FPU_PRESENT not defined in device header file; using default!"
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145 #ifndef __MPU_PRESENT
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146 #define __MPU_PRESENT 0U
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147 #warning "__MPU_PRESENT not defined in device header file; using default!"
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150 #ifndef __SAUREGION_PRESENT
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151 #define __SAUREGION_PRESENT 0U
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152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
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155 #ifndef __VTOR_PRESENT
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156 #define __VTOR_PRESENT 0U
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157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
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160 #ifndef __NVIC_PRIO_BITS
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161 #define __NVIC_PRIO_BITS 2U
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162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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165 #ifndef __Vendor_SysTickConfig
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166 #define __Vendor_SysTickConfig 0U
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167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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170 #ifndef __ETM_PRESENT
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171 #define __ETM_PRESENT 0U
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172 #warning "__ETM_PRESENT not defined in device header file; using default!"
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175 #ifndef __MTB_PRESENT
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176 #define __MTB_PRESENT 0U
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177 #warning "__MTB_PRESENT not defined in device header file; using default!"
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182 /* IO definitions (access restrictions to peripheral registers) */
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184 \defgroup CMSIS_glob_defs CMSIS Global Defines
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186 <strong>IO Type Qualifiers</strong> are used
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187 \li to specify the access to peripheral variables.
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188 \li for automatic generation of peripheral register debug information.
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191 #define __I volatile /*!< Defines 'read only' permissions */
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193 #define __I volatile const /*!< Defines 'read only' permissions */
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195 #define __O volatile /*!< Defines 'write only' permissions */
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196 #define __IO volatile /*!< Defines 'read / write' permissions */
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198 /* following defines should be used for structure members */
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199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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200 #define __OM volatile /*! Defines 'write only' structure member permissions */
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201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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203 /*@} end of group Cortex_M23 */
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207 /*******************************************************************************
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208 * Register Abstraction
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209 Core Register contain:
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211 - Core NVIC Register
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212 - Core SCB Register
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213 - Core SysTick Register
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214 - Core Debug Register
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215 - Core MPU Register
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216 - Core SAU Register
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217 ******************************************************************************/
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219 \defgroup CMSIS_core_register Defines and Type Definitions
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220 \brief Type definitions and defines for Cortex-M processor based devices.
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224 \ingroup CMSIS_core_register
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225 \defgroup CMSIS_CORE Status and Control Registers
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226 \brief Core Register type definitions.
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231 \brief Union type to access the Application Program Status Register (APSR).
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237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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242 } b; /*!< Structure used for bit access */
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243 uint32_t w; /*!< Type used for word access */
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246 /* APSR Register Definitions */
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247 #define APSR_N_Pos 31U /*!< APSR: N Position */
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248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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253 #define APSR_C_Pos 29U /*!< APSR: C Position */
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254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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256 #define APSR_V_Pos 28U /*!< APSR: V Position */
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257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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261 \brief Union type to access the Interrupt Program Status Register (IPSR).
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267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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269 } b; /*!< Structure used for bit access */
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270 uint32_t w; /*!< Type used for word access */
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273 /* IPSR Register Definitions */
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274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
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289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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293 } b; /*!< Structure used for bit access */
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294 uint32_t w; /*!< Type used for word access */
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297 /* xPSR Register Definitions */
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298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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318 \brief Union type to access the Control Registers (CONTROL).
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324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
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326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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327 } b; /*!< Structure used for bit access */
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328 uint32_t w; /*!< Type used for word access */
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331 /* CONTROL Register Definitions */
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332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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338 /*@} end of group CMSIS_CORE */
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342 \ingroup CMSIS_core_register
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343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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344 \brief Type definitions for the NVIC Registers
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349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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354 uint32_t RESERVED0[16U];
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355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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356 uint32_t RSERVED1[16U];
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357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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358 uint32_t RESERVED2[16U];
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359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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360 uint32_t RESERVED3[16U];
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361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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362 uint32_t RESERVED4[16U];
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363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
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364 uint32_t RESERVED5[16U];
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365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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368 /*@} end of group CMSIS_NVIC */
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372 \ingroup CMSIS_core_register
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373 \defgroup CMSIS_SCB System Control Block (SCB)
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374 \brief Type definitions for the System Control Block Registers
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379 \brief Structure type to access the System Control Block (SCB).
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383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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388 uint32_t RESERVED0;
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390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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393 uint32_t RESERVED1;
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394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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398 /* SCB CPUID Register Definitions */
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399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
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400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
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403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
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406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
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409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
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412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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414 /* SCB Interrupt Control State Register Definitions */
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415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
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416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
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418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
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419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
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421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
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422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
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424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
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428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
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437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
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439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
\r
440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
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443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
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446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
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449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
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451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
\r
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
455 /* SCB Vector Table Offset Register Definitions */
\r
456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
\r
457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
460 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
\r
462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
\r
468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
\r
471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
\r
473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
\r
474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
\r
476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
\r
477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
\r
479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
\r
480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
485 /* SCB System Control Register Definitions */
\r
486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
\r
487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
\r
490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
\r
492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
\r
493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
\r
496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
498 /* SCB Configuration Control Register Definitions */
\r
499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
\r
500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
\r
502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
\r
503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
\r
505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
\r
506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
\r
508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
\r
509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
\r
511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
\r
512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
\r
515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
\r
518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
\r
521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
523 /* SCB System Handler Control and State Register Definitions */
\r
524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
\r
525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
\r
527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
\r
528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
\r
531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
\r
534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
\r
537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
\r
540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
\r
542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
\r
543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
\r
545 /*@} end of group CMSIS_SCB */
\r
549 \ingroup CMSIS_core_register
\r
550 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
551 \brief Type definitions for the System Timer Registers.
\r
556 \brief Structure type to access the System Timer (SysTick).
\r
560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
566 /* SysTick Control / Status Register Definitions */
\r
567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
\r
568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
\r
571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
\r
574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
\r
577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
579 /* SysTick Reload Register Definitions */
\r
580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
\r
581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
583 /* SysTick Current Register Definitions */
\r
584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
\r
585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
587 /* SysTick Calibration Register Definitions */
\r
588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
\r
589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
\r
592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
\r
595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
597 /*@} end of group CMSIS_SysTick */
\r
601 \ingroup CMSIS_core_register
\r
602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
603 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
613 uint32_t RESERVED0[6U];
\r
614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
616 uint32_t RESERVED1[1U];
\r
617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
618 uint32_t RESERVED2[1U];
\r
619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
620 uint32_t RESERVED3[1U];
\r
621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
622 uint32_t RESERVED4[1U];
\r
623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
624 uint32_t RESERVED5[1U];
\r
625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
626 uint32_t RESERVED6[1U];
\r
627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
628 uint32_t RESERVED7[1U];
\r
629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
630 uint32_t RESERVED8[1U];
\r
631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
\r
632 uint32_t RESERVED9[1U];
\r
633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
\r
634 uint32_t RESERVED10[1U];
\r
635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
\r
636 uint32_t RESERVED11[1U];
\r
637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
\r
638 uint32_t RESERVED12[1U];
\r
639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
\r
640 uint32_t RESERVED13[1U];
\r
641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
\r
642 uint32_t RESERVED14[1U];
\r
643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
\r
644 uint32_t RESERVED15[1U];
\r
645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
\r
646 uint32_t RESERVED16[1U];
\r
647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
\r
648 uint32_t RESERVED17[1U];
\r
649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
\r
650 uint32_t RESERVED18[1U];
\r
651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
\r
652 uint32_t RESERVED19[1U];
\r
653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
\r
654 uint32_t RESERVED20[1U];
\r
655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
\r
656 uint32_t RESERVED21[1U];
\r
657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
\r
658 uint32_t RESERVED22[1U];
\r
659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
\r
660 uint32_t RESERVED23[1U];
\r
661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
\r
662 uint32_t RESERVED24[1U];
\r
663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
\r
664 uint32_t RESERVED25[1U];
\r
665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
\r
666 uint32_t RESERVED26[1U];
\r
667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
\r
668 uint32_t RESERVED27[1U];
\r
669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
\r
670 uint32_t RESERVED28[1U];
\r
671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
\r
672 uint32_t RESERVED29[1U];
\r
673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
\r
674 uint32_t RESERVED30[1U];
\r
675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
\r
676 uint32_t RESERVED31[1U];
\r
677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
\r
680 /* DWT Control Register Definitions */
\r
681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
\r
682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
\r
685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
\r
688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
\r
691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
\r
694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
696 /* DWT Comparator Function Register Definitions */
\r
697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
\r
698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
\r
700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
\r
701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
\r
704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
\r
707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
\r
709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
\r
710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
\r
712 /*@}*/ /* end of group CMSIS_DWT */
\r
716 \ingroup CMSIS_core_register
\r
717 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
718 \brief Type definitions for the Trace Port Interface (TPI)
\r
723 \brief Structure type to access the Trace Port Interface Register (TPI).
\r
727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
729 uint32_t RESERVED0[2U];
\r
730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
731 uint32_t RESERVED1[55U];
\r
732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
733 uint32_t RESERVED2[131U];
\r
734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
\r
737 uint32_t RESERVED3[759U];
\r
738 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
\r
739 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
\r
740 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
\r
741 uint32_t RESERVED4[1U];
\r
742 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
\r
743 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
\r
744 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
745 uint32_t RESERVED5[39U];
\r
746 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
747 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
748 uint32_t RESERVED7[8U];
\r
749 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
\r
750 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
\r
753 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
754 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
\r
755 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
757 /* TPI Selected Pin Protocol Register Definitions */
\r
758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
\r
759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
761 /* TPI Formatter and Flush Status Register Definitions */
\r
762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
\r
763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
\r
766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
\r
769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
\r
772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
774 /* TPI Formatter and Flush Control Register Definitions */
\r
775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
\r
776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
778 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
\r
779 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
\r
781 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
\r
782 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
784 /* TPI TRIGGER Register Definitions */
\r
785 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
\r
786 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
788 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
\r
789 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
\r
790 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
\r
792 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
\r
793 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
\r
795 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
\r
796 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
\r
798 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
\r
799 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
\r
801 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
\r
802 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
\r
804 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
\r
805 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
\r
807 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
\r
808 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
\r
810 /* TPI Integration Test ATB Control Register 2 Register Definitions */
\r
811 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
\r
812 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
\r
814 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
\r
815 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
\r
817 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
\r
818 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
\r
820 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
\r
821 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
\r
823 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
\r
824 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
\r
825 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
\r
827 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
\r
828 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
\r
830 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
\r
831 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
\r
833 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
\r
834 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
\r
836 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
\r
837 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
\r
839 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
\r
840 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
\r
842 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
\r
843 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
\r
845 /* TPI Integration Test ATB Control Register 0 Definitions */
\r
846 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
\r
847 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
\r
849 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
\r
850 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
\r
852 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
\r
853 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
\r
855 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
\r
856 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
\r
858 /* TPI Integration Mode Control Register Definitions */
\r
859 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
\r
860 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
862 /* TPI DEVID Register Definitions */
\r
863 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
\r
864 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
866 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
\r
867 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
869 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
\r
870 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
872 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
\r
873 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
\r
875 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
\r
876 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
878 /* TPI DEVTYPE Register Definitions */
\r
879 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
\r
880 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
882 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
\r
883 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
885 /*@}*/ /* end of group CMSIS_TPI */
\r
888 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
890 \ingroup CMSIS_core_register
\r
891 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
892 \brief Type definitions for the Memory Protection Unit (MPU)
\r
897 \brief Structure type to access the Memory Protection Unit (MPU).
\r
901 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
903 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
\r
904 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
905 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
\r
906 uint32_t RESERVED0[7U];
\r
908 __IOM uint32_t MAIR[2];
\r
910 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
\r
911 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
\r
916 #define MPU_TYPE_RALIASES 1U
\r
918 /* MPU Type Register Definitions */
\r
919 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
\r
920 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
922 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
\r
923 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
925 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
\r
926 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
928 /* MPU Control Register Definitions */
\r
929 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
\r
930 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
932 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
\r
933 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
935 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
\r
936 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
938 /* MPU Region Number Register Definitions */
\r
939 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
\r
940 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
942 /* MPU Region Base Address Register Definitions */
\r
943 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
\r
944 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
\r
946 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
\r
947 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
\r
949 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
\r
950 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
\r
952 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
\r
953 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
\r
955 /* MPU Region Limit Address Register Definitions */
\r
956 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
\r
957 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
\r
959 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
\r
960 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
\r
962 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
\r
963 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
\r
965 /* MPU Memory Attribute Indirection Register 0 Definitions */
\r
966 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
\r
967 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
\r
969 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
\r
970 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
\r
972 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
\r
973 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
\r
975 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
\r
976 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
\r
978 /* MPU Memory Attribute Indirection Register 1 Definitions */
\r
979 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
\r
980 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
\r
982 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
\r
983 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
\r
985 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
\r
986 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
\r
988 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
\r
989 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
\r
991 /*@} end of group CMSIS_MPU */
\r
995 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
997 \ingroup CMSIS_core_register
\r
998 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
\r
999 \brief Type definitions for the Security Attribution Unit (SAU)
\r
1004 \brief Structure type to access the Security Attribution Unit (SAU).
\r
1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
\r
1009 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
\r
1010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
1011 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
\r
1012 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
\r
1013 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
\r
1017 /* SAU Control Register Definitions */
\r
1018 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
\r
1019 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
\r
1021 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
\r
1022 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
\r
1024 /* SAU Type Register Definitions */
\r
1025 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
\r
1026 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
\r
1028 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
1029 /* SAU Region Number Register Definitions */
\r
1030 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
\r
1031 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
\r
1033 /* SAU Region Base Address Register Definitions */
\r
1034 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
\r
1035 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
\r
1037 /* SAU Region Limit Address Register Definitions */
\r
1038 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
\r
1039 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
\r
1041 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
\r
1042 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
\r
1044 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
\r
1045 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
\r
1047 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
\r
1049 /*@} end of group CMSIS_SAU */
\r
1050 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1054 \ingroup CMSIS_core_register
\r
1055 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1056 \brief Type definitions for the Core Debug Registers
\r
1061 \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1065 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1066 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1067 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1068 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1069 uint32_t RESERVED4[1U];
\r
1070 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
\r
1071 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
\r
1074 /* Debug Halting Control and Status Register Definitions */
\r
1075 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1076 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
\r
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
\r
1081 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1082 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1084 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1085 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1087 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1088 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1090 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1091 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1093 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
\r
1094 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1096 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1097 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1099 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1100 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1102 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
\r
1103 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1105 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
\r
1106 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1108 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1109 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1111 /* Debug Core Register Selector Register Definitions */
\r
1112 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
\r
1113 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1115 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
\r
1116 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1118 /* Debug Exception and Monitor Control Register */
\r
1119 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
\r
1120 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
\r
1122 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1123 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1125 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1126 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1128 /* Debug Authentication Control Register Definitions */
\r
1129 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
\r
1130 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
\r
1132 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
\r
1133 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
\r
1135 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
\r
1136 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
\r
1138 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
\r
1139 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
\r
1141 /* Debug Security Control and Status Register Definitions */
\r
1142 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
\r
1143 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
\r
1145 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
\r
1146 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
\r
1148 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
\r
1149 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
\r
1151 /*@} end of group CMSIS_CoreDebug */
\r
1155 \ingroup CMSIS_core_register
\r
1156 \defgroup CMSIS_core_bitfield Core register bit field macros
\r
1157 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
\r
1162 \brief Mask and shift a bit field value for use in a register bit range.
\r
1163 \param[in] field Name of the register bit field.
\r
1164 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\r
1165 \return Masked and shifted value.
\r
1167 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
\r
1170 \brief Mask and shift a register value to extract a bit filed value.
\r
1171 \param[in] field Name of the register bit field.
\r
1172 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\r
1173 \return Masked and shifted bit field value.
\r
1175 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
\r
1177 /*@} end of group CMSIS_core_bitfield */
\r
1181 \ingroup CMSIS_core_register
\r
1182 \defgroup CMSIS_core_base Core Definitions
\r
1183 \brief Definitions for base addresses, unions, and structures.
\r
1187 /* Memory mapping of Core Hardware */
\r
1188 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1189 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1190 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1191 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1192 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1193 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1194 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1197 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1198 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1199 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1200 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1201 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1202 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
\r
1204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1205 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1206 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1209 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1210 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
\r
1211 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
\r
1214 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1215 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
\r
1216 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
\r
1217 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
\r
1218 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
\r
1219 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
\r
1221 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
\r
1222 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
\r
1223 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
\r
1224 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
\r
1226 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1227 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
\r
1228 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
\r
1231 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1236 /*******************************************************************************
\r
1237 * Hardware Abstraction Layer
\r
1238 Core Function Interface contains:
\r
1239 - Core NVIC Functions
\r
1240 - Core SysTick Functions
\r
1241 - Core Register Access Functions
\r
1242 ******************************************************************************/
\r
1244 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1249 /* ########################## NVIC functions #################################### */
\r
1251 \ingroup CMSIS_Core_FunctionInterface
\r
1252 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1253 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1257 #ifdef CMSIS_NVIC_VIRTUAL
\r
1258 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1259 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
\r
1261 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1263 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
\r
1264 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
\r
1265 #define NVIC_EnableIRQ __NVIC_EnableIRQ
\r
1266 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
\r
1267 #define NVIC_DisableIRQ __NVIC_DisableIRQ
\r
1268 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
\r
1269 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
\r
1270 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
\r
1271 #define NVIC_GetActive __NVIC_GetActive
\r
1272 #define NVIC_SetPriority __NVIC_SetPriority
\r
1273 #define NVIC_GetPriority __NVIC_GetPriority
\r
1274 #define NVIC_SystemReset __NVIC_SystemReset
\r
1275 #endif /* CMSIS_NVIC_VIRTUAL */
\r
1277 #ifdef CMSIS_VECTAB_VIRTUAL
\r
1278 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1279 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
\r
1281 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1283 #define NVIC_SetVector __NVIC_SetVector
\r
1284 #define NVIC_GetVector __NVIC_GetVector
\r
1285 #endif /* (CMSIS_VECTAB_VIRTUAL) */
\r
1287 #define NVIC_USER_IRQ_OFFSET 16
\r
1290 /* Special LR values for Secure/Non-Secure call handling and exception handling */
\r
1292 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
\r
1293 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
\r
1295 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
\r
1296 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
\r
1297 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
\r
1298 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
\r
1299 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
\r
1300 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
\r
1301 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
\r
1302 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
\r
1304 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
\r
1305 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
\r
1306 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
\r
1308 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
\r
1312 /* Interrupt Priorities are WORD accessible only under Armv6-M */
\r
1313 /* The following MACROS handle generation of the register offset and byte masks */
\r
1314 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
\r
1315 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
\r
1316 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
\r
1318 #define __NVIC_SetPriorityGrouping(X) (void)(X)
\r
1319 #define __NVIC_GetPriorityGrouping() (0U)
\r
1322 \brief Enable Interrupt
\r
1323 \details Enables a device specific interrupt in the NVIC interrupt controller.
\r
1324 \param [in] IRQn Device specific interrupt number.
\r
1325 \note IRQn must not be negative.
\r
1327 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1329 if ((int32_t)(IRQn) >= 0)
\r
1331 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1337 \brief Get Interrupt Enable status
\r
1338 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\r
1339 \param [in] IRQn Device specific interrupt number.
\r
1340 \return 0 Interrupt is not enabled.
\r
1341 \return 1 Interrupt is enabled.
\r
1342 \note IRQn must not be negative.
\r
1344 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
\r
1346 if ((int32_t)(IRQn) >= 0)
\r
1348 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1358 \brief Disable Interrupt
\r
1359 \details Disables a device specific interrupt in the NVIC interrupt controller.
\r
1360 \param [in] IRQn Device specific interrupt number.
\r
1361 \note IRQn must not be negative.
\r
1363 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1365 if ((int32_t)(IRQn) >= 0)
\r
1367 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1375 \brief Get Pending Interrupt
\r
1376 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\r
1377 \param [in] IRQn Device specific interrupt number.
\r
1378 \return 0 Interrupt status is not pending.
\r
1379 \return 1 Interrupt status is pending.
\r
1380 \note IRQn must not be negative.
\r
1382 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1384 if ((int32_t)(IRQn) >= 0)
\r
1386 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1396 \brief Set Pending Interrupt
\r
1397 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\r
1398 \param [in] IRQn Device specific interrupt number.
\r
1399 \note IRQn must not be negative.
\r
1401 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1403 if ((int32_t)(IRQn) >= 0)
\r
1405 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1411 \brief Clear Pending Interrupt
\r
1412 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\r
1413 \param [in] IRQn Device specific interrupt number.
\r
1414 \note IRQn must not be negative.
\r
1416 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1418 if ((int32_t)(IRQn) >= 0)
\r
1420 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1426 \brief Get Active Interrupt
\r
1427 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\r
1428 \param [in] IRQn Device specific interrupt number.
\r
1429 \return 0 Interrupt status is not active.
\r
1430 \return 1 Interrupt status is active.
\r
1431 \note IRQn must not be negative.
\r
1433 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\r
1435 if ((int32_t)(IRQn) >= 0)
\r
1437 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1446 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1448 \brief Get Interrupt Target State
\r
1449 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1450 \param [in] IRQn Device specific interrupt number.
\r
1451 \return 0 if interrupt is assigned to Secure
\r
1452 \return 1 if interrupt is assigned to Non Secure
\r
1453 \note IRQn must not be negative.
\r
1455 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
\r
1457 if ((int32_t)(IRQn) >= 0)
\r
1459 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1469 \brief Set Interrupt Target State
\r
1470 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1471 \param [in] IRQn Device specific interrupt number.
\r
1472 \return 0 if interrupt is assigned to Secure
\r
1473 1 if interrupt is assigned to Non Secure
\r
1474 \note IRQn must not be negative.
\r
1476 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
\r
1478 if ((int32_t)(IRQn) >= 0)
\r
1480 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
1481 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1491 \brief Clear Interrupt Target State
\r
1492 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1493 \param [in] IRQn Device specific interrupt number.
\r
1494 \return 0 if interrupt is assigned to Secure
\r
1495 1 if interrupt is assigned to Non Secure
\r
1496 \note IRQn must not be negative.
\r
1498 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
\r
1500 if ((int32_t)(IRQn) >= 0)
\r
1502 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
1503 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1510 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1514 \brief Set Interrupt Priority
\r
1515 \details Sets the priority of a device specific interrupt or a processor exception.
\r
1516 The interrupt number can be positive to specify a device specific interrupt,
\r
1517 or negative to specify a processor exception.
\r
1518 \param [in] IRQn Interrupt number.
\r
1519 \param [in] priority Priority to set.
\r
1520 \note The priority cannot be set for every processor exception.
\r
1522 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1524 if ((int32_t)(IRQn) >= 0)
\r
1526 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1527 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1531 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1532 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1538 \brief Get Interrupt Priority
\r
1539 \details Reads the priority of a device specific interrupt or a processor exception.
\r
1540 The interrupt number can be positive to specify a device specific interrupt,
\r
1541 or negative to specify a processor exception.
\r
1542 \param [in] IRQn Interrupt number.
\r
1543 \return Interrupt Priority.
\r
1544 Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
1546 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\r
1549 if ((int32_t)(IRQn) >= 0)
\r
1551 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1555 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1561 \brief Encode Priority
\r
1562 \details Encodes the priority for an interrupt with the given priority group,
\r
1563 preemptive priority value, and subpriority value.
\r
1564 In case of a conflict between priority grouping and available
\r
1565 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1566 \param [in] PriorityGroup Used priority group.
\r
1567 \param [in] PreemptPriority Preemptive priority value (starting from 0).
\r
1568 \param [in] SubPriority Subpriority value (starting from 0).
\r
1569 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
\r
1571 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
1573 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1574 uint32_t PreemptPriorityBits;
\r
1575 uint32_t SubPriorityBits;
\r
1577 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
1578 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
1581 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
\r
1582 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
\r
1588 \brief Decode Priority
\r
1589 \details Decodes an interrupt priority value with a given priority group to
\r
1590 preemptive priority value and subpriority value.
\r
1591 In case of a conflict between priority grouping and available
\r
1592 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
1593 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\r
1594 \param [in] PriorityGroup Used priority group.
\r
1595 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\r
1596 \param [out] pSubPriority Subpriority value (starting from 0).
\r
1598 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
\r
1600 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1601 uint32_t PreemptPriorityBits;
\r
1602 uint32_t SubPriorityBits;
\r
1604 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
1605 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
1607 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
\r
1608 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
\r
1613 \brief Set Interrupt Vector
\r
1614 \details Sets an interrupt vector in SRAM based interrupt vector table.
\r
1615 The interrupt number can be positive to specify a device specific interrupt,
\r
1616 or negative to specify a processor exception.
\r
1617 VTOR must been relocated to SRAM before.
\r
1618 If VTOR is not present address 0 must be mapped to SRAM.
\r
1619 \param [in] IRQn Interrupt number
\r
1620 \param [in] vector Address of interrupt handler function
\r
1622 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\r
1624 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
1625 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
1627 uint32_t *vectors = (uint32_t *)0x0U;
\r
1629 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
\r
1634 \brief Get Interrupt Vector
\r
1635 \details Reads an interrupt vector from interrupt vector table.
\r
1636 The interrupt number can be positive to specify a device specific interrupt,
\r
1637 or negative to specify a processor exception.
\r
1638 \param [in] IRQn Interrupt number.
\r
1639 \return Address of interrupt handler function
\r
1641 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
\r
1643 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
1644 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
1646 uint32_t *vectors = (uint32_t *)0x0U;
\r
1648 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
\r
1653 \brief System Reset
\r
1654 \details Initiates a system reset request to reset the MCU.
\r
1656 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
\r
1658 __DSB(); /* Ensure all outstanding memory accesses included
\r
1659 buffered write are completed before reset */
\r
1660 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
1661 SCB_AIRCR_SYSRESETREQ_Msk);
\r
1662 __DSB(); /* Ensure completion of memory access */
\r
1664 for(;;) /* wait until reset */
\r
1670 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1672 \brief Enable Interrupt (non-secure)
\r
1673 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\r
1674 \param [in] IRQn Device specific interrupt number.
\r
1675 \note IRQn must not be negative.
\r
1677 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
\r
1679 if ((int32_t)(IRQn) >= 0)
\r
1681 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1687 \brief Get Interrupt Enable status (non-secure)
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1688 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
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1689 \param [in] IRQn Device specific interrupt number.
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1690 \return 0 Interrupt is not enabled.
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1691 \return 1 Interrupt is enabled.
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1692 \note IRQn must not be negative.
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1694 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
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1696 if ((int32_t)(IRQn) >= 0)
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1698 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1708 \brief Disable Interrupt (non-secure)
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1709 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
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1710 \param [in] IRQn Device specific interrupt number.
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1711 \note IRQn must not be negative.
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1713 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
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1715 if ((int32_t)(IRQn) >= 0)
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1717 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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1723 \brief Get Pending Interrupt (non-secure)
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1724 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
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1725 \param [in] IRQn Device specific interrupt number.
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1726 \return 0 Interrupt status is not pending.
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1727 \return 1 Interrupt status is pending.
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1728 \note IRQn must not be negative.
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1730 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
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1732 if ((int32_t)(IRQn) >= 0)
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1734 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1744 \brief Set Pending Interrupt (non-secure)
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1745 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
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1746 \param [in] IRQn Device specific interrupt number.
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1747 \note IRQn must not be negative.
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1749 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
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1751 if ((int32_t)(IRQn) >= 0)
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1753 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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1759 \brief Clear Pending Interrupt (non-secure)
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1760 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
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1761 \param [in] IRQn Device specific interrupt number.
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1762 \note IRQn must not be negative.
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1764 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
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1766 if ((int32_t)(IRQn) >= 0)
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1768 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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1774 \brief Get Active Interrupt (non-secure)
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1775 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
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1776 \param [in] IRQn Device specific interrupt number.
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1777 \return 0 Interrupt status is not active.
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1778 \return 1 Interrupt status is active.
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1779 \note IRQn must not be negative.
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1781 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
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1783 if ((int32_t)(IRQn) >= 0)
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1785 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1795 \brief Set Interrupt Priority (non-secure)
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1796 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
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1797 The interrupt number can be positive to specify a device specific interrupt,
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1798 or negative to specify a processor exception.
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1799 \param [in] IRQn Interrupt number.
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1800 \param [in] priority Priority to set.
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1801 \note The priority cannot be set for every non-secure processor exception.
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1803 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
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1805 if ((int32_t)(IRQn) >= 0)
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1807 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
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1808 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
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1812 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
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1813 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
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1819 \brief Get Interrupt Priority (non-secure)
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1820 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
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1821 The interrupt number can be positive to specify a device specific interrupt,
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1822 or negative to specify a processor exception.
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1823 \param [in] IRQn Interrupt number.
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1824 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
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1826 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
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1829 if ((int32_t)(IRQn) >= 0)
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1831 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
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1835 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
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1838 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
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1840 /*@} end of CMSIS_Core_NVICFunctions */
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1842 /* ########################## MPU functions #################################### */
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1844 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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1846 #include "mpu_armv8.h"
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1850 /* ########################## FPU functions #################################### */
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1852 \ingroup CMSIS_Core_FunctionInterface
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1853 \defgroup CMSIS_Core_FpuFunctions FPU Functions
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1854 \brief Function that provides FPU type.
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1859 \brief get FPU type
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1860 \details returns the FPU type
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1863 - \b 1: Single precision FPU
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1864 - \b 2: Double + Single precision FPU
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1866 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
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1868 return 0U; /* No FPU */
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1872 /*@} end of CMSIS_Core_FpuFunctions */
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1876 /* ########################## SAU functions #################################### */
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1878 \ingroup CMSIS_Core_FunctionInterface
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1879 \defgroup CMSIS_Core_SAUFunctions SAU Functions
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1880 \brief Functions that configure the SAU.
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1884 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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1888 \details Enables the Security Attribution Unit (SAU).
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1890 __STATIC_INLINE void TZ_SAU_Enable(void)
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1892 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
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1898 \brief Disable SAU
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1899 \details Disables the Security Attribution Unit (SAU).
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1901 __STATIC_INLINE void TZ_SAU_Disable(void)
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1903 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
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1906 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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1908 /*@} end of CMSIS_Core_SAUFunctions */
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1913 /* ################################## SysTick function ############################################ */
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1915 \ingroup CMSIS_Core_FunctionInterface
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1916 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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1917 \brief Functions that configure the System.
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1921 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
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1924 \brief System Tick Configuration
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1925 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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1926 Counter is in free running mode to generate periodic interrupts.
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1927 \param [in] ticks Number of ticks between two interrupts.
\r
1928 \return 0 Function succeeded.
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1929 \return 1 Function failed.
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1930 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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1931 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1932 must contain a vendor-specific implementation of this function.
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1934 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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1936 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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1938 return (1UL); /* Reload value impossible */
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1941 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1942 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1943 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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1944 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1945 SysTick_CTRL_TICKINT_Msk |
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1946 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1947 return (0UL); /* Function successful */
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1950 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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1952 \brief System Tick Configuration (non-secure)
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1953 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
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1954 Counter is in free running mode to generate periodic interrupts.
\r
1955 \param [in] ticks Number of ticks between two interrupts.
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1956 \return 0 Function succeeded.
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1957 \return 1 Function failed.
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1958 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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1959 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1960 must contain a vendor-specific implementation of this function.
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1963 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
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1965 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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1967 return (1UL); /* Reload value impossible */
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1970 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1971 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1972 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
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1973 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1974 SysTick_CTRL_TICKINT_Msk |
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1975 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1976 return (0UL); /* Function successful */
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1978 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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1982 /*@} end of CMSIS_Core_SysTickFunctions */
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1987 #ifdef __cplusplus
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1991 #endif /* __CORE_CM23_H_DEPENDANT */
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1993 #endif /* __CMSIS_GENERIC */
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projects / freertos / blob