2 ******************************************************************************
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3 * @file stm32_hal_legacy.h
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4 * @author MCD Application Team
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5 * @brief This file contains aliases definition for the STM32Cube HAL constants
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6 * macros and functions maintained for legacy purpose.
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7 ******************************************************************************
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10 * <h2><center>© Copyright (c) 2018 STMicroelectronics.
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11 * All rights reserved.</center></h2>
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13 * This software component is licensed by ST under BSD 3-Clause license,
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14 * the "License"; You may not use this file except in compliance with the
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15 * License. You may obtain a copy of the License at:
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16 * opensource.org/licenses/BSD-3-Clause
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18 ******************************************************************************
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef STM32_HAL_LEGACY
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23 #define STM32_HAL_LEGACY
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29 /* Includes ------------------------------------------------------------------*/
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30 /* Exported types ------------------------------------------------------------*/
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31 /* Exported constants --------------------------------------------------------*/
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33 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
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36 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
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37 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
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38 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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39 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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40 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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46 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
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49 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
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50 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
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51 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
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52 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
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53 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
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54 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
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55 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
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56 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
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57 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
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58 #define REGULAR_GROUP ADC_REGULAR_GROUP
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59 #define INJECTED_GROUP ADC_INJECTED_GROUP
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60 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
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61 #define AWD_EVENT ADC_AWD_EVENT
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62 #define AWD1_EVENT ADC_AWD1_EVENT
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63 #define AWD2_EVENT ADC_AWD2_EVENT
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64 #define AWD3_EVENT ADC_AWD3_EVENT
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65 #define OVR_EVENT ADC_OVR_EVENT
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66 #define JQOVF_EVENT ADC_JQOVF_EVENT
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67 #define ALL_CHANNELS ADC_ALL_CHANNELS
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68 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
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69 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
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70 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
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71 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
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72 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
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73 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
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74 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
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75 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
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76 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
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77 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
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78 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
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79 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
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80 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
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81 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
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82 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
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83 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
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84 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
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85 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
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86 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
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87 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
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88 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
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90 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
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91 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
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92 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
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93 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
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94 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
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95 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
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96 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
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98 #if defined(STM32H7)
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99 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
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100 #endif /* STM32H7 */
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105 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
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109 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
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115 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
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118 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
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119 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
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120 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
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121 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
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122 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
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123 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
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124 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
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125 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
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126 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
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127 #if defined(STM32L0)
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128 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
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130 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
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131 #if defined(STM32F373xC) || defined(STM32F378xx)
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132 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
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133 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
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134 #endif /* STM32F373xC || STM32F378xx */
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136 #if defined(STM32L0) || defined(STM32L4)
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137 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
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139 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
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140 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
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141 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
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142 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
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143 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
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144 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
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146 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
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147 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
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148 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
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149 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
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150 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
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151 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
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152 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
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153 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
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154 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
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155 #if defined(STM32L0)
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156 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
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157 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
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158 /* to the second dedicated IO (only for COMP2). */
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159 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
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160 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
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162 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
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163 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
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165 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
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166 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
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168 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
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169 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
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171 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
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172 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
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173 #if defined(COMP_CSR_LOCK)
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174 #define COMP_FLAG_LOCK COMP_CSR_LOCK
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175 #elif defined(COMP_CSR_COMP1LOCK)
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176 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
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177 #elif defined(COMP_CSR_COMPxLOCK)
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178 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
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181 #if defined(STM32L4)
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182 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
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183 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
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184 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
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185 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
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186 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
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187 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
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188 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
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191 #if defined(STM32L0)
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192 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
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193 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
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195 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
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196 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
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197 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
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198 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
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206 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
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209 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
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214 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
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218 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
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219 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
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225 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
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229 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
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230 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
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231 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
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232 #define DAC_WAVE_NONE 0x00000000U
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233 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0
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234 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
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235 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
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236 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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237 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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239 #if defined(STM32G4)
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240 #define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
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241 #define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
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244 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5)
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245 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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246 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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253 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
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256 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
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257 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
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258 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
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259 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
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260 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
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261 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
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262 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
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263 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
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264 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
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265 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
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266 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
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267 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
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268 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
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269 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
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271 #define IS_HAL_REMAPDMA IS_DMA_REMAP
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272 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
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273 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
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275 #if defined(STM32L4)
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277 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
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278 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
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279 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
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280 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
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281 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
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282 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
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283 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
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284 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
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285 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
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286 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
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287 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
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288 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
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289 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
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290 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
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291 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
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292 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
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293 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
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294 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
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295 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
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296 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
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297 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
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298 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
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299 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
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300 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
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301 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
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302 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
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304 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
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305 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
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306 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
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307 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
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309 #endif /* STM32L4 */
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311 #if defined(STM32H7)
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313 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
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314 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
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316 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
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317 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
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319 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
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320 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
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321 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
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322 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
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323 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
\r
324 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
\r
325 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
\r
326 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
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328 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
\r
329 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
\r
330 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
\r
331 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
\r
332 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
\r
333 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
\r
334 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
\r
335 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
\r
336 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
\r
337 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
\r
338 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
\r
339 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
\r
340 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
\r
341 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
\r
342 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
\r
343 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
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344 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
\r
345 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
\r
346 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
\r
347 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
\r
348 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
\r
349 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
\r
350 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
\r
351 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
\r
352 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
\r
353 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
\r
354 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
\r
355 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
\r
356 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
\r
357 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
\r
359 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
\r
360 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
\r
361 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
\r
362 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
\r
364 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
\r
365 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
\r
366 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
\r
368 #endif /* STM32H7 */
\r
374 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
\r
378 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
\r
379 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
\r
380 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
\r
381 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
\r
382 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
\r
383 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
\r
384 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
\r
385 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
\r
386 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
\r
387 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
\r
388 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
\r
389 #define OBEX_PCROP OPTIONBYTE_PCROP
\r
390 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
\r
391 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
\r
392 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
\r
393 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
\r
394 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
\r
395 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
\r
396 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
\r
397 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
\r
398 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
\r
399 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
\r
400 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
\r
401 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
\r
402 #define PAGESIZE FLASH_PAGE_SIZE
\r
403 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
\r
404 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
\r
405 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
\r
406 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
\r
407 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
\r
408 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
\r
409 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
\r
410 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
\r
411 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
\r
412 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
\r
413 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
\r
414 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
\r
415 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
\r
416 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
\r
417 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
\r
418 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
\r
419 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
\r
420 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
\r
421 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
\r
422 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
\r
423 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
\r
424 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
\r
425 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
\r
426 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
\r
427 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
\r
428 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
\r
429 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
\r
430 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
\r
431 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
\r
432 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
\r
433 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
\r
434 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
\r
435 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
\r
436 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
\r
437 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
\r
438 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
\r
439 #define OB_WDG_SW OB_IWDG_SW
\r
440 #define OB_WDG_HW OB_IWDG_HW
\r
441 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
\r
442 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
\r
443 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
\r
444 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
\r
445 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
\r
446 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
\r
447 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
\r
448 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
\r
449 #if defined(STM32G0)
\r
450 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
\r
451 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
\r
453 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
\r
454 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
\r
456 #if defined(STM32H7)
\r
457 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
\r
458 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
\r
459 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
\r
460 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
\r
461 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
\r
462 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
\r
469 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
\r
473 #if defined(STM32H7)
\r
474 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
\r
475 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
\r
476 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
\r
477 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
\r
478 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
\r
479 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
\r
480 #endif /* STM32H7 */
\r
486 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
\r
490 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
\r
491 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
\r
492 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
\r
493 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
\r
494 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
\r
495 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
\r
496 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
\r
497 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
\r
498 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
\r
499 #if defined(STM32G4)
\r
501 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
\r
502 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
\r
503 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
\r
504 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
\r
505 #endif /* STM32G4 */
\r
511 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
\r
514 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
\r
515 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
\r
516 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
\r
517 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
\r
518 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
\r
519 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
\r
520 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
\r
521 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
\r
522 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
\r
523 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
\r
529 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
\r
533 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
\r
534 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
\r
539 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
\r
542 #define GET_GPIO_SOURCE GPIO_GET_INDEX
\r
543 #define GET_GPIO_INDEX GPIO_GET_INDEX
\r
545 #if defined(STM32F4)
\r
546 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
\r
547 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
\r
550 #if defined(STM32F7)
\r
551 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
\r
552 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
\r
555 #if defined(STM32L4)
\r
556 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
\r
557 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
\r
560 #if defined(STM32H7)
\r
561 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
\r
562 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
\r
563 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
\r
564 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
\r
565 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
\r
566 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
\r
569 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
\r
570 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
\r
571 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
\r
573 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
\r
574 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
\r
575 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
\r
576 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
\r
577 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
\r
578 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
\r
580 #if defined(STM32L1)
\r
581 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
\r
582 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
\r
583 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
\r
584 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
\r
585 #endif /* STM32L1 */
\r
587 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
\r
588 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
\r
589 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
\r
590 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
\r
591 #endif /* STM32F0 || STM32F3 || STM32F1 */
\r
593 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
\r
598 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
\r
601 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
\r
602 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
\r
603 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
\r
604 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
\r
605 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
\r
606 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
\r
607 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
\r
608 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
\r
609 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
\r
611 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
\r
612 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
\r
613 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
\r
614 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
\r
615 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
\r
616 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
\r
617 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
\r
618 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
\r
620 #if defined(STM32G4)
\r
621 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
\r
622 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
\r
623 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
\r
624 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
\r
625 #endif /* STM32G4 */
\r
630 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
\r
633 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
\r
634 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
\r
635 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
\r
636 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
\r
637 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
\r
638 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
\r
639 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
\r
640 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
\r
641 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
\r
642 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
\r
643 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
\r
644 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
\r
645 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
\r
646 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
\r
647 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
\r
653 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
\r
656 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
\r
657 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
\r
663 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
\r
666 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
\r
667 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
\r
668 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
\r
669 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
\r
674 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
\r
678 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
\r
679 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
\r
680 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
\r
681 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
\r
683 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
\r
684 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
\r
685 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
\r
687 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
\r
688 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
\r
689 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
\r
690 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
\r
692 /* The following 3 definition have also been present in a temporary version of lptim.h */
\r
693 /* They need to be renamed also to the right name, just in case */
\r
694 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
\r
695 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
\r
696 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
\r
702 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
\r
705 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
\r
706 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
\r
707 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
\r
708 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
\r
710 #define NAND_AddressTypedef NAND_AddressTypeDef
\r
712 #define __ARRAY_ADDRESS ARRAY_ADDRESS
\r
713 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
\r
714 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
\r
715 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
\r
716 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
\r
721 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
\r
724 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
\r
725 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
\r
726 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
\r
727 #define NOR_ERROR HAL_NOR_STATUS_ERROR
\r
728 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
\r
730 #define __NOR_WRITE NOR_WRITE
\r
731 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
\r
736 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
\r
740 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
\r
741 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
\r
742 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
\r
743 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
\r
745 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
\r
746 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
\r
747 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
\r
748 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
\r
750 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
\r
751 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
\r
753 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
\r
754 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
\r
756 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
\r
757 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
\r
759 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
\r
761 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
\r
762 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
\r
763 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
\r
765 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5)
\r
766 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
\r
767 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
\r
775 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
\r
778 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
\r
780 #if defined(STM32H7)
\r
781 #define I2S_IT_TXE I2S_IT_TXP
\r
782 #define I2S_IT_RXNE I2S_IT_RXP
\r
784 #define I2S_FLAG_TXE I2S_FLAG_TXP
\r
785 #define I2S_FLAG_RXNE I2S_FLAG_RXP
\r
788 #if defined(STM32F7)
\r
789 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
\r
795 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
\r
799 /* Compact Flash-ATA registers description */
\r
800 #define CF_DATA ATA_DATA
\r
801 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
\r
802 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
\r
803 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
\r
804 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
\r
805 #define CF_CARD_HEAD ATA_CARD_HEAD
\r
806 #define CF_STATUS_CMD ATA_STATUS_CMD
\r
807 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
\r
808 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
\r
810 /* Compact Flash-ATA commands */
\r
811 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
\r
812 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
\r
813 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
\r
814 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
\r
816 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
\r
817 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
\r
818 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
\r
819 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
\r
820 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
\r
825 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
\r
829 #define FORMAT_BIN RTC_FORMAT_BIN
\r
830 #define FORMAT_BCD RTC_FORMAT_BCD
\r
832 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
\r
833 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
\r
834 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
\r
835 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
\r
837 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
\r
838 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
\r
839 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
\r
840 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
\r
841 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
\r
843 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
\r
844 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
\r
845 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
\r
846 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
\r
848 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
\r
849 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
\r
850 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
\r
852 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
\r
853 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
\r
854 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
\r
861 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
\r
864 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
\r
865 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
\r
867 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
\r
868 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
\r
869 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
\r
870 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
\r
872 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
\r
873 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
\r
875 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
\r
876 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
\r
882 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
\r
885 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
\r
886 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
\r
887 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
\r
888 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
\r
889 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
\r
890 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
\r
891 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
\r
892 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
\r
893 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
\r
894 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
\r
895 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
\r
900 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
\r
903 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
\r
904 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
\r
906 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
\r
907 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
\r
909 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
\r
910 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
\r
912 #if defined(STM32H7)
\r
914 #define SPI_FLAG_TXE SPI_FLAG_TXP
\r
915 #define SPI_FLAG_RXNE SPI_FLAG_RXP
\r
917 #define SPI_IT_TXE SPI_IT_TXP
\r
918 #define SPI_IT_RXNE SPI_IT_RXP
\r
920 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
\r
921 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
\r
922 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
\r
923 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
\r
925 #endif /* STM32H7 */
\r
931 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
\r
934 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
\r
935 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
\r
937 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
\r
938 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
\r
939 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
\r
940 #define TIM_DMABase_DIER TIM_DMABASE_DIER
\r
941 #define TIM_DMABase_SR TIM_DMABASE_SR
\r
942 #define TIM_DMABase_EGR TIM_DMABASE_EGR
\r
943 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
\r
944 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
\r
945 #define TIM_DMABase_CCER TIM_DMABASE_CCER
\r
946 #define TIM_DMABase_CNT TIM_DMABASE_CNT
\r
947 #define TIM_DMABase_PSC TIM_DMABASE_PSC
\r
948 #define TIM_DMABase_ARR TIM_DMABASE_ARR
\r
949 #define TIM_DMABase_RCR TIM_DMABASE_RCR
\r
950 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
\r
951 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
\r
952 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
\r
953 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
\r
954 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
\r
955 #define TIM_DMABase_DCR TIM_DMABASE_DCR
\r
956 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
\r
957 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
\r
958 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
\r
959 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
\r
960 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
\r
961 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
\r
962 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
\r
963 #define TIM_DMABase_OR TIM_DMABASE_OR
\r
965 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
\r
966 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
\r
967 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
\r
968 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
\r
969 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
\r
970 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
\r
971 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
\r
972 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
\r
973 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
\r
975 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
\r
976 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
\r
977 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
\r
978 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
\r
979 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
\r
980 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
\r
981 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
\r
982 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
\r
983 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
\r
984 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
\r
985 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
\r
986 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
\r
987 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
\r
988 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
\r
989 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
\r
990 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
\r
991 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
\r
992 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
\r
994 #if defined(STM32L0)
\r
995 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
\r
996 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
\r
999 #if defined(STM32F3)
\r
1000 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
\r
1003 #if defined(STM32H7)
\r
1004 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
\r
1005 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
\r
1006 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
\r
1007 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
\r
1008 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
\r
1009 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
\r
1010 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
\r
1011 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
\r
1012 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
\r
1013 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
\r
1014 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
\r
1015 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
\r
1016 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
\r
1017 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
\r
1018 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
\r
1025 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
\r
1028 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
\r
1029 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
\r
1034 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
\r
1037 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
\r
1038 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
\r
1039 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
\r
1040 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
\r
1042 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
\r
1043 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
\r
1045 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
\r
1046 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
\r
1047 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
\r
1048 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
\r
1050 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
\r
1051 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
\r
1052 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
\r
1053 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
\r
1055 #define __DIV_LPUART UART_DIV_LPUART
\r
1057 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
\r
1058 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
\r
1065 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
\r
1069 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
\r
1070 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
\r
1072 #define USARTNACK_ENABLED USART_NACK_ENABLE
\r
1073 #define USARTNACK_DISABLED USART_NACK_DISABLE
\r
1078 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
\r
1081 #define CFR_BASE WWDG_CFR_BASE
\r
1087 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
\r
1090 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
\r
1091 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
\r
1092 #define CAN_IT_RQCP0 CAN_IT_TME
\r
1093 #define CAN_IT_RQCP1 CAN_IT_TME
\r
1094 #define CAN_IT_RQCP2 CAN_IT_TME
\r
1095 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
\r
1096 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
\r
1097 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
\r
1098 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
\r
1099 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
\r
1105 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
\r
1109 #define VLAN_TAG ETH_VLAN_TAG
\r
1110 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
\r
1111 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
\r
1112 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
\r
1113 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
\r
1114 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
\r
1115 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
\r
1116 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
\r
1118 #define ETH_MMCCR 0x00000100U
\r
1119 #define ETH_MMCRIR 0x00000104U
\r
1120 #define ETH_MMCTIR 0x00000108U
\r
1121 #define ETH_MMCRIMR 0x0000010CU
\r
1122 #define ETH_MMCTIMR 0x00000110U
\r
1123 #define ETH_MMCTGFSCCR 0x0000014CU
\r
1124 #define ETH_MMCTGFMSCCR 0x00000150U
\r
1125 #define ETH_MMCTGFCR 0x00000168U
\r
1126 #define ETH_MMCRFCECR 0x00000194U
\r
1127 #define ETH_MMCRFAECR 0x00000198U
\r
1128 #define ETH_MMCRGUFCR 0x000001C4U
\r
1130 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
\r
1131 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
\r
1132 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
\r
1133 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
\r
1134 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
\r
1135 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
\r
1136 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
\r
1137 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
\r
1138 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
\r
1139 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
\r
1140 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
\r
1141 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
\r
1142 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
\r
1143 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
\r
1144 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
\r
1145 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
\r
1146 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
\r
1147 #if defined(STM32F1)
\r
1149 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
\r
1150 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
\r
1151 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
\r
1153 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
\r
1154 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
\r
1155 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
\r
1156 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
\r
1157 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
\r
1158 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
\r
1159 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
\r
1165 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
\r
1168 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
\r
1169 #define DCMI_IT_OVF DCMI_IT_OVR
\r
1170 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
\r
1171 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
\r
1173 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
\r
1174 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
\r
1175 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
\r
1181 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
\r
1182 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
\r
1183 || defined(STM32H7)
\r
1184 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
\r
1187 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
\r
1188 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
\r
1189 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
\r
1190 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
\r
1191 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
\r
1193 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
\r
1194 #define CM_RGB888 DMA2D_INPUT_RGB888
\r
1195 #define CM_RGB565 DMA2D_INPUT_RGB565
\r
1196 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
\r
1197 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
\r
1198 #define CM_L8 DMA2D_INPUT_L8
\r
1199 #define CM_AL44 DMA2D_INPUT_AL44
\r
1200 #define CM_AL88 DMA2D_INPUT_AL88
\r
1201 #define CM_L4 DMA2D_INPUT_L4
\r
1202 #define CM_A8 DMA2D_INPUT_A8
\r
1203 #define CM_A4 DMA2D_INPUT_A4
\r
1207 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
\r
1209 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
\r
1217 /* Exported functions --------------------------------------------------------*/
\r
1219 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
\r
1222 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
\r
1227 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
\r
1230 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
\r
1231 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
\r
1232 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
\r
1233 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
\r
1234 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
\r
1235 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
\r
1237 /*HASH Algorithm Selection*/
\r
1239 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
\r
1240 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
\r
1241 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
\r
1242 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
\r
1244 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
\r
1245 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
\r
1247 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
\r
1248 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
\r
1253 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
\r
1256 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
\r
1257 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
\r
1258 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
\r
1259 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
\r
1260 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
\r
1261 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
\r
1262 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
\r
1263 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
\r
1264 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
\r
1265 #if defined(STM32L0)
\r
1267 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
\r
1269 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
\r
1270 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
\r
1275 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
\r
1278 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
\r
1279 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
\r
1280 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
\r
1281 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
\r
1282 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
\r
1283 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
\r
1284 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
\r
1290 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
\r
1293 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
\r
1294 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
\r
1295 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
\r
1296 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
\r
1298 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
\r
1300 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
\r
1301 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
\r
1302 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
\r
1303 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
\r
1304 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
\r
1305 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
\r
1306 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
\r
1307 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
\r
1308 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
\r
1309 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
\r
1311 #if defined(STM32F4)
\r
1312 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
\r
1313 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
\r
1314 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
\r
1315 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
\r
1316 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
\r
1317 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
\r
1318 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
\r
1319 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
\r
1320 #endif /* STM32F4 */
\r
1325 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
\r
1328 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
\r
1329 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
\r
1330 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
\r
1331 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
\r
1332 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
\r
1333 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
\r
1334 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
\r
1335 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
\r
1336 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
\r
1337 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
\r
1338 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
\r
1339 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
\r
1340 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
\r
1341 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
\r
1342 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
\r
1343 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
\r
1345 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
\r
1346 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
\r
1347 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
\r
1348 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
\r
1349 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
\r
1350 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
\r
1351 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
\r
1353 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
\r
1354 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
\r
1355 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER
\r
1356 #define CR_PMODE_BB CR_VOS_BB
\r
1358 #define DBP_BitNumber DBP_BIT_NUMBER
\r
1359 #define PVDE_BitNumber PVDE_BIT_NUMBER
\r
1360 #define PMODE_BitNumber PMODE_BIT_NUMBER
\r
1361 #define EWUP_BitNumber EWUP_BIT_NUMBER
\r
1362 #define FPDS_BitNumber FPDS_BIT_NUMBER
\r
1363 #define ODEN_BitNumber ODEN_BIT_NUMBER
\r
1364 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
\r
1365 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
\r
1366 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
\r
1367 #define BRE_BitNumber BRE_BIT_NUMBER
\r
1369 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
\r
1375 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
\r
1378 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
\r
1379 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
\r
1380 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
\r
1385 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
\r
1388 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
\r
1393 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
\r
1396 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
\r
1397 #define HAL_TIM_DMAError TIM_DMAError
\r
1398 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
\r
1399 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
\r
1400 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
\r
1401 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
\r
1402 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
\r
1403 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
\r
1404 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
\r
1405 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
\r
1406 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
\r
1407 #endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
\r
1412 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
\r
1415 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
\r
1420 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
\r
1423 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
\r
1424 #define HAL_LTDC_Relaod HAL_LTDC_Reload
\r
1425 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
\r
1426 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
\r
1432 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
\r
1440 /* Exported macros ------------------------------------------------------------*/
\r
1442 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
\r
1445 #define AES_IT_CC CRYP_IT_CC
\r
1446 #define AES_IT_ERR CRYP_IT_ERR
\r
1447 #define AES_FLAG_CCF CRYP_FLAG_CCF
\r
1452 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
\r
1455 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
\r
1456 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
\r
1457 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
\r
1458 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
\r
1459 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
\r
1460 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
\r
1461 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
\r
1462 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
\r
1463 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
\r
1464 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
\r
1465 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
\r
1466 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
\r
1467 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
\r
1468 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
\r
1470 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
\r
1471 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
\r
1472 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
\r
1473 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
\r
1474 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
\r
1481 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
\r
1484 #define __ADC_ENABLE __HAL_ADC_ENABLE
\r
1485 #define __ADC_DISABLE __HAL_ADC_DISABLE
\r
1486 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
\r
1487 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
\r
1488 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
\r
1489 #define __ADC_IS_ENABLED ADC_IS_ENABLE
\r
1490 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
\r
1491 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
\r
1492 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
\r
1493 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
\r
1494 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
\r
1495 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
\r
1496 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
\r
1498 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
\r
1499 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
\r
1500 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
\r
1501 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
\r
1502 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
\r
1503 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
\r
1504 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
\r
1505 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
\r
1506 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
\r
1507 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
\r
1508 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
\r
1509 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
\r
1510 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
\r
1511 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
\r
1512 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
\r
1513 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
\r
1514 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
\r
1515 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
\r
1516 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
\r
1517 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
\r
1519 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
\r
1520 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
\r
1521 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
\r
1522 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
\r
1523 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
\r
1524 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
\r
1525 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
\r
1526 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
\r
1527 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
\r
1528 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
\r
1530 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
\r
1531 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
\r
1532 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
\r
1533 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
\r
1534 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
\r
1535 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
\r
1536 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
\r
1537 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
\r
1539 #define __HAL_ADC_SQR1 ADC_SQR1
\r
1540 #define __HAL_ADC_SMPR1 ADC_SMPR1
\r
1541 #define __HAL_ADC_SMPR2 ADC_SMPR2
\r
1542 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
\r
1543 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
\r
1544 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
\r
1545 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
\r
1546 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
\r
1547 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
\r
1548 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
\r
1549 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
\r
1550 #define __HAL_ADC_JSQR ADC_JSQR
\r
1552 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
\r
1553 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
\r
1554 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
\r
1555 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
\r
1556 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
\r
1557 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
\r
1558 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
\r
1559 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
\r
1565 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
\r
1568 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
\r
1569 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
\r
1570 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
\r
1571 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
\r
1577 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
\r
1580 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
\r
1581 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
\r
1582 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
\r
1583 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
\r
1584 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
\r
1585 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
\r
1586 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
\r
1587 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
\r
1588 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
\r
1589 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
\r
1590 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
\r
1591 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
\r
1592 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
\r
1593 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
\r
1594 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
\r
1595 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
\r
1597 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
\r
1598 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
\r
1599 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
\r
1600 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
\r
1601 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
\r
1602 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
\r
1603 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
\r
1604 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
\r
1605 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
\r
1606 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
\r
1607 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
\r
1608 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
\r
1609 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
\r
1610 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
\r
1613 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
\r
1614 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
\r
1615 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
\r
1616 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
\r
1617 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
\r
1618 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
\r
1619 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
\r
1620 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
\r
1621 #if defined(STM32H7)
\r
1622 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
\r
1623 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
\r
1624 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
\r
1625 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
\r
1627 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
\r
1628 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
\r
1629 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
\r
1630 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
\r
1631 #endif /* STM32H7 */
\r
1632 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
\r
1633 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
\r
1634 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
\r
1635 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
\r
1636 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
\r
1637 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
\r
1638 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
\r
1639 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
\r
1640 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
\r
1641 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
\r
1642 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
\r
1643 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
\r
1649 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
\r
1652 #if defined(STM32F3)
\r
1653 #define COMP_START __HAL_COMP_ENABLE
\r
1654 #define COMP_STOP __HAL_COMP_DISABLE
\r
1655 #define COMP_LOCK __HAL_COMP_LOCK
\r
1657 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
\r
1658 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
\r
1659 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
\r
1660 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
\r
1661 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
\r
1662 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
\r
1663 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
\r
1664 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
\r
1665 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
\r
1666 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
\r
1667 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
\r
1668 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
\r
1669 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
\r
1670 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
\r
1671 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
\r
1672 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
\r
1673 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
\r
1674 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
\r
1675 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
\r
1676 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
\r
1677 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
\r
1678 __HAL_COMP_COMP6_EXTI_GET_FLAG())
\r
1679 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
\r
1680 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
\r
1681 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
\r
1683 # if defined(STM32F302xE) || defined(STM32F302xC)
\r
1684 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1685 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
\r
1686 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
\r
1687 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
\r
1688 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
\r
1689 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
\r
1690 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
\r
1691 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
\r
1692 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1693 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
\r
1694 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
\r
1695 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
\r
1696 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
\r
1697 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
\r
1698 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
\r
1699 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
\r
1700 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
\r
1701 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
\r
1702 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
\r
1703 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
\r
1704 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
\r
1705 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
\r
1706 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
\r
1707 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
\r
1708 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
\r
1709 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
\r
1710 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
\r
1711 __HAL_COMP_COMP6_EXTI_GET_FLAG())
\r
1712 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
\r
1713 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
\r
1714 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
\r
1715 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
\r
1717 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
\r
1718 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1719 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
\r
1720 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
\r
1721 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
\r
1722 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
\r
1723 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
\r
1724 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
\r
1725 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
\r
1726 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
\r
1727 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
\r
1728 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
\r
1729 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
\r
1730 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
\r
1731 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
\r
1732 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1733 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
\r
1734 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
\r
1735 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
\r
1736 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
\r
1737 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
\r
1738 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
\r
1739 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
\r
1740 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
\r
1741 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
\r
1742 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
\r
1743 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
\r
1744 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
\r
1745 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
\r
1746 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
\r
1747 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
\r
1748 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
\r
1749 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
\r
1750 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
\r
1751 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
\r
1752 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
\r
1753 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
\r
1754 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
\r
1755 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
\r
1756 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
\r
1757 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
\r
1758 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
\r
1759 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
\r
1760 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
\r
1761 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
\r
1762 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
\r
1763 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
\r
1764 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
\r
1765 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
\r
1766 __HAL_COMP_COMP7_EXTI_GET_FLAG())
\r
1767 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
\r
1768 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
\r
1769 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
\r
1770 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
\r
1771 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
\r
1772 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
\r
1773 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
\r
1775 # if defined(STM32F373xC) ||defined(STM32F378xx)
\r
1776 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1777 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
\r
1778 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
\r
1779 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
\r
1780 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1781 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
\r
1782 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
\r
1783 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
\r
1784 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
\r
1785 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
\r
1786 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
\r
1787 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
\r
1788 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
\r
1789 __HAL_COMP_COMP2_EXTI_GET_FLAG())
\r
1790 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
\r
1791 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
\r
1794 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1795 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
\r
1796 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
\r
1797 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
\r
1798 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1799 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
\r
1800 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
\r
1801 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
\r
1802 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
\r
1803 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
\r
1804 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
\r
1805 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
\r
1806 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
\r
1807 __HAL_COMP_COMP2_EXTI_GET_FLAG())
\r
1808 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
\r
1809 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
\r
1812 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
\r
1814 #if defined(STM32L0) || defined(STM32L4)
\r
1815 /* Note: On these STM32 families, the only argument of this macro */
\r
1816 /* is COMP_FLAG_LOCK. */
\r
1817 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
\r
1819 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
\r
1825 #if defined(STM32L0) || defined(STM32L4)
\r
1826 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
\r
1829 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
\r
1830 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
\r
1836 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
\r
1840 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
\r
1841 ((WAVE) == DAC_WAVE_NOISE)|| \
\r
1842 ((WAVE) == DAC_WAVE_TRIANGLE))
\r
1848 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
\r
1852 #define IS_WRPAREA IS_OB_WRPAREA
\r
1853 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
\r
1854 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
\r
1855 #define IS_TYPEERASE IS_FLASH_TYPEERASE
\r
1856 #define IS_NBSECTORS IS_FLASH_NBSECTORS
\r
1857 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
\r
1863 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
\r
1867 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
\r
1868 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
\r
1869 #if defined(STM32F1)
\r
1870 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
\r
1872 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
\r
1873 #endif /* STM32F1 */
\r
1874 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
\r
1875 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
\r
1876 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
\r
1877 #define __HAL_I2C_SPEED I2C_SPEED
\r
1878 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
\r
1879 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
\r
1880 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
\r
1881 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
\r
1882 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
\r
1883 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
\r
1884 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
\r
1885 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
\r
1890 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
\r
1894 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
\r
1895 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
\r
1897 #if defined(STM32H7)
\r
1898 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
\r
1905 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
\r
1909 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
\r
1910 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
\r
1912 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
\r
1913 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
\r
1914 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
\r
1915 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
\r
1917 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
\r
1925 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
\r
1928 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
\r
1929 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
\r
1935 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
\r
1939 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
\r
1940 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
\r
1941 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
\r
1948 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
\r
1951 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
\r
1952 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
\r
1953 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
\r
1954 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
\r
1955 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
\r
1956 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
\r
1957 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
\r
1958 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
\r
1959 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
\r
1960 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
\r
1961 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
\r
1962 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
\r
1963 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
\r
1970 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
\r
1973 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
\r
1974 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
\r
1975 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
\r
1976 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1977 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
\r
1978 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1979 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
\r
1980 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
\r
1981 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
\r
1982 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
\r
1983 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
\r
1984 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
\r
1985 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
\r
1986 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
\r
1987 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
\r
1988 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
\r
1989 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
\r
1990 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
\r
1991 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
\r
1992 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
\r
1993 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1994 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
\r
1995 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1996 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1997 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1998 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
\r
1999 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
\r
2000 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
\r
2001 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
\r
2002 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
\r
2003 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
\r
2004 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
\r
2005 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
\r
2006 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
\r
2007 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
\r
2009 #if defined (STM32F4)
\r
2010 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
\r
2011 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
\r
2012 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
\r
2013 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
\r
2014 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
\r
2016 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
\r
2017 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
\r
2018 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
\r
2019 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
\r
2020 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
\r
2021 #endif /* STM32F4 */
\r
2027 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
\r
2031 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
\r
2032 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
\r
2034 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
\r
2035 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
\r
2037 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
\r
2038 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
\r
2039 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
\r
2040 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
\r
2041 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
\r
2042 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
\r
2043 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
\r
2044 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
\r
2045 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
\r
2046 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
\r
2047 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
\r
2048 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
\r
2049 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
\r
2050 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
\r
2051 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
\r
2052 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
\r
2053 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
\r
2054 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
\r
2055 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
\r
2056 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
\r
2057 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
\r
2058 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
\r
2059 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
\r
2060 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
\r
2061 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
\r
2062 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
\r
2063 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
\r
2064 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
\r
2065 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
\r
2066 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
\r
2067 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
\r
2068 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
\r
2069 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
\r
2070 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
\r
2071 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
\r
2072 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
\r
2073 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
\r
2074 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
\r
2075 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
\r
2076 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
\r
2077 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
\r
2078 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
\r
2079 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
\r
2080 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
\r
2081 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
\r
2082 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
\r
2083 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
\r
2084 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
\r
2085 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
\r
2086 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
\r
2087 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
\r
2088 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
\r
2089 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
\r
2090 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
\r
2091 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
\r
2092 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
\r
2093 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
\r
2094 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
\r
2095 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
\r
2096 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
\r
2097 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
\r
2098 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
\r
2099 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
\r
2100 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
\r
2101 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
\r
2102 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
\r
2103 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
\r
2104 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
\r
2105 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
\r
2106 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
\r
2107 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
\r
2108 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
\r
2109 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
\r
2110 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
\r
2111 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
\r
2112 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
\r
2113 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
\r
2114 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
\r
2115 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
\r
2116 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
\r
2117 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
\r
2118 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
\r
2119 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
\r
2120 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
\r
2121 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
\r
2122 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
\r
2123 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
\r
2124 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
\r
2125 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
\r
2126 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
\r
2127 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
\r
2128 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
\r
2129 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
\r
2130 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
\r
2131 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
\r
2132 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
\r
2133 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
\r
2134 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
\r
2135 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
\r
2136 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
\r
2137 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
\r
2138 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
\r
2139 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
\r
2140 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
\r
2141 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
\r
2142 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
\r
2143 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
\r
2144 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
\r
2145 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
\r
2146 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
\r
2147 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
\r
2148 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
\r
2149 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
\r
2150 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
\r
2151 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
\r
2152 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
\r
2153 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
\r
2154 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
\r
2155 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
\r
2156 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
\r
2157 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
\r
2158 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
\r
2159 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
\r
2160 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
\r
2161 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
\r
2162 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
\r
2163 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
\r
2164 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
\r
2165 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
\r
2166 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
\r
2167 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
\r
2168 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
\r
2169 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
\r
2170 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
\r
2171 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
\r
2172 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
\r
2173 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
\r
2174 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
\r
2175 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
\r
2176 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
\r
2177 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
\r
2178 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
\r
2179 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
\r
2180 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
\r
2181 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
\r
2182 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
\r
2183 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
\r
2184 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
\r
2185 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
\r
2186 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
\r
2187 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
\r
2188 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
\r
2189 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
\r
2190 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
\r
2191 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
\r
2192 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
\r
2193 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
\r
2194 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
\r
2195 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
\r
2196 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
\r
2197 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
\r
2198 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
\r
2199 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
\r
2200 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
\r
2201 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
\r
2202 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
\r
2203 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
\r
2204 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
\r
2205 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
\r
2206 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
\r
2207 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
\r
2208 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
\r
2209 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
\r
2210 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
\r
2211 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
\r
2212 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
\r
2213 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
\r
2214 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
\r
2215 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
\r
2216 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
\r
2217 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
\r
2218 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
\r
2219 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
\r
2220 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
\r
2221 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
\r
2222 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
\r
2223 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
\r
2224 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
\r
2225 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
\r
2226 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
\r
2227 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
\r
2228 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
\r
2229 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
\r
2230 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
\r
2231 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
\r
2232 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
\r
2233 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
\r
2234 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
\r
2235 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
\r
2236 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
\r
2237 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
\r
2238 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
\r
2239 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
\r
2240 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
\r
2241 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
\r
2242 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
\r
2243 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
\r
2244 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
\r
2245 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
\r
2246 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
\r
2247 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
\r
2248 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
\r
2249 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
\r
2250 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
\r
2251 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
\r
2252 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
\r
2253 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
\r
2254 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
\r
2255 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
\r
2256 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
\r
2257 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
\r
2258 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
\r
2259 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
\r
2260 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
\r
2261 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
\r
2262 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
\r
2263 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
\r
2264 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
\r
2265 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
\r
2266 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
\r
2267 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
\r
2268 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
\r
2269 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
\r
2270 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
\r
2271 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
\r
2272 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
\r
2273 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
\r
2274 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
\r
2275 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
\r
2276 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
\r
2277 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
\r
2278 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
\r
2279 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
\r
2280 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
\r
2281 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
\r
2282 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
\r
2283 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
\r
2284 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
\r
2285 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
\r
2286 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
\r
2287 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
\r
2288 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
\r
2289 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
\r
2290 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
\r
2291 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
\r
2292 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
\r
2293 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
\r
2294 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
\r
2296 #if defined(STM32WB)
\r
2297 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
\r
2298 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
\r
2299 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
\r
2300 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
\r
2301 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
\r
2302 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
\r
2303 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
\r
2304 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
\r
2305 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
\r
2306 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
\r
2307 #define QSPI_IRQHandler QUADSPI_IRQHandler
\r
2308 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
\r
2310 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
\r
2311 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
\r
2312 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
\r
2313 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
\r
2314 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
\r
2315 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
\r
2316 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
\r
2317 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
\r
2318 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
\r
2319 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
\r
2320 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
\r
2321 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
\r
2322 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
\r
2323 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
\r
2324 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
\r
2325 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
\r
2326 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
\r
2327 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
\r
2328 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
\r
2329 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
\r
2330 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
\r
2331 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
\r
2332 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
\r
2333 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
\r
2334 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
\r
2335 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
\r
2336 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
\r
2337 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
\r
2338 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
\r
2339 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
\r
2340 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
\r
2341 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
\r
2342 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
\r
2343 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
\r
2344 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
\r
2345 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
\r
2346 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
\r
2347 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
\r
2348 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
\r
2349 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
\r
2350 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
\r
2351 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
\r
2352 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
\r
2353 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
\r
2354 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
\r
2355 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
\r
2356 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
\r
2357 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
\r
2358 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
\r
2359 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
\r
2360 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
\r
2361 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
\r
2362 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
\r
2363 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
\r
2364 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
\r
2365 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
\r
2366 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
\r
2367 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
\r
2368 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
\r
2369 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
\r
2370 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
\r
2371 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
\r
2372 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
\r
2373 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
\r
2374 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
\r
2375 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
\r
2376 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
\r
2377 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
\r
2378 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
\r
2379 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
\r
2380 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
\r
2381 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
\r
2382 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
\r
2383 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
\r
2384 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
\r
2385 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
\r
2386 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
\r
2387 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
\r
2388 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
\r
2389 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
\r
2390 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
\r
2391 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
\r
2392 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
\r
2393 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
\r
2394 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
\r
2395 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
\r
2396 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
\r
2397 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
\r
2398 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
\r
2399 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
\r
2400 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
\r
2401 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
\r
2402 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
\r
2403 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
\r
2404 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
\r
2405 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
\r
2406 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
\r
2407 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
\r
2408 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
\r
2409 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
\r
2410 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
\r
2411 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
\r
2412 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
\r
2413 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
\r
2414 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
\r
2415 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
\r
2416 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
\r
2417 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
\r
2418 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
\r
2419 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
\r
2420 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
\r
2421 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
\r
2422 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
\r
2423 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
\r
2424 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
\r
2425 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
\r
2426 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
\r
2427 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
\r
2428 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
\r
2429 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
\r
2430 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
\r
2431 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
\r
2432 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
\r
2433 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
\r
2434 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
\r
2435 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
\r
2436 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
\r
2437 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
\r
2438 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
\r
2439 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
\r
2440 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
\r
2441 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
\r
2442 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
\r
2443 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
\r
2444 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
\r
2445 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
\r
2446 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
\r
2447 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
\r
2448 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
\r
2449 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
\r
2450 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
\r
2451 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
\r
2452 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
\r
2453 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
\r
2454 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
\r
2455 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
\r
2456 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
\r
2457 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
\r
2458 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
\r
2459 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
\r
2460 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
\r
2461 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
\r
2462 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
\r
2463 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
\r
2464 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
\r
2465 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
\r
2466 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
\r
2467 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
\r
2468 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
\r
2469 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
\r
2470 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
\r
2471 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
\r
2472 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
\r
2473 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
\r
2474 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
\r
2475 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
\r
2476 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
\r
2477 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
\r
2478 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
\r
2479 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
\r
2480 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
\r
2481 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
\r
2482 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
\r
2483 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
\r
2484 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
\r
2485 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
\r
2486 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
\r
2487 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
\r
2488 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
\r
2489 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
\r
2490 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
\r
2491 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
\r
2492 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
\r
2493 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
\r
2494 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
\r
2495 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
\r
2496 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
\r
2497 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
\r
2498 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
\r
2499 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
\r
2500 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
\r
2501 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
\r
2502 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
\r
2503 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
\r
2504 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
\r
2505 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
\r
2506 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
\r
2507 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
\r
2508 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
\r
2509 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
\r
2510 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
\r
2511 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
\r
2512 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
\r
2513 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
\r
2514 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
\r
2515 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
\r
2516 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
\r
2517 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
\r
2518 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
\r
2519 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
\r
2520 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
\r
2521 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
\r
2522 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
\r
2523 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
\r
2524 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
\r
2525 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
\r
2527 #if defined(STM32H7)
\r
2528 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
\r
2529 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
\r
2530 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
\r
2531 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
\r
2533 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
\r
2534 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
\r
2537 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
\r
2538 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
\r
2541 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
\r
2542 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
\r
2543 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
\r
2544 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
\r
2545 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
\r
2546 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
\r
2548 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
\r
2549 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
\r
2550 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
\r
2551 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
\r
2552 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
\r
2553 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
\r
2554 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
\r
2555 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
\r
2556 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
\r
2557 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
\r
2558 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
\r
2559 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
\r
2560 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
\r
2561 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
\r
2562 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
\r
2563 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
\r
2564 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
\r
2565 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
\r
2566 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
\r
2567 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
\r
2569 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
\r
2570 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
\r
2571 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
\r
2572 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
\r
2573 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
\r
2574 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
\r
2575 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
\r
2576 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
\r
2577 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
\r
2578 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
\r
2579 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
\r
2580 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
\r
2581 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
\r
2582 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
\r
2583 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
\r
2584 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
\r
2585 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
\r
2586 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
\r
2587 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
\r
2588 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
\r
2589 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
\r
2590 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
\r
2591 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
\r
2592 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
\r
2593 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
\r
2594 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
\r
2595 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
\r
2596 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
\r
2597 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
\r
2598 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
\r
2599 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
\r
2600 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
\r
2601 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
\r
2602 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
\r
2603 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
\r
2604 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
\r
2605 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
\r
2606 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
\r
2607 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
\r
2608 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
\r
2609 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
\r
2610 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
\r
2611 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
\r
2612 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
\r
2613 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
\r
2614 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
\r
2615 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
\r
2616 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
\r
2617 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
\r
2618 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
\r
2619 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
\r
2620 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
\r
2621 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
\r
2622 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
\r
2623 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
\r
2624 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
\r
2625 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
\r
2626 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
\r
2627 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
\r
2628 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
\r
2629 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
\r
2630 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
\r
2631 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
\r
2632 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
\r
2633 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
\r
2634 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
\r
2635 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
\r
2636 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
\r
2637 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
\r
2638 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
\r
2639 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
\r
2640 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
\r
2641 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
\r
2642 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
\r
2643 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
\r
2644 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
\r
2645 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
\r
2646 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
\r
2647 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
\r
2648 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
\r
2649 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
\r
2650 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
\r
2651 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
\r
2652 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
\r
2653 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
\r
2654 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
\r
2655 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
\r
2656 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
\r
2657 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
\r
2658 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
\r
2659 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
\r
2660 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
\r
2661 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
\r
2662 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
\r
2663 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
\r
2664 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
\r
2665 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
\r
2666 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
\r
2667 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
\r
2668 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
\r
2669 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
\r
2670 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
\r
2671 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
\r
2672 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
\r
2673 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
\r
2674 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
\r
2675 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
\r
2676 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
\r
2677 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
\r
2678 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
\r
2679 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
\r
2680 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
\r
2681 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
\r
2682 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
\r
2683 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
\r
2684 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
\r
2685 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
\r
2686 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
\r
2687 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
\r
2688 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
\r
2689 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
\r
2690 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
\r
2691 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
\r
2692 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
\r
2693 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
\r
2694 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
\r
2695 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
\r
2696 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
\r
2697 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
\r
2698 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
\r
2699 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
\r
2700 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
\r
2701 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
\r
2702 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
\r
2703 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
\r
2704 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
\r
2705 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
\r
2706 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
\r
2707 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
\r
2708 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
\r
2709 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
\r
2710 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
\r
2711 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
\r
2712 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
\r
2713 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
\r
2714 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
\r
2715 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
\r
2717 /* alias define maintained for legacy */
\r
2718 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
\r
2719 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
\r
2721 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
\r
2722 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
\r
2723 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
\r
2724 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
\r
2725 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
\r
2726 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
\r
2727 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
\r
2728 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
\r
2729 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
\r
2730 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
\r
2731 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
\r
2732 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
\r
2733 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
\r
2734 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
\r
2735 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
\r
2736 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
\r
2737 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
\r
2738 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
\r
2739 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
\r
2740 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
\r
2742 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
\r
2743 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
\r
2744 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
\r
2745 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
\r
2746 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
\r
2747 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
\r
2748 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
\r
2749 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
\r
2750 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
\r
2751 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
\r
2752 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
\r
2753 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
\r
2754 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
\r
2755 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
\r
2756 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
\r
2757 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
\r
2758 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
\r
2759 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
\r
2760 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
\r
2761 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
\r
2763 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
\r
2764 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
\r
2765 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
\r
2766 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
\r
2767 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
\r
2768 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
\r
2769 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
\r
2770 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
\r
2771 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
\r
2772 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
\r
2773 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
\r
2774 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
\r
2775 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
\r
2776 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
\r
2777 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
\r
2778 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
\r
2779 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
\r
2780 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
\r
2781 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
\r
2782 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
\r
2783 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
\r
2784 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
\r
2785 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
\r
2786 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
\r
2787 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
\r
2788 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
\r
2789 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
\r
2790 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
\r
2791 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
\r
2792 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
\r
2793 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
\r
2794 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
\r
2795 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
\r
2796 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
\r
2797 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
\r
2798 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
\r
2799 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
\r
2800 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
\r
2801 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
\r
2802 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
\r
2803 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
\r
2804 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
\r
2805 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
\r
2806 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
\r
2807 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
\r
2808 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
\r
2809 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
\r
2810 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
\r
2811 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
\r
2812 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
\r
2813 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
\r
2814 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
\r
2815 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
\r
2816 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
\r
2817 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
\r
2818 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
\r
2819 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
\r
2820 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
\r
2821 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
\r
2822 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
\r
2823 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
\r
2824 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
\r
2825 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
\r
2826 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
\r
2827 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
\r
2828 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
\r
2829 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
\r
2830 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
\r
2831 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
\r
2832 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
\r
2833 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
\r
2834 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
\r
2835 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
\r
2836 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
\r
2837 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
\r
2838 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
\r
2839 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
\r
2840 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
\r
2841 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
\r
2842 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
\r
2843 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
\r
2844 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
\r
2845 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
\r
2846 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
\r
2847 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
\r
2848 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
\r
2849 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
\r
2850 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
\r
2851 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
\r
2852 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
\r
2853 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
\r
2854 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
\r
2855 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
\r
2856 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
\r
2857 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
\r
2858 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
\r
2859 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
\r
2860 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
\r
2861 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
\r
2862 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
\r
2863 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
\r
2864 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
\r
2865 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
\r
2866 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
\r
2867 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
\r
2868 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
\r
2869 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
\r
2870 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
\r
2871 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
\r
2872 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
\r
2873 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
\r
2874 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
\r
2875 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
\r
2876 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
\r
2877 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
\r
2878 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
\r
2880 #if defined(STM32L1)
\r
2881 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
\r
2882 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
\r
2883 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
\r
2884 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
\r
2885 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
\r
2886 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
\r
2887 #endif /* STM32L1 */
\r
2889 #if defined(STM32F4)
\r
2890 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
\r
2891 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
\r
2892 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
\r
2893 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
\r
2894 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
\r
2895 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
\r
2896 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
\r
2897 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
\r
2898 #define Sdmmc1ClockSelection SdioClockSelection
\r
2899 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
\r
2900 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
\r
2901 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
\r
2902 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
\r
2903 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
\r
2906 #if defined(STM32F7) || defined(STM32L4)
\r
2907 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
\r
2908 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
\r
2909 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
\r
2910 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
\r
2911 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
\r
2912 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
\r
2913 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
\r
2914 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
\r
2915 #define SdioClockSelection Sdmmc1ClockSelection
\r
2916 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
\r
2917 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
\r
2918 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
\r
2921 #if defined(STM32F7)
\r
2922 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
\r
2923 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
\r
2926 #if defined(STM32H7)
\r
2927 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
\r
2928 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
\r
2929 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
\r
2930 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
\r
2931 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
\r
2932 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
\r
2933 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
\r
2934 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
\r
2935 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
\r
2936 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
\r
2938 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
\r
2939 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
\r
2940 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
\r
2941 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
\r
2942 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
\r
2943 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
\r
2944 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
\r
2945 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
\r
2946 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
\r
2947 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
\r
2950 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
\r
2951 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
\r
2953 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
\r
2955 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
\r
2956 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
\r
2957 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
\r
2958 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
\r
2959 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
\r
2961 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
\r
2963 #define RCC_IT_CSSLSE RCC_IT_LSECSS
\r
2964 #define RCC_IT_CSSHSE RCC_IT_CSS
\r
2966 #define RCC_PLLMUL_3 RCC_PLL_MUL3
\r
2967 #define RCC_PLLMUL_4 RCC_PLL_MUL4
\r
2968 #define RCC_PLLMUL_6 RCC_PLL_MUL6
\r
2969 #define RCC_PLLMUL_8 RCC_PLL_MUL8
\r
2970 #define RCC_PLLMUL_12 RCC_PLL_MUL12
\r
2971 #define RCC_PLLMUL_16 RCC_PLL_MUL16
\r
2972 #define RCC_PLLMUL_24 RCC_PLL_MUL24
\r
2973 #define RCC_PLLMUL_32 RCC_PLL_MUL32
\r
2974 #define RCC_PLLMUL_48 RCC_PLL_MUL48
\r
2976 #define RCC_PLLDIV_2 RCC_PLL_DIV2
\r
2977 #define RCC_PLLDIV_3 RCC_PLL_DIV3
\r
2978 #define RCC_PLLDIV_4 RCC_PLL_DIV4
\r
2980 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
\r
2981 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
\r
2982 #define RCC_MCO_NODIV RCC_MCODIV_1
\r
2983 #define RCC_MCO_DIV1 RCC_MCODIV_1
\r
2984 #define RCC_MCO_DIV2 RCC_MCODIV_2
\r
2985 #define RCC_MCO_DIV4 RCC_MCODIV_4
\r
2986 #define RCC_MCO_DIV8 RCC_MCODIV_8
\r
2987 #define RCC_MCO_DIV16 RCC_MCODIV_16
\r
2988 #define RCC_MCO_DIV32 RCC_MCODIV_32
\r
2989 #define RCC_MCO_DIV64 RCC_MCODIV_64
\r
2990 #define RCC_MCO_DIV128 RCC_MCODIV_128
\r
2991 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
\r
2992 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
\r
2993 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
\r
2994 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
\r
2995 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
\r
2996 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
\r
2997 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
\r
2998 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
\r
2999 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
\r
3000 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
\r
3001 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
\r
3003 #if defined(STM32L4)
\r
3004 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
\r
3005 #elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
\r
3007 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
\r
3010 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
\r
3011 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
\r
3012 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
\r
3013 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
\r
3014 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
\r
3015 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
\r
3016 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
\r
3017 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
\r
3019 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
\r
3020 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
\r
3021 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
\r
3022 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
\r
3023 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
\r
3024 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
\r
3025 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
\r
3026 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
\r
3027 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
\r
3028 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
\r
3029 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
\r
3030 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
\r
3031 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
\r
3032 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
\r
3033 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
\r
3034 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
\r
3035 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
\r
3036 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
\r
3037 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
\r
3038 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
\r
3039 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
\r
3040 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
\r
3041 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
\r
3042 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
\r
3043 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
\r
3044 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
\r
3045 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
\r
3046 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
\r
3047 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
\r
3048 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
\r
3049 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
\r
3050 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
\r
3052 #define CR_HSION_BB RCC_CR_HSION_BB
\r
3053 #define CR_CSSON_BB RCC_CR_CSSON_BB
\r
3054 #define CR_PLLON_BB RCC_CR_PLLON_BB
\r
3055 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
\r
3056 #define CR_MSION_BB RCC_CR_MSION_BB
\r
3057 #define CSR_LSION_BB RCC_CSR_LSION_BB
\r
3058 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
\r
3059 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
\r
3060 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
\r
3061 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
\r
3062 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
\r
3063 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
\r
3064 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
\r
3065 #define CR_HSEON_BB RCC_CR_HSEON_BB
\r
3066 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
\r
3067 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
\r
3068 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
\r
3070 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
\r
3071 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
\r
3072 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
\r
3073 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
\r
3074 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
\r
3076 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
\r
3078 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
\r
3079 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
\r
3081 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
\r
3082 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
\r
3083 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
\r
3084 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
\r
3085 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
\r
3086 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
\r
3088 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
\r
3089 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
\r
3090 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
\r
3091 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
\r
3092 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
\r
3093 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
\r
3094 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
\r
3095 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
\r
3096 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
\r
3097 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
\r
3098 #define DfsdmClockSelection Dfsdm1ClockSelection
\r
3099 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
\r
3100 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
\r
3101 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
\r
3102 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
\r
3103 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
\r
3104 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
\r
3105 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
\r
3106 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
\r
3107 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
\r
3109 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
\r
3110 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
\r
3111 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
\r
3112 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
\r
3113 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
\r
3114 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
\r
3115 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
\r
3121 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
\r
3124 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
\r
3130 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
\r
3133 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
\r
3135 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
\r
3137 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
\r
3138 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
\r
3140 #if defined (STM32F1)
\r
3141 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
\r
3143 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
\r
3145 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
\r
3147 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
\r
3149 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
\r
3151 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
\r
3152 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
\r
3153 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
\r
3154 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
\r
3155 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
\r
3156 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
\r
3157 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
\r
3158 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
\r
3159 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
\r
3160 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
\r
3161 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
\r
3162 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
\r
3163 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
\r
3164 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
\r
3165 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
\r
3166 #endif /* STM32F1 */
\r
3168 #define IS_ALARM IS_RTC_ALARM
\r
3169 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
\r
3170 #define IS_TAMPER IS_RTC_TAMPER
\r
3171 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
\r
3172 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
\r
3173 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
\r
3174 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
\r
3175 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
\r
3176 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
\r
3177 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
\r
3178 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
\r
3179 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
\r
3180 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
\r
3181 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
\r
3183 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
\r
3184 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
\r
3190 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
\r
3194 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
\r
3195 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
\r
3197 #if defined(STM32F4) || defined(STM32F2)
\r
3198 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
\r
3199 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
\r
3200 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
\r
3201 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
\r
3202 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
\r
3203 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
\r
3204 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
\r
3205 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
\r
3206 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
\r
3207 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
\r
3208 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
\r
3209 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
\r
3210 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
\r
3211 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
\r
3212 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
\r
3213 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
\r
3214 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
\r
3215 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
\r
3216 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
\r
3217 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
\r
3219 #define SDMMC1_IRQn SDIO_IRQn
\r
3220 #define SDMMC1_IRQHandler SDIO_IRQHandler
\r
3223 #if defined(STM32F7) || defined(STM32L4)
\r
3224 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
\r
3225 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
\r
3226 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
\r
3227 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
\r
3228 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
\r
3229 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
\r
3230 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
\r
3231 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
\r
3232 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
\r
3233 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
\r
3234 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
\r
3235 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
\r
3236 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
\r
3237 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
\r
3238 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
\r
3239 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
\r
3240 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
\r
3241 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
\r
3242 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
\r
3243 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
\r
3244 /* alias CMSIS for compatibilities */
\r
3245 #define SDIO_IRQn SDMMC1_IRQn
\r
3246 #define SDIO_IRQHandler SDMMC1_IRQHandler
\r
3249 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
\r
3250 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
\r
3251 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
\r
3252 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
\r
3253 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
\r
3256 #if defined(STM32H7)
\r
3257 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
\r
3258 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
\r
3259 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
\r
3260 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
\r
3261 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
\r
3262 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
\r
3263 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
\r
3264 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
\r
3265 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
\r
3271 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
\r
3275 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
\r
3276 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
\r
3277 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
\r
3278 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
\r
3279 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
\r
3280 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
\r
3282 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
\r
3283 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
\r
3285 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
\r
3291 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
\r
3294 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
\r
3295 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
\r
3296 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
\r
3297 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
\r
3298 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
\r
3299 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
\r
3300 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
\r
3301 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
\r
3306 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
\r
3310 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
\r
3311 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
\r
3312 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
\r
3318 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
\r
3322 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
\r
3323 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
\r
3324 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
\r
3325 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
\r
3327 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
\r
3329 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
\r
3330 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
\r
3337 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
\r
3341 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
\r
3342 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
\r
3343 #define __USART_ENABLE __HAL_USART_ENABLE
\r
3344 #define __USART_DISABLE __HAL_USART_DISABLE
\r
3346 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
\r
3347 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
\r
3353 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
\r
3356 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
\r
3358 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
\r
3359 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
\r
3360 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
\r
3361 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
\r
3363 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
\r
3364 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
\r
3365 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
\r
3366 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
\r
3368 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
\r
3369 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
\r
3370 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
\r
3371 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
\r
3372 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
\r
3373 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
\r
3374 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
\r
3376 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
\r
3377 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
\r
3378 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
\r
3379 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
\r
3380 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
\r
3381 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
\r
3382 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
\r
3383 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
\r
3385 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
\r
3386 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
\r
3387 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
\r
3388 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
\r
3389 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
\r
3390 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
\r
3391 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
\r
3392 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
\r
3394 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
\r
3395 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
\r
3397 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
\r
3398 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
\r
3403 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
\r
3406 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
\r
3407 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
\r
3409 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
\r
3410 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
\r
3412 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
\r
3414 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
\r
3415 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
\r
3416 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
\r
3417 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
\r
3418 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
\r
3419 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
\r
3420 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
\r
3421 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
\r
3422 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
\r
3423 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
\r
3424 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
\r
3425 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
\r
3427 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
\r
3432 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
\r
3436 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
\r
3437 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
\r
3438 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
\r
3439 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
\r
3440 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
\r
3441 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
\r
3442 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
\r
3444 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
\r
3445 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
\r
3446 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
\r
3451 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
\r
3454 #define __HAL_LTDC_LAYER LTDC_LAYER
\r
3455 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
\r
3460 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
\r
3463 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
\r
3464 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
\r
3465 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
\r
3466 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
\r
3467 #define SAI_STREOMODE SAI_STEREOMODE
\r
3468 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
\r
3469 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
\r
3470 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
\r
3471 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
\r
3472 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
\r
3473 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
\r
3474 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
\r
3475 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
\r
3476 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
\r
3481 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
\r
3484 #if defined(STM32H7)
\r
3485 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
\r
3486 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
\r
3487 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
\r
3493 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
\r
3496 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
\r
3497 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
\r
3498 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
\r
3499 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
\r
3500 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
\r
3501 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
\r
3502 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
\r
3508 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
\r
3511 #if defined (STM32L4)
\r
3512 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
\r
3518 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
\r
3526 #ifdef __cplusplus
\r
3530 #endif /* STM32_HAL_LEGACY */
\r
3532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob