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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32l4xx_hal_dfsdm.h\r
   4   * @author  MCD Application Team\r
   5   * @brief   Header file of DFSDM HAL module.\r
   6   ******************************************************************************\r
   7   * @attention\r
   8   *\r
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
  10   * All rights reserved.</center></h2>\r
  11   *\r
  12   * This software component is licensed by ST under BSD 3-Clause license,\r
  13   * the "License"; You may not use this file except in compliance with the\r
  14   * License. You may obtain a copy of the License at:\r
  15   *                        opensource.org/licenses/BSD-3-Clause\r
  16   *\r
  17   ******************************************************************************\r
  18   */\r
  19 \r
  20 /* Define to prevent recursive inclusion -------------------------------------*/\r
  21 #ifndef STM32L4xx_HAL_DFSDM_H\r
  22 #define STM32L4xx_HAL_DFSDM_H\r
  23 \r
  24 #ifdef __cplusplus\r
  25 extern "C" {\r
  26 #endif\r
  27 \r
  28 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
  29     defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
  30     defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
  31     defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
  32 \r
  33 /* Includes ------------------------------------------------------------------*/\r
  34 #include "stm32l4xx_hal_def.h"\r
  35 \r
  36 /** @addtogroup STM32L4xx_HAL_Driver\r
  37   * @{\r
  38   */\r
  39 \r
  40 /** @addtogroup DFSDM\r
  41   * @{\r
  42   */\r
  43 \r
  44 /* Exported types ------------------------------------------------------------*/\r
  45 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types\r
  46   * @{\r
  47   */\r
  48 \r
  49 /**\r
  50   * @brief  HAL DFSDM Channel states definition\r
  51   */\r
  52 typedef enum\r
  53 {\r
  54   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */\r
  55   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */\r
  56   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */\r
  57 } HAL_DFSDM_Channel_StateTypeDef;\r
  58 \r
  59 /**\r
  60   * @brief  DFSDM channel output clock structure definition\r
  61   */\r
  62 typedef struct\r
  63 {\r
  64   FunctionalState Activation; /*!< Output clock enable/disable */\r
  65   uint32_t        Selection;  /*!< Output clock is system clock or audio clock.\r
  66                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */\r
  67   uint32_t        Divider;    /*!< Output clock divider.\r
  68                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */\r
  69 } DFSDM_Channel_OutputClockTypeDef;\r
  70 \r
  71 /**\r
  72   * @brief  DFSDM channel input structure definition\r
  73   */\r
  74 typedef struct\r
  75 {\r
  76   uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.\r
  77                              ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,\r
  78                              STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,\r
  79                              STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.\r
  80                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */\r
  81   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.\r
  82                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */\r
  83   uint32_t Pins;        /*!< Input pins are taken from same or following channel.\r
  84                              This parameter can be a value of @ref DFSDM_Channel_InputPins */\r
  85 } DFSDM_Channel_InputTypeDef;\r
  86 \r
  87 /**\r
  88   * @brief  DFSDM channel serial interface structure definition\r
  89   */\r
  90 typedef struct\r
  91 {\r
  92   uint32_t Type;     /*!< SPI or Manchester modes.\r
  93                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */\r
  94   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).\r
  95                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */\r
  96 } DFSDM_Channel_SerialInterfaceTypeDef;\r
  97 \r
  98 /**\r
  99   * @brief  DFSDM channel analog watchdog structure definition\r
 100   */\r
 101 typedef struct\r
 102 {\r
 103   uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.\r
 104                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */\r
 105   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.\r
 106                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
 107 } DFSDM_Channel_AwdTypeDef;\r
 108 \r
 109 /**\r
 110   * @brief  DFSDM channel init structure definition\r
 111   */\r
 112 typedef struct\r
 113 {\r
 114   DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */\r
 115   DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */\r
 116   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */\r
 117   DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */\r
 118   int32_t                              Offset;          /*!< DFSDM channel offset.\r
 119                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
 120   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.\r
 121                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
 122 } DFSDM_Channel_InitTypeDef;\r
 123 \r
 124 /**\r
 125   * @brief  DFSDM channel handle structure definition\r
 126   */\r
 127 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 128 typedef struct __DFSDM_Channel_HandleTypeDef\r
 129 #else\r
 130 typedef struct\r
 131 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
 132 {\r
 133   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */\r
 134   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */\r
 135   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */\r
 136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 137   void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);       /*!< DFSDM channel clock absence detection callback */\r
 138   void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);        /*!< DFSDM channel short circuit detection callback */\r
 139   void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);    /*!< DFSDM channel MSP init callback */\r
 140   void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);  /*!< DFSDM channel MSP de-init callback */\r
 141 #endif\r
 142 } DFSDM_Channel_HandleTypeDef;\r
 143 \r
 144 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 145 /**\r
 146   * @brief  DFSDM channel callback ID enumeration definition\r
 147   */\r
 148 typedef enum\r
 149 {\r
 150   HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */\r
 151   HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */\r
 152   HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */\r
 153   HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */\r
 154 } HAL_DFSDM_Channel_CallbackIDTypeDef;\r
 155 \r
 156 /**\r
 157   * @brief  DFSDM channel callback pointer definition\r
 158   */\r
 159 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 160 #endif\r
 161 \r
 162 /**\r
 163   * @brief  HAL DFSDM Filter states definition\r
 164   */\r
 165 typedef enum\r
 166 {\r
 167   HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */\r
 168   HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */\r
 169   HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */\r
 170   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */\r
 171   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */\r
 172   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */\r
 173 } HAL_DFSDM_Filter_StateTypeDef;\r
 174 \r
 175 /**\r
 176   * @brief  DFSDM filter regular conversion parameters structure definition\r
 177   */\r
 178 typedef struct\r
 179 {\r
 180   uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.\r
 181                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
 182   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */\r
 183   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */\r
 184 } DFSDM_Filter_RegularParamTypeDef;\r
 185 \r
 186 /**\r
 187   * @brief  DFSDM filter injected conversion parameters structure definition\r
 188   */\r
 189 typedef struct\r
 190 {\r
 191   uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.\r
 192                                        This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
 193   FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */\r
 194   FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */\r
 195   uint32_t        ExtTrigger;     /*!< External trigger.\r
 196                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */\r
 197   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.\r
 198                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */\r
 199 } DFSDM_Filter_InjectedParamTypeDef;\r
 200 \r
 201 /**\r
 202   * @brief  DFSDM filter parameters structure definition\r
 203   */\r
 204 typedef struct\r
 205 {\r
 206   uint32_t SincOrder;       /*!< Sinc filter order.\r
 207                                  This parameter can be a value of @ref DFSDM_Filter_SincOrder */\r
 208   uint32_t Oversampling;    /*!< Filter oversampling ratio.\r
 209                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r
 210   uint32_t IntOversampling; /*!< Integrator oversampling ratio.\r
 211                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */\r
 212 } DFSDM_Filter_FilterParamTypeDef;\r
 213 \r
 214 /**\r
 215   * @brief  DFSDM filter init structure definition\r
 216   */\r
 217 typedef struct\r
 218 {\r
 219   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */\r
 220   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */\r
 221   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */\r
 222 } DFSDM_Filter_InitTypeDef;\r
 223 \r
 224 /**\r
 225   * @brief  DFSDM filter handle structure definition\r
 226   */\r
 227 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 228 typedef struct __DFSDM_Filter_HandleTypeDef\r
 229 #else\r
 230 typedef struct\r
 231 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
 232 {\r
 233   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */\r
 234   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */\r
 235   DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */\r
 236   DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */\r
 237   uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */\r
 238   uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */\r
 239   uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */\r
 240   uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */\r
 241   FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */\r
 242   uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */\r
 243   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */\r
 244   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */\r
 245   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */\r
 246 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 247   void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
 248                       uint32_t Channel, uint32_t Threshold);                            /*!< DFSDM filter analog watchdog callback */\r
 249   void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter regular conversion complete callback */\r
 250   void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half regular conversion complete callback */\r
 251   void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter injected conversion complete callback */\r
 252   void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half injected conversion complete callback */\r
 253   void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);            /*!< DFSDM filter error callback */\r
 254   void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);          /*!< DFSDM filter MSP init callback */\r
 255   void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);        /*!< DFSDM filter MSP de-init callback */\r
 256 #endif\r
 257 } DFSDM_Filter_HandleTypeDef;\r
 258 \r
 259 /**\r
 260   * @brief  DFSDM filter analog watchdog parameters structure definition\r
 261   */\r
 262 typedef struct\r
 263 {\r
 264   uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.\r
 265                                  This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */\r
 266   uint32_t Channel;         /*!< Analog watchdog channel selection.\r
 267                                  This parameter can be a values combination of @ref DFSDM_Channel_Selection */\r
 268   int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.\r
 269                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
 270   int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.\r
 271                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
 272   uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.\r
 273                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
 274   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.\r
 275                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
 276 } DFSDM_Filter_AwdParamTypeDef;\r
 277 \r
 278 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 279 /**\r
 280   * @brief  DFSDM filter callback ID enumeration definition\r
 281   */\r
 282 typedef enum\r
 283 {\r
 284   HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */\r
 285   HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */\r
 286   HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */\r
 287   HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */\r
 288   HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */\r
 289   HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */\r
 290   HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */\r
 291 } HAL_DFSDM_Filter_CallbackIDTypeDef;\r
 292 \r
 293 /**\r
 294   * @brief  DFSDM filter callback pointer definition\r
 295   */\r
 296 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 297 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
 298 #endif\r
 299 \r
 300 /**\r
 301   * @}\r
 302   */\r
 303 /* End of exported types -----------------------------------------------------*/\r
 304 \r
 305 /* Exported constants --------------------------------------------------------*/\r
 306 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants\r
 307   * @{\r
 308   */\r
 309 \r
 310 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection\r
 311   * @{\r
 312   */\r
 313 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U             /*!< Source for ouput clock is system clock */\r
 314 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */\r
 315 /**\r
 316   * @}\r
 317   */\r
 318 \r
 319 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer\r
 320   * @{\r
 321   */\r
 322 #define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */\r
 323 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
 324     defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
 325     defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
 326 #define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */\r
 327 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
 328 #define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */\r
 329 /**\r
 330   * @}\r
 331   */\r
 332 \r
 333 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing\r
 334   * @{\r
 335   */\r
 336 #define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */\r
 337 #define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */\r
 338 #define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */\r
 339 /**\r
 340   * @}\r
 341   */\r
 342 \r
 343 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins\r
 344   * @{\r
 345   */\r
 346 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U             /*!< Input from pins on same channel */\r
 347 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */\r
 348 /**\r
 349   * @}\r
 350   */\r
 351 \r
 352 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type\r
 353   * @{\r
 354   */\r
 355 #define DFSDM_CHANNEL_SPI_RISING         0x00000000U             /*!< SPI with rising edge */\r
 356 #define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */\r
 357 #define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */\r
 358 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */\r
 359 /**\r
 360   * @}\r
 361   */\r
 362 \r
 363 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection\r
 364   * @{\r
 365   */\r
 366 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */\r
 367 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */\r
 368 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */\r
 369 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */\r
 370 /**\r
 371   * @}\r
 372   */\r
 373 \r
 374 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order\r
 375   * @{\r
 376   */\r
 377 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */\r
 378 #define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */\r
 379 #define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */\r
 380 #define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */\r
 381 /**\r
 382   * @}\r
 383   */\r
 384 \r
 385 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger\r
 386   * @{\r
 387   */\r
 388 #define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */\r
 389 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */\r
 390 #define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */\r
 391 /**\r
 392   * @}\r
 393   */\r
 394 \r
 395 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger\r
 396   * @{\r
 397   */\r
 398 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
 399 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 400 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 401 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 402 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
 403 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
 404 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 405 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 406 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
 407 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For all DFSDM filters */\r
 408 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */\r
 409 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */\r
 410 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */\r
 411 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */\r
 412 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
 413 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
 414 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \\r
 415                                           DFSDM_FLTCR1_JEXTSEL_2)                          /*!< For all DFSDM filters */\r
 416 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3                            /*!< For all DFSDM filters */\r
 417 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
 418 #define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
 419                                           DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
 420 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
 421                                           DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
 422 #else\r
 423 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 424 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 425 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 426 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
 427 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */\r
 428 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */\r
 429 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */\r
 430 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
 431 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */\r
 432 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 433 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
 434 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
 435 /**\r
 436   * @}\r
 437   */\r
 438 \r
 439 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge\r
 440   * @{\r
 441   */\r
 442 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */\r
 443 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */\r
 444 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */\r
 445 /**\r
 446   * @}\r
 447   */\r
 448 \r
 449 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order\r
 450   * @{\r
 451   */\r
 452 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */\r
 453 #define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */\r
 454 #define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */\r
 455 #define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */\r
 456 #define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */\r
 457 #define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */\r
 458 /**\r
 459   * @}\r
 460   */\r
 461 \r
 462 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source\r
 463   * @{\r
 464   */\r
 465 #define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */\r
 466 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */\r
 467 /**\r
 468   * @}\r
 469   */\r
 470 \r
 471 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code\r
 472   * @{\r
 473   */\r
 474 #define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */\r
 475 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */\r
 476 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */\r
 477 #define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */\r
 478 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 479 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */\r
 480 #endif\r
 481 /**\r
 482   * @}\r
 483   */\r
 484 \r
 485 /** @defgroup DFSDM_BreakSignals DFSDM break signals\r
 486   * @{\r
 487   */\r
 488 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */\r
 489 #define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */\r
 490 #define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */\r
 491 #define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */\r
 492 #define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */\r
 493 /**\r
 494   * @}\r
 495   */\r
 496 \r
 497 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection\r
 498   * @{\r
 499   */\r
 500 /* DFSDM Channels ------------------------------------------------------------*/\r
 501 /* The DFSDM channels are defined as follows:\r
 502    - in 16-bit LSB the channel mask is set\r
 503    - in 16-bit MSB the channel number is set\r
 504    e.g. for channel 5 definition:\r
 505         - the channel mask is 0x00000020 (bit 5 is set)\r
 506         - the channel number 5 is 0x00050000\r
 507         --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */\r
 508 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
 509 #define DFSDM_CHANNEL_0                              0x00000001U\r
 510 #define DFSDM_CHANNEL_1                              0x00010002U\r
 511 #define DFSDM_CHANNEL_2                              0x00020004U\r
 512 #define DFSDM_CHANNEL_3                              0x00030008U\r
 513 #else\r
 514 #define DFSDM_CHANNEL_0                              0x00000001U\r
 515 #define DFSDM_CHANNEL_1                              0x00010002U\r
 516 #define DFSDM_CHANNEL_2                              0x00020004U\r
 517 #define DFSDM_CHANNEL_3                              0x00030008U\r
 518 #define DFSDM_CHANNEL_4                              0x00040010U\r
 519 #define DFSDM_CHANNEL_5                              0x00050020U\r
 520 #define DFSDM_CHANNEL_6                              0x00060040U\r
 521 #define DFSDM_CHANNEL_7                              0x00070080U\r
 522 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
 523 /**\r
 524   * @}\r
 525   */\r
 526 \r
 527 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode\r
 528   * @{\r
 529   */\r
 530 #define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */\r
 531 #define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */\r
 532 /**\r
 533   * @}\r
 534   */\r
 535 \r
 536 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold\r
 537   * @{\r
 538   */\r
 539 #define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */\r
 540 #define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */\r
 541 /**\r
 542   * @}\r
 543   */\r
 544 \r
 545 /**\r
 546   * @}\r
 547   */\r
 548 /* End of exported constants -------------------------------------------------*/\r
 549 \r
 550 /* Exported macros -----------------------------------------------------------*/\r
 551 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros\r
 552  * @{\r
 553  */\r
 554 \r
 555 /** @brief  Reset DFSDM channel handle state.\r
 556   * @param  __HANDLE__ DFSDM channel handle.\r
 557   * @retval None\r
 558   */\r
 559 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 560 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \\r
 561                                                                (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \\r
 562                                                                (__HANDLE__)->MspInitCallback = NULL;                \\r
 563                                                                (__HANDLE__)->MspDeInitCallback = NULL;              \\r
 564                                                              } while(0)\r
 565 #else\r
 566 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)\r
 567 #endif\r
 568 \r
 569 /** @brief  Reset DFSDM filter handle state.\r
 570   * @param  __HANDLE__ DFSDM filter handle.\r
 571   * @retval None\r
 572   */\r
 573 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 574 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \\r
 575                                                               (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \\r
 576                                                               (__HANDLE__)->MspInitCallback = NULL;               \\r
 577                                                               (__HANDLE__)->MspDeInitCallback = NULL;             \\r
 578                                                             } while(0)\r
 579 #else\r
 580 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)\r
 581 #endif\r
 582 \r
 583 /**\r
 584   * @}\r
 585   */\r
 586 /* End of exported macros ----------------------------------------------------*/\r
 587 \r
 588 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
 589 /* Include DFSDM HAL Extension module */\r
 590 #include "stm32l4xx_hal_dfsdm_ex.h"\r
 591 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
 592 \r
 593 /* Exported functions --------------------------------------------------------*/\r
 594 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions\r
 595   * @{\r
 596   */\r
 597 \r
 598 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
 599   * @{\r
 600   */\r
 601 /* Channel initialization and de-initialization functions *********************/\r
 602 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 603 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 604 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 605 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 606 \r
 607 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 608 /* Channel callbacks register/unregister functions ****************************/\r
 609 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
 610                                                      HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
 611                                                      pDFSDM_Channel_CallbackTypeDef      pCallback);\r
 612 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
 613                                                        HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);\r
 614 #endif\r
 615 /**\r
 616   * @}\r
 617   */\r
 618 \r
 619 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
 620   * @{\r
 621   */\r
 622 /* Channel operation functions ************************************************/\r
 623 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 624 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 625 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 626 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 627 \r
 628 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
 629 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
 630 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 631 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 632 \r
 633 int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 634 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);\r
 635 \r
 636 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
 637 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
 638 \r
 639 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 640 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 641 /**\r
 642   * @}\r
 643   */\r
 644 \r
 645 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
 646   * @{\r
 647   */\r
 648 /* Channel state function *****************************************************/\r
 649 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
 650 /**\r
 651   * @}\r
 652   */\r
 653 \r
 654 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
 655   * @{\r
 656   */\r
 657 /* Filter initialization and de-initialization functions *********************/\r
 658 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 659 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 660 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 661 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 662 \r
 663 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
 664 /* Filter callbacks register/unregister functions ****************************/\r
 665 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
 666                                                     HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
 667                                                     pDFSDM_Filter_CallbackTypeDef      pCallback);\r
 668 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
 669                                                       HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);\r
 670 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,\r
 671                                                        pDFSDM_Filter_AwdCallbackTypeDef pCallback);\r
 672 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 673 #endif\r
 674 /**\r
 675   * @}\r
 676   */\r
 677 \r
 678 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
 679   * @{\r
 680   */\r
 681 /* Filter control functions *********************/\r
 682 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
 683                                                    uint32_t                    Channel,\r
 684                                                    uint32_t                    ContinuousMode);\r
 685 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
 686                                                    uint32_t                    Channel);\r
 687 /**\r
 688   * @}\r
 689   */\r
 690 \r
 691 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
 692   * @{\r
 693   */\r
 694 /* Filter operation functions *********************/\r
 695 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 696 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 697 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
 698 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
 699 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 700 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 701 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 702 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 703 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 704 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
 705 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
 706 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 707 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 708 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 709 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
 710                                               DFSDM_Filter_AwdParamTypeDef *awdParam);\r
 711 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 712 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);\r
 713 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 714 \r
 715 int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
 716 int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
 717 int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
 718 int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
 719 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 720 \r
 721 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 722 \r
 723 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
 724 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
 725 \r
 726 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 727 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 728 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 729 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 730 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
 731 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 732 /**\r
 733   * @}\r
 734   */\r
 735 \r
 736 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
 737   * @{\r
 738   */\r
 739 /* Filter state functions *****************************************************/\r
 740 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 741 uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
 742 /**\r
 743   * @}\r
 744   */\r
 745 \r
 746 /**\r
 747   * @}\r
 748   */\r
 749 /* End of exported functions -------------------------------------------------*/\r
 750 \r
 751 /* Private macros ------------------------------------------------------------*/\r
 752 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros\r
 753 * @{\r
 754 */\r
 755 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \\r
 756                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))\r
 757 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))\r
 758 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
 759     defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
 760     defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
 761 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
 762                                                        ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \\r
 763                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
 764 #else\r
 765 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
 766                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
 767 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
 768 /* STM32L496xx || STM32L4A6xx ||                */\r
 769 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
 770 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \\r
 771                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \\r
 772                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))\r
 773 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \\r
 774                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))\r
 775 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \\r
 776                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \\r
 777                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \\r
 778                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))\r
 779 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \\r
 780                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \\r
 781                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \\r
 782                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))\r
 783 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \\r
 784                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \\r
 785                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \\r
 786                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))\r
 787 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))\r
 788 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
 789 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)\r
 790 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)\r
 791 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
 792                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))\r
 793 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
 794                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \\r
 795                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))\r
 796 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
 797 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
 798                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
 799                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
 800                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
 801                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
 802                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
 803                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
 804 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
 805 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
 806                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
 807                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
 808                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
 809                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
 810                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
 811                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
 812                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
 813                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
 814                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
 815                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \\r
 816                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))\r
 817 #else\r
 818 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
 819                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
 820                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
 821                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
 822                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
 823                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
 824                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
 825                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
 826                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
 827                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
 828                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
 829 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
 830 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \\r
 831                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \\r
 832                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))\r
 833 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \\r
 834                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \\r
 835                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \\r
 836                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \\r
 837                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \\r
 838                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))\r
 839 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))\r
 840 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))\r
 841 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \\r
 842                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))\r
 843 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
 844 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)\r
 845 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
 846 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
 847                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
 848                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
 849                                                        ((CHANNEL) == DFSDM_CHANNEL_3))\r
 850 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))\r
 851 #else\r
 852 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
 853                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
 854                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
 855                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \\r
 856                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \\r
 857                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \\r
 858                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \\r
 859                                                        ((CHANNEL) == DFSDM_CHANNEL_7))\r
 860 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))\r
 861 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
 862 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \\r
 863                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))\r
 864 /**\r
 865   * @}\r
 866   */\r
 867 /* End of private macros -----------------------------------------------------*/\r
 868 \r
 869 /**\r
 870   * @}\r
 871   */\r
 872 \r
 873 /**\r
 874   * @}\r
 875   */\r
 876 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
 877 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
 878 /* STM32L496xx || STM32L4A6xx || */\r
 879 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
 880 \r
 881 #ifdef __cplusplus\r
 882 }\r
 883 #endif\r
 884 \r
 885 #endif /* STM32L4xx_HAL_DFSDM_H */\r
 886 \r
 887 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r