2 ******************************************************************************
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3 * @file stm32l4xx_hal_rcc.h
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4 * @author MCD Application Team
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5 * @brief Header file of RCC HAL module.
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6 ******************************************************************************
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9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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10 * All rights reserved.</center></h2>
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12 * This software component is licensed by ST under BSD 3-Clause license,
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13 * the "License"; You may not use this file except in compliance with the
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14 * License. You may obtain a copy of the License at:
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15 * opensource.org/licenses/BSD-3-Clause
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17 ******************************************************************************
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20 /* Define to prevent recursive inclusion -------------------------------------*/
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21 #ifndef __STM32L4xx_HAL_RCC_H
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22 #define __STM32L4xx_HAL_RCC_H
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28 /* Includes ------------------------------------------------------------------*/
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29 #include "stm32l4xx_hal_def.h"
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31 /** @addtogroup STM32L4xx_HAL_Driver
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39 /* Exported types ------------------------------------------------------------*/
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40 /** @defgroup RCC_Exported_Types RCC Exported Types
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45 * @brief RCC PLL configuration structure definition
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49 uint32_t PLLState; /*!< The new state of the PLL.
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50 This parameter can be a value of @ref RCC_PLL_Config */
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52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
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53 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
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56 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
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57 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */
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59 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
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60 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
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62 #if defined(RCC_PLLP_SUPPORT)
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63 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
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64 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
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65 #endif /* RCC_PLLP_SUPPORT */
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67 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
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68 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
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70 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
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71 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ
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72 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.
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73 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
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75 }RCC_PLLInitTypeDef;
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78 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
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82 uint32_t OscillatorType; /*!< The oscillators to be configured.
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83 This parameter can be a value of @ref RCC_Oscillator_Type */
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85 uint32_t HSEState; /*!< The new state of the HSE.
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86 This parameter can be a value of @ref RCC_HSE_Config */
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88 uint32_t LSEState; /*!< The new state of the LSE.
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89 This parameter can be a value of @ref RCC_LSE_Config */
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91 uint32_t HSIState; /*!< The new state of the HSI.
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92 This parameter can be a value of @ref RCC_HSI_Config */
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94 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
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95 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
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96 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
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98 uint32_t LSIState; /*!< The new state of the LSI.
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99 This parameter can be a value of @ref RCC_LSI_Config */
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100 #if defined(RCC_CSR_LSIPREDIV)
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102 uint32_t LSIDiv; /*!< The division factor of the LSI.
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103 This parameter can be a value of @ref RCC_LSI_Div */
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104 #endif /* RCC_CSR_LSIPREDIV */
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106 uint32_t MSIState; /*!< The new state of the MSI.
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107 This parameter can be a value of @ref RCC_MSI_Config */
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109 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
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110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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112 uint32_t MSIClockRange; /*!< The MSI frequency range.
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113 This parameter can be a value of @ref RCC_MSI_Clock_Range */
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115 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
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116 This parameter can be a value of @ref RCC_HSI48_Config */
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118 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
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120 }RCC_OscInitTypeDef;
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123 * @brief RCC System, AHB and APB busses clock configuration structure definition
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127 uint32_t ClockType; /*!< The clock to be configured.
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128 This parameter can be a value of @ref RCC_System_Clock_Type */
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130 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
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131 This parameter can be a value of @ref RCC_System_Clock_Source */
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133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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134 This parameter can be a value of @ref RCC_AHB_Clock_Source */
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136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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142 }RCC_ClkInitTypeDef;
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148 /* Exported constants --------------------------------------------------------*/
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149 /** @defgroup RCC_Exported_Constants RCC Exported Constants
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153 /** @defgroup RCC_Timeout_Value Timeout Values
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156 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
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157 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
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162 /** @defgroup RCC_Oscillator_Type Oscillator Type
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165 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
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166 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
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167 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
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168 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
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169 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
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170 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */
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171 #if defined(RCC_HSI48_SUPPORT)
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172 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
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173 #endif /* RCC_HSI48_SUPPORT */
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178 /** @defgroup RCC_HSE_Config HSE Config
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181 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
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182 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
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183 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
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188 /** @defgroup RCC_LSE_Config LSE Config
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191 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
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192 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
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193 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
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194 #if defined(RCC_BDCR_LSESYSDIS)
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195 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */
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196 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */
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197 #endif /* RCC_BDCR_LSESYSDIS */
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202 /** @defgroup RCC_HSI_Config HSI Config
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205 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
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206 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
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208 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
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209 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
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210 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
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212 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
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213 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
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214 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
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219 /** @defgroup RCC_LSI_Config LSI Config
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222 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
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223 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
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227 #if defined(RCC_CSR_LSIPREDIV)
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229 /** @defgroup RCC_LSI_Div LSI Div
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232 #define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */
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233 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */
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237 #endif /* RCC_CSR_LSIPREDIV */
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239 /** @defgroup RCC_MSI_Config MSI Config
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242 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */
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243 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
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245 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */
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250 #if defined(RCC_HSI48_SUPPORT)
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251 /** @defgroup RCC_HSI48_Config HSI48 Config
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254 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
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255 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
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260 /** @defgroup RCC_HSI48_Config HSI48 Config
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263 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
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267 #endif /* RCC_HSI48_SUPPORT */
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269 /** @defgroup RCC_PLL_Config PLL Config
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272 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
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273 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
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274 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */
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279 #if defined(RCC_PLLP_SUPPORT)
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280 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
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283 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
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284 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
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285 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
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286 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
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287 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
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288 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
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289 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
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290 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
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291 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
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292 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
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293 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
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294 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
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295 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
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296 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
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297 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
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298 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
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299 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
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300 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
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301 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
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302 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
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303 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
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304 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
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305 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
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306 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
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307 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
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308 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
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309 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
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310 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
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311 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
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312 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
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313 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
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315 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
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316 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
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317 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
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321 #endif /* RCC_PLLP_SUPPORT */
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323 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
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326 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
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327 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
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328 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
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329 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
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334 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
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337 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
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338 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
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339 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
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340 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
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345 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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348 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
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349 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
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350 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
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351 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
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356 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
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359 #if defined(RCC_PLLSAI2_SUPPORT)
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360 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
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361 #elif defined(RCC_PLLSAI1_SUPPORT)
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362 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
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363 #endif /* RCC_PLLSAI2_SUPPORT */
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364 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
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365 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
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369 #if defined(RCC_PLLSAI1_SUPPORT)
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371 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
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374 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
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375 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
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376 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
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380 #endif /* RCC_PLLSAI1_SUPPORT */
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382 #if defined(RCC_PLLSAI2_SUPPORT)
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384 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
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387 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
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388 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
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389 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */
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390 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
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391 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
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392 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
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394 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */
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395 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
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400 #endif /* RCC_PLLSAI2_SUPPORT */
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402 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
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405 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
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406 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
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407 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
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408 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
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409 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
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410 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
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411 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
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412 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
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413 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
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414 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
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415 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
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416 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
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421 /** @defgroup RCC_System_Clock_Type System Clock Type
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424 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
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425 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
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426 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
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427 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
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432 /** @defgroup RCC_System_Clock_Source System Clock Source
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435 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
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436 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
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437 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
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438 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
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443 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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446 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
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447 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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448 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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449 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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454 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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457 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
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458 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
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459 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
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460 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
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461 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
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462 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
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463 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
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464 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
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465 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
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470 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
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473 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
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474 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
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475 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
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476 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
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477 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
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482 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
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485 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
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486 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
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487 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
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488 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
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493 /** @defgroup RCC_MCO_Index MCO Index
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496 #define RCC_MCO1 0x00000000U
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497 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
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502 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
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505 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
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506 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
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507 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
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508 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
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509 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
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510 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
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511 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
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512 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
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513 #if defined(RCC_HSI48_SUPPORT)
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514 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
\r
515 #endif /* RCC_HSI48_SUPPORT */
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520 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
\r
523 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
\r
524 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
\r
525 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
\r
526 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
\r
527 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
\r
532 /** @defgroup RCC_Interrupt Interrupts
\r
535 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
\r
536 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
\r
537 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
\r
538 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
\r
539 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
\r
540 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
\r
541 #if defined(RCC_PLLSAI1_SUPPORT)
\r
542 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
\r
543 #endif /* RCC_PLLSAI1_SUPPORT */
\r
544 #if defined(RCC_PLLSAI2_SUPPORT)
\r
545 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
\r
546 #endif /* RCC_PLLSAI2_SUPPORT */
\r
547 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
\r
548 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
\r
549 #if defined(RCC_HSI48_SUPPORT)
\r
550 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
\r
551 #endif /* RCC_HSI48_SUPPORT */
\r
556 /** @defgroup RCC_Flag Flags
\r
557 * Elements values convention: XXXYYYYYb
\r
558 * - YYYYY : Flag position in the register
\r
559 * - XXX : Register index
\r
560 * - 001: CR register
\r
561 * - 010: BDCR register
\r
562 * - 011: CSR register
\r
563 * - 100: CRRCR register
\r
566 /* Flags in the CR register */
\r
567 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */
\r
568 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
\r
569 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
\r
570 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
\r
571 #if defined(RCC_PLLSAI1_SUPPORT)
\r
572 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */
\r
573 #endif /* RCC_PLLSAI1_SUPPORT */
\r
574 #if defined(RCC_PLLSAI2_SUPPORT)
\r
575 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */
\r
576 #endif /* RCC_PLLSAI2_SUPPORT */
\r
578 /* Flags in the BDCR register */
\r
579 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
\r
580 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
\r
582 /* Flags in the CSR register */
\r
583 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
\r
584 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */
\r
585 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
\r
586 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
\r
587 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
\r
588 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
\r
589 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
\r
590 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
\r
591 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
\r
593 #if defined(RCC_HSI48_SUPPORT)
\r
594 /* Flags in the CRRCR register */
\r
595 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
\r
596 #endif /* RCC_HSI48_SUPPORT */
\r
601 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
\r
604 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
\r
605 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
\r
606 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
\r
607 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
\r
612 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
\r
615 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
\r
616 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
\r
625 /* Exported macros -----------------------------------------------------------*/
\r
627 /** @defgroup RCC_Exported_Macros RCC Exported Macros
\r
631 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
\r
632 * @brief Enable or disable the AHB1 peripheral clock.
\r
633 * @note After reset, the peripheral clock (used for registers read/write access)
\r
634 * is disabled and the application software has to enable this clock before
\r
639 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
\r
640 __IO uint32_t tmpreg; \
\r
641 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
\r
642 /* Delay after an RCC peripheral clock enabling */ \
\r
643 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
\r
647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
\r
648 __IO uint32_t tmpreg; \
\r
649 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
\r
650 /* Delay after an RCC peripheral clock enabling */ \
\r
651 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
\r
655 #if defined(DMAMUX1)
\r
656 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
\r
657 __IO uint32_t tmpreg; \
\r
658 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
\r
659 /* Delay after an RCC peripheral clock enabling */ \
\r
660 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
\r
663 #endif /* DMAMUX1 */
\r
665 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
\r
666 __IO uint32_t tmpreg; \
\r
667 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
\r
668 /* Delay after an RCC peripheral clock enabling */ \
\r
669 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
\r
673 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
\r
674 __IO uint32_t tmpreg; \
\r
675 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
\r
676 /* Delay after an RCC peripheral clock enabling */ \
\r
677 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
\r
681 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
\r
682 __IO uint32_t tmpreg; \
\r
683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
\r
684 /* Delay after an RCC peripheral clock enabling */ \
\r
685 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
\r
690 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
\r
691 __IO uint32_t tmpreg; \
\r
692 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
\r
693 /* Delay after an RCC peripheral clock enabling */ \
\r
694 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
\r
699 #if defined(GFXMMU)
\r
700 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
\r
701 __IO uint32_t tmpreg; \
\r
702 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
\r
703 /* Delay after an RCC peripheral clock enabling */ \
\r
704 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
\r
707 #endif /* GFXMMU */
\r
710 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
\r
712 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
\r
714 #if defined(DMAMUX1)
\r
715 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
\r
716 #endif /* DMAMUX1 */
\r
718 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
\r
720 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
\r
722 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
\r
725 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
\r
728 #if defined(GFXMMU)
\r
729 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)
\r
730 #endif /* GFXMMU */
\r
736 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
\r
737 * @brief Enable or disable the AHB2 peripheral clock.
\r
738 * @note After reset, the peripheral clock (used for registers read/write access)
\r
739 * is disabled and the application software has to enable this clock before
\r
744 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
\r
745 __IO uint32_t tmpreg; \
\r
746 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
\r
747 /* Delay after an RCC peripheral clock enabling */ \
\r
748 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
\r
752 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
\r
753 __IO uint32_t tmpreg; \
\r
754 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
\r
755 /* Delay after an RCC peripheral clock enabling */ \
\r
756 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
\r
760 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
\r
761 __IO uint32_t tmpreg; \
\r
762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
\r
763 /* Delay after an RCC peripheral clock enabling */ \
\r
764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
\r
769 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
\r
770 __IO uint32_t tmpreg; \
\r
771 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
\r
772 /* Delay after an RCC peripheral clock enabling */ \
\r
773 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
\r
779 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
\r
780 __IO uint32_t tmpreg; \
\r
781 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
\r
782 /* Delay after an RCC peripheral clock enabling */ \
\r
783 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
\r
789 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
\r
790 __IO uint32_t tmpreg; \
\r
791 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
\r
792 /* Delay after an RCC peripheral clock enabling */ \
\r
793 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
\r
799 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
\r
800 __IO uint32_t tmpreg; \
\r
801 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
\r
802 /* Delay after an RCC peripheral clock enabling */ \
\r
803 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
\r
808 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
\r
809 __IO uint32_t tmpreg; \
\r
810 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
\r
811 /* Delay after an RCC peripheral clock enabling */ \
\r
812 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
\r
817 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
\r
818 __IO uint32_t tmpreg; \
\r
819 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
\r
820 /* Delay after an RCC peripheral clock enabling */ \
\r
821 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
\r
826 #if defined(USB_OTG_FS)
\r
827 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
\r
828 __IO uint32_t tmpreg; \
\r
829 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
\r
830 /* Delay after an RCC peripheral clock enabling */ \
\r
831 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
\r
834 #endif /* USB_OTG_FS */
\r
836 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
\r
837 __IO uint32_t tmpreg; \
\r
838 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
\r
839 /* Delay after an RCC peripheral clock enabling */ \
\r
840 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
\r
845 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
\r
846 __IO uint32_t tmpreg; \
\r
847 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
\r
848 /* Delay after an RCC peripheral clock enabling */ \
\r
849 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
\r
855 #define __HAL_RCC_AES_CLK_ENABLE() do { \
\r
856 __IO uint32_t tmpreg; \
\r
857 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
\r
858 /* Delay after an RCC peripheral clock enabling */ \
\r
859 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
\r
865 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
\r
866 __IO uint32_t tmpreg; \
\r
867 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
\r
868 /* Delay after an RCC peripheral clock enabling */ \
\r
869 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
\r
874 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
\r
875 __IO uint32_t tmpreg; \
\r
876 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
\r
877 /* Delay after an RCC peripheral clock enabling */ \
\r
878 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
\r
882 #if defined(OCTOSPIM)
\r
883 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
\r
884 __IO uint32_t tmpreg; \
\r
885 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
\r
886 /* Delay after an RCC peripheral clock enabling */ \
\r
887 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
\r
890 #endif /* OCTOSPIM */
\r
892 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
\r
893 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
\r
894 __IO uint32_t tmpreg; \
\r
895 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
\r
896 /* Delay after an RCC peripheral clock enabling */ \
\r
897 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
\r
900 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
\r
903 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
\r
905 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
\r
907 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
\r
910 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
\r
914 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
\r
918 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
\r
922 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
\r
925 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
\r
928 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
\r
931 #if defined(USB_OTG_FS)
\r
932 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
\r
933 #endif /* USB_OTG_FS */
\r
935 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
\r
938 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
\r
942 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
\r
946 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
\r
949 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
\r
951 #if defined(OCTOSPIM)
\r
952 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)
\r
953 #endif /* OCTOSPIM */
\r
955 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
\r
956 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)
\r
957 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
\r
963 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
\r
964 * @brief Enable or disable the AHB3 peripheral clock.
\r
965 * @note After reset, the peripheral clock (used for registers read/write access)
\r
966 * is disabled and the application software has to enable this clock before
\r
971 #if defined(FMC_BANK1)
\r
972 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
\r
973 __IO uint32_t tmpreg; \
\r
974 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
\r
975 /* Delay after an RCC peripheral clock enabling */ \
\r
976 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
\r
979 #endif /* FMC_BANK1 */
\r
981 #if defined(QUADSPI)
\r
982 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
\r
983 __IO uint32_t tmpreg; \
\r
984 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
\r
985 /* Delay after an RCC peripheral clock enabling */ \
\r
986 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
\r
989 #endif /* QUADSPI */
\r
991 #if defined(OCTOSPI1)
\r
992 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
\r
993 __IO uint32_t tmpreg; \
\r
994 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
\r
995 /* Delay after an RCC peripheral clock enabling */ \
\r
996 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
\r
999 #endif /* OCTOSPI1 */
\r
1001 #if defined(OCTOSPI2)
\r
1002 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
\r
1003 __IO uint32_t tmpreg; \
\r
1004 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
\r
1005 /* Delay after an RCC peripheral clock enabling */ \
\r
1006 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
\r
1009 #endif /* OCTOSPI2 */
\r
1011 #if defined(FMC_BANK1)
\r
1012 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
\r
1013 #endif /* FMC_BANK1 */
\r
1015 #if defined(QUADSPI)
\r
1016 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
\r
1017 #endif /* QUADSPI */
\r
1019 #if defined(OCTOSPI1)
\r
1020 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)
\r
1021 #endif /* OCTOSPI1 */
\r
1023 #if defined(OCTOSPI2)
\r
1024 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)
\r
1025 #endif /* OCTOSPI2 */
\r
1031 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
\r
1032 * @brief Enable or disable the APB1 peripheral clock.
\r
1033 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1034 * is disabled and the application software has to enable this clock before
\r
1039 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
\r
1040 __IO uint32_t tmpreg; \
\r
1041 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
\r
1042 /* Delay after an RCC peripheral clock enabling */ \
\r
1043 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
\r
1048 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
\r
1049 __IO uint32_t tmpreg; \
\r
1050 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
\r
1051 /* Delay after an RCC peripheral clock enabling */ \
\r
1052 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
\r
1058 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
\r
1059 __IO uint32_t tmpreg; \
\r
1060 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
\r
1061 /* Delay after an RCC peripheral clock enabling */ \
\r
1062 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
\r
1068 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
\r
1069 __IO uint32_t tmpreg; \
\r
1070 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
\r
1071 /* Delay after an RCC peripheral clock enabling */ \
\r
1072 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
\r
1077 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
\r
1078 __IO uint32_t tmpreg; \
\r
1079 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
\r
1080 /* Delay after an RCC peripheral clock enabling */ \
\r
1081 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
\r
1086 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
\r
1087 __IO uint32_t tmpreg; \
\r
1088 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
\r
1089 /* Delay after an RCC peripheral clock enabling */ \
\r
1090 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
\r
1096 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
\r
1097 __IO uint32_t tmpreg; \
\r
1098 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
\r
1099 /* Delay after an RCC peripheral clock enabling */ \
\r
1100 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
\r
1105 #if defined(RCC_APB1ENR1_RTCAPBEN)
\r
1106 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
\r
1107 __IO uint32_t tmpreg; \
\r
1108 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
\r
1109 /* Delay after an RCC peripheral clock enabling */ \
\r
1110 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
\r
1113 #endif /* RCC_APB1ENR1_RTCAPBEN */
\r
1115 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
\r
1116 __IO uint32_t tmpreg; \
\r
1117 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
\r
1118 /* Delay after an RCC peripheral clock enabling */ \
\r
1119 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
\r
1124 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
\r
1125 __IO uint32_t tmpreg; \
\r
1126 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
\r
1127 /* Delay after an RCC peripheral clock enabling */ \
\r
1128 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
\r
1134 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
\r
1135 __IO uint32_t tmpreg; \
\r
1136 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
\r
1137 /* Delay after an RCC peripheral clock enabling */ \
\r
1138 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
\r
1143 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
\r
1144 __IO uint32_t tmpreg; \
\r
1145 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
\r
1146 /* Delay after an RCC peripheral clock enabling */ \
\r
1147 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
\r
1151 #if defined(USART3)
\r
1152 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
\r
1153 __IO uint32_t tmpreg; \
\r
1154 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
\r
1155 /* Delay after an RCC peripheral clock enabling */ \
\r
1156 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
\r
1159 #endif /* USART3 */
\r
1161 #if defined(UART4)
\r
1162 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
\r
1163 __IO uint32_t tmpreg; \
\r
1164 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
\r
1165 /* Delay after an RCC peripheral clock enabling */ \
\r
1166 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
\r
1169 #endif /* UART4 */
\r
1171 #if defined(UART5)
\r
1172 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
\r
1173 __IO uint32_t tmpreg; \
\r
1174 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
\r
1175 /* Delay after an RCC peripheral clock enabling */ \
\r
1176 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
\r
1179 #endif /* UART5 */
\r
1181 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
\r
1182 __IO uint32_t tmpreg; \
\r
1183 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
\r
1184 /* Delay after an RCC peripheral clock enabling */ \
\r
1185 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
\r
1190 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
\r
1191 __IO uint32_t tmpreg; \
\r
1192 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
\r
1193 /* Delay after an RCC peripheral clock enabling */ \
\r
1194 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
\r
1199 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
\r
1200 __IO uint32_t tmpreg; \
\r
1201 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
\r
1202 /* Delay after an RCC peripheral clock enabling */ \
\r
1203 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
\r
1208 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
\r
1209 __IO uint32_t tmpreg; \
\r
1210 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
\r
1211 /* Delay after an RCC peripheral clock enabling */ \
\r
1212 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
\r
1218 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
\r
1219 __IO uint32_t tmpreg; \
\r
1220 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
\r
1221 /* Delay after an RCC peripheral clock enabling */ \
\r
1222 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
\r
1228 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
\r
1229 __IO uint32_t tmpreg; \
\r
1230 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
\r
1231 /* Delay after an RCC peripheral clock enabling */ \
\r
1232 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
\r
1238 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
\r
1239 __IO uint32_t tmpreg; \
\r
1240 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
\r
1241 /* Delay after an RCC peripheral clock enabling */ \
\r
1242 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
\r
1248 #define __HAL_RCC_USB_CLK_ENABLE() do { \
\r
1249 __IO uint32_t tmpreg; \
\r
1250 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
\r
1251 /* Delay after an RCC peripheral clock enabling */ \
\r
1252 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
\r
1257 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
\r
1258 __IO uint32_t tmpreg; \
\r
1259 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
\r
1260 /* Delay after an RCC peripheral clock enabling */ \
\r
1261 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
\r
1266 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
\r
1267 __IO uint32_t tmpreg; \
\r
1268 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
\r
1269 /* Delay after an RCC peripheral clock enabling */ \
\r
1270 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
\r
1275 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
\r
1276 __IO uint32_t tmpreg; \
\r
1277 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
\r
1278 /* Delay after an RCC peripheral clock enabling */ \
\r
1279 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
\r
1283 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
\r
1284 __IO uint32_t tmpreg; \
\r
1285 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
\r
1286 /* Delay after an RCC peripheral clock enabling */ \
\r
1287 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
\r
1291 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
\r
1292 __IO uint32_t tmpreg; \
\r
1293 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
\r
1294 /* Delay after an RCC peripheral clock enabling */ \
\r
1295 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
\r
1299 #if defined(SWPMI1)
\r
1300 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
\r
1301 __IO uint32_t tmpreg; \
\r
1302 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
\r
1303 /* Delay after an RCC peripheral clock enabling */ \
\r
1304 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
\r
1307 #endif /* SWPMI1 */
\r
1309 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
\r
1310 __IO uint32_t tmpreg; \
\r
1311 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
\r
1312 /* Delay after an RCC peripheral clock enabling */ \
\r
1313 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
\r
1318 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
\r
1321 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
\r
1325 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
\r
1329 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
\r
1332 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
\r
1335 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
\r
1339 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
\r
1342 #if defined(RCC_APB1ENR1_RTCAPBEN)
\r
1343 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
\r
1344 #endif /* RCC_APB1ENR1_RTCAPBEN */
\r
1347 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
\r
1351 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
\r
1354 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
\r
1356 #if defined(USART3)
\r
1357 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
\r
1358 #endif /* USART3 */
\r
1360 #if defined(UART4)
\r
1361 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
\r
1362 #endif /* UART4 */
\r
1364 #if defined(UART5)
\r
1365 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
\r
1366 #endif /* UART5 */
\r
1368 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
\r
1371 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
\r
1374 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
\r
1377 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
\r
1381 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
\r
1385 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
\r
1389 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
\r
1393 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
\r
1396 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
\r
1399 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
\r
1402 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
\r
1404 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
\r
1406 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
\r
1408 #if defined(SWPMI1)
\r
1409 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
\r
1410 #endif /* SWPMI1 */
\r
1412 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
\r
1418 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
\r
1419 * @brief Enable or disable the APB2 peripheral clock.
\r
1420 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1421 * is disabled and the application software has to enable this clock before
\r
1426 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
\r
1427 __IO uint32_t tmpreg; \
\r
1428 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
\r
1429 /* Delay after an RCC peripheral clock enabling */ \
\r
1430 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
\r
1434 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
\r
1435 __IO uint32_t tmpreg; \
\r
1436 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
\r
1437 /* Delay after an RCC peripheral clock enabling */ \
\r
1438 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
\r
1442 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
\r
1443 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
\r
1444 __IO uint32_t tmpreg; \
\r
1445 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
\r
1446 /* Delay after an RCC peripheral clock enabling */ \
\r
1447 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
\r
1450 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
\r
1452 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
\r
1453 __IO uint32_t tmpreg; \
\r
1454 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
\r
1455 /* Delay after an RCC peripheral clock enabling */ \
\r
1456 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
\r
1460 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
\r
1461 __IO uint32_t tmpreg; \
\r
1462 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
\r
1463 /* Delay after an RCC peripheral clock enabling */ \
\r
1464 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
\r
1469 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
\r
1470 __IO uint32_t tmpreg; \
\r
1471 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
\r
1472 /* Delay after an RCC peripheral clock enabling */ \
\r
1473 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
\r
1478 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
\r
1479 __IO uint32_t tmpreg; \
\r
1480 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
\r
1481 /* Delay after an RCC peripheral clock enabling */ \
\r
1482 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
\r
1487 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
\r
1488 __IO uint32_t tmpreg; \
\r
1489 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
\r
1490 /* Delay after an RCC peripheral clock enabling */ \
\r
1491 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
\r
1495 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
\r
1496 __IO uint32_t tmpreg; \
\r
1497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
\r
1498 /* Delay after an RCC peripheral clock enabling */ \
\r
1499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
\r
1503 #if defined(TIM17)
\r
1504 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
\r
1505 __IO uint32_t tmpreg; \
\r
1506 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
\r
1507 /* Delay after an RCC peripheral clock enabling */ \
\r
1508 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
\r
1511 #endif /* TIM17 */
\r
1514 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
\r
1515 __IO uint32_t tmpreg; \
\r
1516 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
\r
1517 /* Delay after an RCC peripheral clock enabling */ \
\r
1518 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
\r
1524 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
\r
1525 __IO uint32_t tmpreg; \
\r
1526 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
\r
1527 /* Delay after an RCC peripheral clock enabling */ \
\r
1528 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
\r
1533 #if defined(DFSDM1_Filter0)
\r
1534 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
\r
1535 __IO uint32_t tmpreg; \
\r
1536 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
\r
1537 /* Delay after an RCC peripheral clock enabling */ \
\r
1538 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
\r
1541 #endif /* DFSDM1_Filter0 */
\r
1544 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
\r
1545 __IO uint32_t tmpreg; \
\r
1546 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
\r
1547 /* Delay after an RCC peripheral clock enabling */ \
\r
1548 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
\r
1554 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
\r
1555 __IO uint32_t tmpreg; \
\r
1556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
\r
1557 /* Delay after an RCC peripheral clock enabling */ \
\r
1558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
\r
1564 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
\r
1566 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
\r
1567 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
\r
1568 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
\r
1570 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
\r
1572 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
\r
1575 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
\r
1578 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
\r
1580 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
\r
1582 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
\r
1584 #if defined(TIM17)
\r
1585 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
\r
1586 #endif /* TIM17 */
\r
1589 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
\r
1593 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
\r
1596 #if defined(DFSDM1_Filter0)
\r
1597 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
\r
1598 #endif /* DFSDM1_Filter0 */
\r
1601 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)
\r
1605 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)
\r
1612 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
\r
1613 * @brief Check whether the AHB1 peripheral clock is enabled or not.
\r
1614 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1615 * is disabled and the application software has to enable this clock before
\r
1620 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
\r
1622 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
\r
1624 #if defined(DMAMUX1)
\r
1625 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
\r
1626 #endif /* DMAMUX1 */
\r
1628 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
\r
1630 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
\r
1632 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)
\r
1634 #if defined(DMA2D)
\r
1635 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)
\r
1636 #endif /* DMA2D */
\r
1638 #if defined(GFXMMU)
\r
1639 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)
\r
1640 #endif /* GFXMMU */
\r
1643 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
\r
1645 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
\r
1647 #if defined(DMAMUX1)
\r
1648 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
\r
1649 #endif /* DMAMUX1 */
\r
1651 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
\r
1653 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
\r
1655 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)
\r
1657 #if defined(DMA2D)
\r
1658 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)
\r
1659 #endif /* DMA2D */
\r
1661 #if defined(GFXMMU)
\r
1662 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)
\r
1663 #endif /* GFXMMU */
\r
1669 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
\r
1670 * @brief Check whether the AHB2 peripheral clock is enabled or not.
\r
1671 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1672 * is disabled and the application software has to enable this clock before
\r
1677 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
\r
1679 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
\r
1681 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
\r
1683 #if defined(GPIOD)
\r
1684 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
\r
1685 #endif /* GPIOD */
\r
1687 #if defined(GPIOE)
\r
1688 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
\r
1689 #endif /* GPIOE */
\r
1691 #if defined(GPIOF)
\r
1692 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
\r
1693 #endif /* GPIOF */
\r
1695 #if defined(GPIOG)
\r
1696 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
\r
1697 #endif /* GPIOG */
\r
1699 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)
\r
1701 #if defined(GPIOI)
\r
1702 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)
\r
1703 #endif /* GPIOI */
\r
1705 #if defined(USB_OTG_FS)
\r
1706 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)
\r
1707 #endif /* USB_OTG_FS */
\r
1709 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)
\r
1712 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)
\r
1716 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
\r
1720 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)
\r
1723 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
\r
1726 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
\r
1728 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
\r
1730 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
\r
1732 #if defined(GPIOD)
\r
1733 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
\r
1734 #endif /* GPIOD */
\r
1736 #if defined(GPIOE)
\r
1737 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
\r
1738 #endif /* GPIOE */
\r
1740 #if defined(GPIOF)
\r
1741 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
\r
1742 #endif /* GPIOF */
\r
1744 #if defined(GPIOG)
\r
1745 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
\r
1746 #endif /* GPIOG */
\r
1748 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)
\r
1750 #if defined(GPIOI)
\r
1751 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)
\r
1752 #endif /* GPIOI */
\r
1754 #if defined(USB_OTG_FS)
\r
1755 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)
\r
1756 #endif /* USB_OTG_FS */
\r
1758 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)
\r
1761 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)
\r
1765 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
\r
1769 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)
\r
1772 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
\r
1778 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
\r
1779 * @brief Check whether the AHB3 peripheral clock is enabled or not.
\r
1780 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1781 * is disabled and the application software has to enable this clock before
\r
1786 #if defined(FMC_BANK1)
\r
1787 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
\r
1788 #endif /* FMC_BANK1 */
\r
1790 #if defined(QUADSPI)
\r
1791 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
\r
1792 #endif /* QUADSPI */
\r
1794 #if defined(FMC_BANK1)
\r
1795 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
\r
1796 #endif /* FMC_BANK1 */
\r
1798 #if defined(QUADSPI)
\r
1799 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
\r
1800 #endif /* QUADSPI */
\r
1806 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
\r
1807 * @brief Check whether the APB1 peripheral clock is enabled or not.
\r
1808 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1809 * is disabled and the application software has to enable this clock before
\r
1814 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
\r
1817 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
\r
1821 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
\r
1825 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
\r
1828 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
\r
1831 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
\r
1835 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)
\r
1838 #if defined(RCC_APB1ENR1_RTCAPBEN)
\r
1839 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
\r
1840 #endif /* RCC_APB1ENR1_RTCAPBEN */
\r
1842 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
\r
1845 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
\r
1849 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
\r
1852 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
\r
1854 #if defined(USART3)
\r
1855 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
\r
1856 #endif /* USART3 */
\r
1858 #if defined(UART4)
\r
1859 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
\r
1860 #endif /* UART4 */
\r
1862 #if defined(UART5)
\r
1863 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
\r
1864 #endif /* UART5 */
\r
1866 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
\r
1869 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
\r
1872 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
\r
1875 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
\r
1879 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
\r
1883 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)
\r
1887 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)
\r
1891 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)
\r
1894 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
\r
1897 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)
\r
1900 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)
\r
1902 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
\r
1904 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
\r
1906 #if defined(SWPMI1)
\r
1907 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)
\r
1908 #endif /* SWPMI1 */
\r
1910 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)
\r
1913 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
\r
1916 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
\r
1920 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
\r
1924 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
\r
1927 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
\r
1930 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
\r
1934 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)
\r
1937 #if defined(RCC_APB1ENR1_RTCAPBEN)
\r
1938 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
\r
1939 #endif /* RCC_APB1ENR1_RTCAPBEN */
\r
1941 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
\r
1944 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
\r
1948 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
\r
1951 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
\r
1953 #if defined(USART3)
\r
1954 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
\r
1955 #endif /* USART3 */
\r
1957 #if defined(UART4)
\r
1958 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
\r
1959 #endif /* UART4 */
\r
1961 #if defined(UART5)
\r
1962 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
\r
1963 #endif /* UART5 */
\r
1965 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
\r
1968 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
\r
1971 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
\r
1974 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
\r
1978 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
\r
1982 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)
\r
1986 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)
\r
1990 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)
\r
1993 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
\r
1996 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)
\r
1999 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)
\r
2001 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
\r
2003 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
\r
2005 #if defined(SWPMI1)
\r
2006 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)
\r
2007 #endif /* SWPMI1 */
\r
2009 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)
\r
2015 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
\r
2016 * @brief Check whether the APB2 peripheral clock is enabled or not.
\r
2017 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2018 * is disabled and the application software has to enable this clock before
\r
2023 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
\r
2025 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)
\r
2027 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
\r
2028 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)
\r
2029 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
\r
2031 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
\r
2033 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
\r
2036 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
\r
2039 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
\r
2041 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
\r
2043 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
\r
2045 #if defined(TIM17)
\r
2046 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
\r
2047 #endif /* TIM17 */
\r
2050 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
\r
2054 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
\r
2057 #if defined(DFSDM1_Filter0)
\r
2058 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)
\r
2059 #endif /* DFSDM1_Filter0 */
\r
2062 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)
\r
2066 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)
\r
2070 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
\r
2072 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
\r
2073 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)
\r
2074 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
\r
2076 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
\r
2078 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
\r
2081 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
\r
2084 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
\r
2086 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
\r
2088 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
\r
2090 #if defined(TIM17)
\r
2091 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
\r
2092 #endif /* TIM17 */
\r
2095 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
\r
2099 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
\r
2102 #if defined(DFSDM1_Filter0)
\r
2103 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)
\r
2104 #endif /* DFSDM1_Filter0 */
\r
2107 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)
\r
2111 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)
\r
2118 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
\r
2119 * @brief Force or release AHB1 peripheral reset.
\r
2122 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
\r
2124 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
\r
2126 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
\r
2128 #if defined(DMAMUX1)
\r
2129 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
\r
2130 #endif /* DMAMUX1 */
\r
2132 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
\r
2134 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
\r
2136 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
\r
2138 #if defined(DMA2D)
\r
2139 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
\r
2140 #endif /* DMA2D */
\r
2142 #if defined(GFXMMU)
\r
2143 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
\r
2144 #endif /* GFXMMU */
\r
2147 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
\r
2149 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
\r
2151 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
\r
2153 #if defined(DMAMUX1)
\r
2154 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
\r
2155 #endif /* DMAMUX1 */
\r
2157 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
\r
2159 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
\r
2161 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
\r
2163 #if defined(DMA2D)
\r
2164 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
\r
2165 #endif /* DMA2D */
\r
2167 #if defined(GFXMMU)
\r
2168 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
\r
2169 #endif /* GFXMMU */
\r
2175 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
\r
2176 * @brief Force or release AHB2 peripheral reset.
\r
2179 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
\r
2181 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
\r
2183 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
\r
2185 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
\r
2187 #if defined(GPIOD)
\r
2188 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
\r
2189 #endif /* GPIOD */
\r
2191 #if defined(GPIOE)
\r
2192 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
\r
2193 #endif /* GPIOE */
\r
2195 #if defined(GPIOF)
\r
2196 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
\r
2197 #endif /* GPIOF */
\r
2199 #if defined(GPIOG)
\r
2200 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
\r
2201 #endif /* GPIOG */
\r
2203 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
\r
2205 #if defined(GPIOI)
\r
2206 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
\r
2207 #endif /* GPIOI */
\r
2209 #if defined(USB_OTG_FS)
\r
2210 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
\r
2211 #endif /* USB_OTG_FS */
\r
2213 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
\r
2216 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
\r
2220 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
\r
2224 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
\r
2227 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
\r
2229 #if defined(OCTOSPIM)
\r
2230 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
\r
2231 #endif /* OCTOSPIM */
\r
2233 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
\r
2234 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
\r
2235 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
\r
2238 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
\r
2240 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
\r
2242 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
\r
2244 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
\r
2246 #if defined(GPIOD)
\r
2247 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
\r
2248 #endif /* GPIOD */
\r
2250 #if defined(GPIOE)
\r
2251 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
\r
2252 #endif /* GPIOE */
\r
2254 #if defined(GPIOF)
\r
2255 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
\r
2256 #endif /* GPIOF */
\r
2258 #if defined(GPIOG)
\r
2259 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
\r
2260 #endif /* GPIOG */
\r
2262 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
\r
2264 #if defined(GPIOI)
\r
2265 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
\r
2266 #endif /* GPIOI */
\r
2268 #if defined(USB_OTG_FS)
\r
2269 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
\r
2270 #endif /* USB_OTG_FS */
\r
2272 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
\r
2275 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
\r
2279 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
\r
2283 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
\r
2286 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
\r
2288 #if defined(OCTOSPIM)
\r
2289 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
\r
2290 #endif /* OCTOSPIM */
\r
2292 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
\r
2293 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
\r
2294 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
\r
2300 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
\r
2301 * @brief Force or release AHB3 peripheral reset.
\r
2304 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
\r
2306 #if defined(FMC_BANK1)
\r
2307 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
\r
2308 #endif /* FMC_BANK1 */
\r
2310 #if defined(QUADSPI)
\r
2311 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
\r
2312 #endif /* QUADSPI */
\r
2314 #if defined(OCTOSPI1)
\r
2315 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
\r
2316 #endif /* OCTOSPI1 */
\r
2318 #if defined(OCTOSPI2)
\r
2319 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
\r
2320 #endif /* OCTOSPI2 */
\r
2322 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
\r
2324 #if defined(FMC_BANK1)
\r
2325 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
\r
2326 #endif /* FMC_BANK1 */
\r
2328 #if defined(QUADSPI)
\r
2329 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
\r
2330 #endif /* QUADSPI */
\r
2332 #if defined(OCTOSPI1)
\r
2333 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
\r
2334 #endif /* OCTOSPI1 */
\r
2336 #if defined(OCTOSPI2)
\r
2337 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
\r
2338 #endif /* OCTOSPI2 */
\r
2344 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
\r
2345 * @brief Force or release APB1 peripheral reset.
\r
2348 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
\r
2350 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
\r
2353 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
\r
2357 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
\r
2361 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
\r
2364 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
\r
2367 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
\r
2371 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
\r
2375 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
\r
2379 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
\r
2382 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
\r
2384 #if defined(USART3)
\r
2385 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
\r
2386 #endif /* USART3 */
\r
2388 #if defined(UART4)
\r
2389 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
\r
2390 #endif /* UART4 */
\r
2392 #if defined(UART5)
\r
2393 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
\r
2394 #endif /* UART5 */
\r
2396 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
\r
2399 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
\r
2402 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
\r
2405 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
\r
2409 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
\r
2413 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
\r
2417 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
\r
2421 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
\r
2424 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
\r
2427 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
\r
2430 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
\r
2432 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
\r
2434 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
\r
2436 #if defined(SWPMI1)
\r
2437 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
\r
2438 #endif /* SWPMI1 */
\r
2440 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
\r
2443 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
\r
2445 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
\r
2448 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
\r
2452 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
\r
2456 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
\r
2459 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
\r
2462 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
\r
2466 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
\r
2470 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
\r
2474 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
\r
2477 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
\r
2479 #if defined(USART3)
\r
2480 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
\r
2481 #endif /* USART3 */
\r
2483 #if defined(UART4)
\r
2484 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
\r
2485 #endif /* UART4 */
\r
2487 #if defined(UART5)
\r
2488 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
\r
2489 #endif /* UART5 */
\r
2491 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
\r
2494 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
\r
2497 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
\r
2500 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
\r
2504 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
\r
2508 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
\r
2512 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
\r
2516 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
\r
2519 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
\r
2522 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
\r
2525 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
\r
2527 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
\r
2529 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
\r
2531 #if defined(SWPMI1)
\r
2532 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
\r
2533 #endif /* SWPMI1 */
\r
2535 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
\r
2541 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
\r
2542 * @brief Force or release APB2 peripheral reset.
\r
2545 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
\r
2547 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
\r
2549 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
\r
2550 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
\r
2551 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
\r
2553 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
\r
2555 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
\r
2558 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
\r
2561 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
\r
2563 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
\r
2565 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
\r
2567 #if defined(TIM17)
\r
2568 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
\r
2569 #endif /* TIM17 */
\r
2572 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
\r
2576 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
\r
2579 #if defined(DFSDM1_Filter0)
\r
2580 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
\r
2581 #endif /* DFSDM1_Filter0 */
\r
2584 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
\r
2588 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
\r
2592 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
\r
2594 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
\r
2596 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
\r
2597 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
\r
2598 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
\r
2600 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
\r
2602 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
\r
2605 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
\r
2608 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
\r
2610 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
\r
2612 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
\r
2614 #if defined(TIM17)
\r
2615 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
\r
2616 #endif /* TIM17 */
\r
2619 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
\r
2623 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
\r
2626 #if defined(DFSDM1_Filter0)
\r
2627 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
\r
2628 #endif /* DFSDM1_Filter0 */
\r
2631 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
\r
2635 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
\r
2642 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
\r
2643 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
2644 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
2645 * power consumption.
\r
2646 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
2647 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
2651 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
\r
2653 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
\r
2655 #if defined(DMAMUX1)
\r
2656 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
\r
2657 #endif /* DMAMUX1 */
\r
2659 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
\r
2661 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
\r
2663 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
\r
2665 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
\r
2667 #if defined(DMA2D)
\r
2668 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
\r
2669 #endif /* DMA2D */
\r
2671 #if defined(GFXMMU)
\r
2672 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
\r
2673 #endif /* GFXMMU */
\r
2676 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
\r
2678 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
\r
2680 #if defined(DMAMUX1)
\r
2681 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
\r
2682 #endif /* DMAMUX1 */
\r
2684 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
\r
2686 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
\r
2688 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
\r
2690 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
\r
2692 #if defined(DMA2D)
\r
2693 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
\r
2694 #endif /* DMA2D */
\r
2696 #if defined(GFXMMU)
\r
2697 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
\r
2698 #endif /* GFXMMU */
\r
2704 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
\r
2705 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
2706 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
2707 * power consumption.
\r
2708 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
2709 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
2713 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
\r
2715 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
\r
2717 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
\r
2719 #if defined(GPIOD)
\r
2720 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
\r
2721 #endif /* GPIOD */
\r
2723 #if defined(GPIOE)
\r
2724 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
\r
2725 #endif /* GPIOE */
\r
2727 #if defined(GPIOF)
\r
2728 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
\r
2729 #endif /* GPIOF */
\r
2731 #if defined(GPIOG)
\r
2732 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
\r
2733 #endif /* GPIOG */
\r
2735 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
\r
2737 #if defined(GPIOI)
\r
2738 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
\r
2739 #endif /* GPIOI */
\r
2741 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
\r
2743 #if defined(SRAM3)
\r
2744 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
\r
2745 #endif /* SRAM3 */
\r
2747 #if defined(USB_OTG_FS)
\r
2748 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
\r
2749 #endif /* USB_OTG_FS */
\r
2751 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
\r
2754 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
\r
2758 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
\r
2762 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
\r
2765 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
\r
2767 #if defined(OCTOSPIM)
\r
2768 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
\r
2769 #endif /* OCTOSPIM */
\r
2771 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
\r
2772 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
\r
2773 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
\r
2776 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
\r
2778 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
\r
2780 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
\r
2782 #if defined(GPIOD)
\r
2783 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
\r
2784 #endif /* GPIOD */
\r
2786 #if defined(GPIOE)
\r
2787 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
\r
2788 #endif /* GPIOE */
\r
2790 #if defined(GPIOF)
\r
2791 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
\r
2792 #endif /* GPIOF */
\r
2794 #if defined(GPIOG)
\r
2795 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
\r
2796 #endif /* GPIOG */
\r
2798 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
\r
2800 #if defined(GPIOI)
\r
2801 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
\r
2802 #endif /* GPIOI */
\r
2804 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
\r
2806 #if defined(SRAM3)
\r
2807 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
\r
2808 #endif /* SRAM3 */
\r
2810 #if defined(USB_OTG_FS)
\r
2811 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
\r
2812 #endif /* USB_OTG_FS */
\r
2814 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
\r
2817 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
\r
2821 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
\r
2825 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
\r
2828 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
\r
2830 #if defined(OCTOSPIM)
\r
2831 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
\r
2832 #endif /* OCTOSPIM */
\r
2834 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
\r
2835 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
\r
2836 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
\r
2842 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
\r
2843 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
2844 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
2845 * power consumption.
\r
2846 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
2847 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
2851 #if defined(QUADSPI)
\r
2852 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
\r
2853 #endif /* QUADSPI */
\r
2855 #if defined(OCTOSPI1)
\r
2856 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
\r
2857 #endif /* OCTOSPI1 */
\r
2859 #if defined(OCTOSPI2)
\r
2860 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
\r
2861 #endif /* OCTOSPI2 */
\r
2863 #if defined(FMC_BANK1)
\r
2864 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
\r
2865 #endif /* FMC_BANK1 */
\r
2867 #if defined(QUADSPI)
\r
2868 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
\r
2869 #endif /* QUADSPI */
\r
2871 #if defined(OCTOSPI1)
\r
2872 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
\r
2873 #endif /* OCTOSPI1 */
\r
2875 #if defined(OCTOSPI2)
\r
2876 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
\r
2877 #endif /* OCTOSPI2 */
\r
2879 #if defined(FMC_BANK1)
\r
2880 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
\r
2881 #endif /* FMC_BANK1 */
\r
2887 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
\r
2888 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
2889 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
2890 * power consumption.
\r
2891 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
2892 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
2896 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
\r
2899 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
\r
2903 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
\r
2907 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
\r
2910 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
\r
2913 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
\r
2917 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
\r
2920 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
\r
2921 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
\r
2922 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
\r
2924 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
\r
2927 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
\r
2931 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
\r
2934 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
\r
2936 #if defined(USART3)
\r
2937 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
\r
2938 #endif /* USART3 */
\r
2940 #if defined(UART4)
\r
2941 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
\r
2942 #endif /* UART4 */
\r
2944 #if defined(UART5)
\r
2945 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
\r
2946 #endif /* UART5 */
\r
2948 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
\r
2951 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
\r
2954 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
\r
2957 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
\r
2961 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
\r
2965 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
\r
2969 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
\r
2973 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
\r
2976 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
\r
2979 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
\r
2982 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
\r
2984 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
\r
2986 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
\r
2988 #if defined(SWPMI1)
\r
2989 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
\r
2990 #endif /* SWPMI1 */
\r
2992 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
\r
2995 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
\r
2998 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
\r
3002 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
\r
3006 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
\r
3009 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
\r
3012 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
\r
3016 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
\r
3019 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
\r
3020 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
\r
3021 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
\r
3023 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
\r
3026 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
\r
3030 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
\r
3033 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
\r
3035 #if defined(USART3)
\r
3036 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
\r
3037 #endif /* USART3 */
\r
3039 #if defined(UART4)
\r
3040 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
\r
3041 #endif /* UART4 */
\r
3043 #if defined(UART5)
\r
3044 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
\r
3045 #endif /* UART5 */
\r
3047 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
\r
3050 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
\r
3053 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
\r
3056 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
\r
3060 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
\r
3064 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
\r
3068 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
\r
3072 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
\r
3075 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
\r
3078 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
\r
3081 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
\r
3083 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
\r
3085 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
\r
3087 #if defined(SWPMI1)
\r
3088 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
\r
3089 #endif /* SWPMI1 */
\r
3091 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
\r
3097 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
\r
3098 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
3099 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3100 * power consumption.
\r
3101 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3102 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3106 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
\r
3108 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
\r
3109 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
\r
3110 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
\r
3112 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
\r
3114 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
\r
3117 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
\r
3120 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
\r
3122 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
\r
3124 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
\r
3126 #if defined(TIM17)
\r
3127 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
\r
3128 #endif /* TIM17 */
\r
3131 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
\r
3135 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
\r
3138 #if defined(DFSDM1_Filter0)
\r
3139 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
\r
3140 #endif /* DFSDM1_Filter0 */
\r
3143 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
\r
3147 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
\r
3151 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
\r
3153 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
\r
3154 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
\r
3155 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
\r
3157 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
\r
3159 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
\r
3162 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
\r
3165 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
\r
3167 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
\r
3169 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
\r
3171 #if defined(TIM17)
\r
3172 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
\r
3173 #endif /* TIM17 */
\r
3176 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
\r
3180 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
\r
3183 #if defined(DFSDM1_Filter0)
\r
3184 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
\r
3185 #endif /* DFSDM1_Filter0 */
\r
3188 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
\r
3192 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
\r
3199 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
\r
3200 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
\r
3201 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3202 * power consumption.
\r
3203 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3204 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3208 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
\r
3210 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
\r
3212 #if defined(DMAMUX1)
\r
3213 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
\r
3214 #endif /* DMAMUX1 */
\r
3216 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
\r
3218 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
\r
3220 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
\r
3222 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)
\r
3224 #if defined(DMA2D)
\r
3225 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)
\r
3226 #endif /* DMA2D */
\r
3228 #if defined(GFXMMU)
\r
3229 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)
\r
3230 #endif /* GFXMMU */
\r
3233 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
\r
3235 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
\r
3237 #if defined(DMAMUX1)
\r
3238 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
\r
3239 #endif /* DMAMUX1 */
\r
3241 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
\r
3243 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
\r
3245 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
\r
3247 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)
\r
3249 #if defined(DMA2D)
\r
3250 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)
\r
3251 #endif /* DMA2D */
\r
3253 #if defined(GFXMMU)
\r
3254 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)
\r
3255 #endif /* GFXMMU */
\r
3261 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
\r
3262 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
\r
3263 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3264 * power consumption.
\r
3265 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3266 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3270 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
\r
3272 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
\r
3274 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
\r
3276 #if defined(GPIOD)
\r
3277 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
\r
3278 #endif /* GPIOD */
\r
3280 #if defined(GPIOE)
\r
3281 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
\r
3282 #endif /* GPIOE */
\r
3284 #if defined(GPIOF)
\r
3285 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
\r
3286 #endif /* GPIOF */
\r
3288 #if defined(GPIOG)
\r
3289 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
\r
3290 #endif /* GPIOG */
\r
3292 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)
\r
3294 #if defined(GPIOI)
\r
3295 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)
\r
3296 #endif /* GPIOI */
\r
3298 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
\r
3300 #if defined(SRAM3)
\r
3301 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)
\r
3302 #endif /* SRAM3 */
\r
3304 #if defined(USB_OTG_FS)
\r
3305 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)
\r
3306 #endif /* USB_OTG_FS */
\r
3308 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)
\r
3311 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)
\r
3315 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
\r
3319 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)
\r
3322 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
\r
3324 #if defined(OCTOSPIM)
\r
3325 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)
\r
3326 #endif /* OCTOSPIM */
\r
3328 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
\r
3329 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)
\r
3330 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
\r
3333 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
\r
3335 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
\r
3337 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
\r
3339 #if defined(GPIOD)
\r
3340 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
\r
3341 #endif /* GPIOD */
\r
3343 #if defined(GPIOE)
\r
3344 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
\r
3345 #endif /* GPIOE */
\r
3347 #if defined(GPIOF)
\r
3348 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
\r
3349 #endif /* GPIOF */
\r
3351 #if defined(GPIOG)
\r
3352 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
\r
3353 #endif /* GPIOG */
\r
3355 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)
\r
3357 #if defined(GPIOI)
\r
3358 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)
\r
3359 #endif /* GPIOI */
\r
3361 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
\r
3363 #if defined(SRAM3)
\r
3364 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)
\r
3365 #endif /* SRAM3 */
\r
3367 #if defined(USB_OTG_FS)
\r
3368 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)
\r
3369 #endif /* USB_OTG_FS */
\r
3371 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)
\r
3374 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)
\r
3378 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
\r
3382 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)
\r
3385 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
\r
3387 #if defined(OCTOSPIM)
\r
3388 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)
\r
3389 #endif /* OCTOSPIM */
\r
3391 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
\r
3392 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)
\r
3393 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
\r
3399 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
\r
3400 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
\r
3401 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3402 * power consumption.
\r
3403 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3404 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3408 #if defined(QUADSPI)
\r
3409 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
\r
3410 #endif /* QUADSPI */
\r
3412 #if defined(OCTOSPI1)
\r
3413 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)
\r
3414 #endif /* OCTOSPI1 */
\r
3416 #if defined(OCTOSPI2)
\r
3417 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)
\r
3418 #endif /* OCTOSPI2 */
\r
3420 #if defined(FMC_BANK1)
\r
3421 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
\r
3422 #endif /* FMC_BANK1 */
\r
3425 #if defined(QUADSPI)
\r
3426 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
\r
3427 #endif /* QUADSPI */
\r
3429 #if defined(OCTOSPI1)
\r
3430 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)
\r
3431 #endif /* OCTOSPI1 */
\r
3433 #if defined(OCTOSPI2)
\r
3434 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)
\r
3435 #endif /* OCTOSPI2 */
\r
3437 #if defined(FMC_BANK1)
\r
3438 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
\r
3439 #endif /* FMC_BANK1 */
\r
3445 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
\r
3446 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
\r
3447 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3448 * power consumption.
\r
3449 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3450 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3454 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
\r
3457 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
\r
3461 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
\r
3465 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
\r
3468 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
\r
3471 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
\r
3475 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)
\r
3478 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
\r
3479 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
\r
3480 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
\r
3482 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
\r
3485 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
\r
3489 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
\r
3492 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
\r
3494 #if defined(USART3)
\r
3495 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
\r
3496 #endif /* USART3 */
\r
3498 #if defined(UART4)
\r
3499 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
\r
3500 #endif /* UART4 */
\r
3502 #if defined(UART5)
\r
3503 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
\r
3504 #endif /* UART5 */
\r
3506 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
\r
3509 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
\r
3512 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
\r
3515 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
\r
3519 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
\r
3523 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)
\r
3527 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)
\r
3531 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)
\r
3534 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
\r
3537 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)
\r
3540 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)
\r
3542 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
\r
3544 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
\r
3546 #if defined(SWPMI1)
\r
3547 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)
\r
3548 #endif /* SWPMI1 */
\r
3550 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)
\r
3553 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
\r
3556 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
\r
3560 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
\r
3564 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
\r
3567 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
\r
3570 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
\r
3574 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)
\r
3577 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
\r
3578 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
\r
3579 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
\r
3581 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
\r
3584 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
\r
3588 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
\r
3591 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
\r
3593 #if defined(USART3)
\r
3594 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
\r
3595 #endif /* USART3 */
\r
3597 #if defined(UART4)
\r
3598 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
\r
3599 #endif /* UART4 */
\r
3601 #if defined(UART5)
\r
3602 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
\r
3603 #endif /* UART5 */
\r
3605 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
\r
3608 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
\r
3611 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
\r
3614 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
\r
3618 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
\r
3622 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)
\r
3626 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)
\r
3630 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)
\r
3633 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
\r
3636 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)
\r
3639 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)
\r
3641 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
\r
3643 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
\r
3645 #if defined(SWPMI1)
\r
3646 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)
\r
3647 #endif /* SWPMI1 */
\r
3649 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)
\r
3655 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
\r
3656 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
\r
3657 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
3658 * power consumption.
\r
3659 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
3660 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
3664 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
\r
3666 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
\r
3667 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)
\r
3668 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
\r
3670 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
\r
3672 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
\r
3675 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
\r
3678 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
\r
3680 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
\r
3682 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
\r
3684 #if defined(TIM17)
\r
3685 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
\r
3686 #endif /* TIM17 */
\r
3689 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
\r
3693 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)
\r
3696 #if defined(DFSDM1_Filter0)
\r
3697 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)
\r
3698 #endif /* DFSDM1_Filter0 */
\r
3701 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)
\r
3705 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)
\r
3709 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
\r
3711 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
\r
3712 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)
\r
3713 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
\r
3715 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
\r
3717 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
\r
3720 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
\r
3723 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
\r
3725 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
\r
3727 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
\r
3729 #if defined(TIM17)
\r
3730 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
\r
3731 #endif /* TIM17 */
\r
3734 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
\r
3738 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)
\r
3741 #if defined(DFSDM1_Filter0)
\r
3742 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)
\r
3743 #endif /* DFSDM1_Filter0 */
\r
3746 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)
\r
3750 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)
\r
3757 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
\r
3761 /** @brief Macros to force or release the Backup domain reset.
\r
3762 * @note This function resets the RTC peripheral (including the backup registers)
\r
3763 * and the RTC clock source selection in RCC_CSR register.
\r
3764 * @note The BKPSRAM is not affected by this reset.
\r
3767 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
\r
3769 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
\r
3775 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
\r
3779 /** @brief Macros to enable or disable the RTC clock.
\r
3780 * @note As the RTC is in the Backup domain and write access is denied to
\r
3781 * this domain after reset, you have to enable write access using
\r
3782 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
\r
3783 * (to be done once after reset).
\r
3784 * @note These macros must be used after the RTC clock source was selected.
\r
3787 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
\r
3789 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
\r
3795 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
\r
3796 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
\r
3797 * It is used (enabled by hardware) as system clock source after startup
\r
3798 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
\r
3799 * of the HSE used directly or indirectly as system clock (if the Clock
\r
3800 * Security System CSS is enabled).
\r
3801 * @note HSI can not be stopped if it is used as system clock source. In this case,
\r
3802 * you have to select another source of the system clock then stop the HSI.
\r
3803 * @note After enabling the HSI, the application software should wait on HSIRDY
\r
3804 * flag to be set indicating that HSI clock is stable and can be used as
\r
3805 * system clock source.
\r
3806 * This parameter can be: ENABLE or DISABLE.
\r
3807 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
\r
3811 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
\r
3813 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
\r
3815 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
\r
3816 * @note The calibration is used to compensate for the variations in voltage
\r
3817 * and temperature that influence the frequency of the internal HSI RC.
\r
3818 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
\r
3819 * (default is RCC_HSICALIBRATION_DEFAULT).
\r
3820 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
\r
3823 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
\r
3824 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
\r
3827 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
\r
3828 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
\r
3829 * @note The enable of this function has not effect on the HSION bit.
\r
3830 * This parameter can be: ENABLE or DISABLE.
\r
3833 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
\r
3835 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
\r
3838 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
\r
3839 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
\r
3840 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
\r
3841 * speed because of the HSI startup time.
\r
3842 * @note The enable of this function has not effect on the HSION bit.
\r
3843 * This parameter can be: ENABLE or DISABLE.
\r
3846 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
\r
3848 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
\r
3851 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
\r
3852 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
\r
3853 * It is used (enabled by hardware) as system clock source after
\r
3854 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
\r
3855 * of failure of the HSE used directly or indirectly as system clock
\r
3856 * (if the Clock Security System CSS is enabled).
\r
3857 * @note MSI can not be stopped if it is used as system clock source.
\r
3858 * In this case, you have to select another source of the system
\r
3859 * clock then stop the MSI.
\r
3860 * @note After enabling the MSI, the application software should wait on
\r
3861 * MSIRDY flag to be set indicating that MSI clock is stable and can
\r
3862 * be used as system clock source.
\r
3863 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
\r
3867 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
\r
3869 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
\r
3871 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
\r
3872 * @note The calibration is used to compensate for the variations in voltage
\r
3873 * and temperature that influence the frequency of the internal MSI RC.
\r
3874 * Refer to the Application Note AN3300 for more details on how to
\r
3875 * calibrate the MSI.
\r
3876 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value
\r
3877 * (default is RCC_MSICALIBRATION_DEFAULT).
\r
3878 * This parameter must be a number between 0 and 255.
\r
3881 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
\r
3882 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
\r
3885 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
\r
3886 * @note After restart from Reset , the MSI clock is around 4 MHz.
\r
3887 * After stop the startup clock can be MSI (at any of its possible
\r
3888 * frequencies, the one that was used before entering stop mode) or HSI.
\r
3889 * After Standby its frequency can be selected between 4 possible values
\r
3890 * (1, 2, 4 or 8 MHz).
\r
3891 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
\r
3893 * @note The MSI clock range after reset can be modified on the fly.
\r
3894 * @param __MSIRANGEVALUE__ specifies the MSI clock range.
\r
3895 * This parameter must be one of the following values:
\r
3896 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
\r
3897 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
\r
3898 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
\r
3899 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
\r
3900 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
\r
3901 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
\r
3902 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
\r
3903 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
\r
3904 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
\r
3905 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
\r
3906 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
\r
3907 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
\r
3910 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
\r
3912 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
\r
3913 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
\r
3917 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
\r
3918 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
\r
3919 * @param __MSIRANGEVALUE__ specifies the MSI clock range.
\r
3920 * This parameter must be one of the following values:
\r
3921 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
\r
3922 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
\r
3923 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
\r
3924 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
\r
3927 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
\r
3928 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
\r
3930 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
\r
3931 * @retval MSI clock range.
\r
3932 * This parameter must be one of the following values:
\r
3933 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
\r
3934 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
\r
3935 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
\r
3936 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
\r
3937 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
\r
3938 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
\r
3939 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
\r
3940 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
\r
3941 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
\r
3942 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
\r
3943 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
\r
3944 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
\r
3946 #define __HAL_RCC_GET_MSI_RANGE() \
\r
3947 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \
\r
3948 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \
\r
3949 (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))
\r
3951 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
\r
3952 * @note After enabling the LSI, the application software should wait on
\r
3953 * LSIRDY flag to be set indicating that LSI clock is stable and can
\r
3954 * be used to clock the IWDG and/or the RTC.
\r
3955 * @note LSI can not be disabled if the IWDG is running.
\r
3956 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
\r
3960 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
\r
3962 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
\r
3965 * @brief Macro to configure the External High Speed oscillator (HSE).
\r
3966 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
\r
3967 * supported by this macro. User should request a transition to HSE Off
\r
3968 * first and then HSE On or HSE Bypass.
\r
3969 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
\r
3970 * software should wait on HSERDY flag to be set indicating that HSE clock
\r
3971 * is stable and can be used to clock the PLL and/or system clock.
\r
3972 * @note HSE state can not be changed if it is used directly or through the
\r
3973 * PLL as system clock. In this case, you have to select another source
\r
3974 * of the system clock then change the HSE state (ex. disable it).
\r
3975 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
\r
3976 * @note This function reset the CSSON bit, so if the clock security system(CSS)
\r
3977 * was previously enabled you have to enable it again after calling this
\r
3979 * @param __STATE__ specifies the new state of the HSE.
\r
3980 * This parameter can be one of the following values:
\r
3981 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
\r
3982 * 6 HSE oscillator clock cycles.
\r
3983 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
\r
3984 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
\r
3987 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
\r
3989 if((__STATE__) == RCC_HSE_ON) \
\r
3991 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
3993 else if((__STATE__) == RCC_HSE_BYPASS) \
\r
3995 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
3996 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
4000 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
\r
4001 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
4006 * @brief Macro to configure the External Low Speed oscillator (LSE).
\r
4007 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
\r
4008 * supported by this macro. User should request a transition to LSE Off
\r
4009 * first and then LSE On or LSE Bypass.
\r
4010 * @note As the LSE is in the Backup domain and write access is denied to
\r
4011 * this domain after reset, you have to enable write access using
\r
4012 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
4013 * (to be done once after reset).
\r
4014 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
\r
4015 * software should wait on LSERDY flag to be set indicating that LSE clock
\r
4016 * is stable and can be used to clock the RTC.
\r
4017 * @param __STATE__ specifies the new state of the LSE.
\r
4018 * This parameter can be one of the following values:
\r
4019 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
\r
4020 * 6 LSE oscillator clock cycles.
\r
4021 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
\r
4022 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
\r
4025 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
\r
4027 if((__STATE__) == RCC_LSE_ON) \
\r
4029 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
4031 else if((__STATE__) == RCC_LSE_BYPASS) \
\r
4033 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
4034 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
4038 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
4039 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
4043 #if defined(RCC_HSI48_SUPPORT)
\r
4045 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
\r
4046 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
\r
4047 * @note After enabling the HSI48, the application software should wait on HSI48RDY
\r
4048 * flag to be set indicating that HSI48 clock is stable.
\r
4049 * This parameter can be: ENABLE or DISABLE.
\r
4052 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
\r
4054 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
\r
4056 #endif /* RCC_HSI48_SUPPORT */
\r
4058 /** @brief Macros to configure the RTC clock (RTCCLK).
\r
4059 * @note As the RTC clock configuration bits are in the Backup domain and write
\r
4060 * access is denied to this domain after reset, you have to enable write
\r
4061 * access using the Power Backup Access macro before to configure
\r
4062 * the RTC clock source (to be done once after reset).
\r
4063 * @note Once the RTC clock is configured it cannot be changed unless the
\r
4064 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
\r
4065 * a Power On Reset (POR).
\r
4067 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
\r
4068 * This parameter can be one of the following values:
\r
4069 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
\r
4070 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
\r
4071 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
\r
4072 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
\r
4074 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
\r
4075 * work in STOP and STANDBY modes, and can be used as wakeup source.
\r
4076 * However, when the HSE clock is used as RTC clock source, the RTC
\r
4077 * cannot be used in STOP and STANDBY modes.
\r
4078 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
\r
4079 * RTC clock source).
\r
4082 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
\r
4083 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
\r
4086 /** @brief Macro to get the RTC clock source.
\r
4087 * @retval The returned value can be one of the following:
\r
4088 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
\r
4089 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
\r
4090 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
\r
4091 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
\r
4093 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
\r
4095 /** @brief Macros to enable or disable the main PLL.
\r
4096 * @note After enabling the main PLL, the application software should wait on
\r
4097 * PLLRDY flag to be set indicating that PLL clock is stable and can
\r
4098 * be used as system clock source.
\r
4099 * @note The main PLL can not be disabled if it is used as system clock source
\r
4100 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
\r
4103 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
\r
4105 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
\r
4107 /** @brief Macro to configure the PLL clock source.
\r
4108 * @note This function must be used only when the main PLL is disabled.
\r
4109 * @param __PLLSOURCE__ specifies the PLL entry clock source.
\r
4110 * This parameter can be one of the following values:
\r
4111 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
\r
4112 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
\r
4113 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
\r
4114 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
\r
4115 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
\r
4119 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
\r
4120 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
\r
4122 /** @brief Macro to configure the PLL source division factor M.
\r
4123 * @note This function must be used only when the main PLL is disabled.
\r
4124 * @param __PLLM__ specifies the division factor for PLL VCO input clock
\r
4125 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
\r
4126 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
\r
4127 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
\r
4128 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
\r
4129 * of 16 MHz to limit PLL jitter.
\r
4133 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
\r
4134 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
\r
4137 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
\r
4138 * @note This function must be used only when the main PLL is disabled.
\r
4140 * @param __PLLSOURCE__ specifies the PLL entry clock source.
\r
4141 * This parameter can be one of the following values:
\r
4142 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
\r
4143 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
\r
4144 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
\r
4145 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
\r
4146 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
\r
4148 * @param __PLLM__ specifies the division factor for PLL VCO input clock.
\r
4149 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
\r
4150 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
\r
4151 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
\r
4152 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
\r
4153 * of 16 MHz to limit PLL jitter.
\r
4155 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
\r
4156 * This parameter must be a number between 8 and 86.
\r
4157 * @note You have to set the PLLN parameter correctly to ensure that the VCO
\r
4158 * output frequency is between 64 and 344 MHz.
\r
4160 * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device.
\r
4161 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
\r
4164 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
\r
4165 * This parameter must be in the range (2, 4, 6 or 8).
\r
4166 * @note If the USB OTG FS is used in your application, you have to set the
\r
4167 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
\r
4168 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
\r
4170 * @param __PLLR__ specifies the division factor for the main system clock.
\r
4171 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
\r
4172 * This parameter must be in the range (2, 4, 6 or 8).
\r
4175 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
\r
4177 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
\r
4178 MODIFY_REG(RCC->PLLCFGR, \
\r
4179 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
\r
4180 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \
\r
4181 ((__PLLSOURCE__) | \
\r
4182 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
\r
4183 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
\r
4184 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
\r
4185 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
\r
4186 ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
\r
4188 #elif defined(RCC_PLLP_SUPPORT)
\r
4190 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
\r
4191 MODIFY_REG(RCC->PLLCFGR, \
\r
4192 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
\r
4193 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \
\r
4194 ((__PLLSOURCE__) | \
\r
4195 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
\r
4196 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
\r
4197 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
\r
4198 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
\r
4199 (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))
\r
4203 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \
\r
4204 MODIFY_REG(RCC->PLLCFGR, \
\r
4205 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
\r
4206 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \
\r
4207 ((__PLLSOURCE__) | \
\r
4208 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
\r
4209 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
\r
4210 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
\r
4211 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
\r
4213 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
\r
4215 /** @brief Macro to get the oscillator used as PLL clock source.
\r
4216 * @retval The oscillator used as PLL clock source. The returned value can be one
\r
4217 * of the following:
\r
4218 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
\r
4219 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
\r
4220 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
\r
4221 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
\r
4223 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
\r
4226 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
\r
4227 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
\r
4228 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
\r
4229 * be stopped if used as System Clock.
\r
4230 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
\r
4231 * This parameter can be one or a combination of the following values:
\r
4232 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
\r
4233 * high-quality audio performance on SAI interface in case.
\r
4234 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
\r
4235 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
\r
4236 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
\r
4239 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
\r
4241 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
\r
4244 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
\r
4245 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
\r
4246 * This parameter can be one of the following values:
\r
4247 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
\r
4248 * high-quality audio performance on SAI interface in case.
\r
4249 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
\r
4250 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
\r
4251 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
\r
4252 * @retval SET / RESET
\r
4254 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
\r
4257 * @brief Macro to configure the system clock source.
\r
4258 * @param __SYSCLKSOURCE__ specifies the system clock source.
\r
4259 * This parameter can be one of the following values:
\r
4260 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
\r
4261 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
\r
4262 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
\r
4263 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
\r
4266 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
\r
4267 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
\r
4269 /** @brief Macro to get the clock source used as system clock.
\r
4270 * @retval The clock source used as system clock. The returned value can be one
\r
4271 * of the following:
\r
4272 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
\r
4273 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
\r
4274 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
\r
4275 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
\r
4277 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
\r
4280 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
\r
4281 * @note As the LSE is in the Backup domain and write access is denied to
\r
4282 * this domain after reset, you have to enable write access using
\r
4283 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
4284 * (to be done once after reset).
\r
4285 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
\r
4286 * This parameter can be one of the following values:
\r
4287 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
\r
4288 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
\r
4289 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
\r
4290 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
\r
4293 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
\r
4294 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
\r
4297 * @brief Macro to configure the wake up from stop clock.
\r
4298 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop.
\r
4299 * This parameter can be one of the following values:
\r
4300 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
\r
4301 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
\r
4304 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
\r
4305 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
\r
4308 /** @brief Macro to configure the MCO clock.
\r
4309 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
\r
4310 * This parameter can be one of the following values:
\r
4311 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
\r
4312 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
\r
4313 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
\r
4314 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
\r
4315 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
\r
4316 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
\r
4317 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
\r
4318 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
\r
4320 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
\r
4323 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
\r
4325 * @param __MCODIV__ specifies the MCO clock prescaler.
\r
4326 * This parameter can be one of the following values:
\r
4327 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
\r
4328 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
\r
4329 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
\r
4330 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
\r
4331 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
\r
4333 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
\r
4334 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
\r
4336 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
\r
4337 * @brief macros to manage the specified RCC Flags and interrupts.
\r
4341 /** @brief Enable RCC interrupt(s).
\r
4342 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.
\r
4343 * This parameter can be any combination of the following values:
\r
4344 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
\r
4345 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
\r
4346 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
\r
4347 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
\r
4348 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
\r
4349 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
\r
4350 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
\r
4351 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
\r
4352 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
\r
4354 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4357 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4361 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
\r
4363 /** @brief Disable RCC interrupt(s).
\r
4364 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.
\r
4365 * This parameter can be any combination of the following values:
\r
4366 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
\r
4367 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
\r
4368 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
\r
4369 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
\r
4370 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
\r
4371 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
\r
4372 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
\r
4373 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
\r
4374 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
\r
4376 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4379 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4383 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
\r
4385 /** @brief Clear the RCC's interrupt pending bits.
\r
4386 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
\r
4387 * This parameter can be any combination of the following values:
\r
4388 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
\r
4389 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
\r
4390 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
\r
4391 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
\r
4392 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
\r
4393 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
\r
4394 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
\r
4395 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
\r
4396 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
\r
4397 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
\r
4399 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4402 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4406 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
\r
4408 /** @brief Check whether the RCC interrupt has occurred or not.
\r
4409 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
\r
4410 * This parameter can be one of the following values:
\r
4411 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
\r
4412 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
\r
4413 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
\r
4414 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
\r
4415 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
\r
4416 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
\r
4417 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
\r
4418 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
\r
4419 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
\r
4420 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
\r
4422 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4425 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
\r
4427 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
\r
4429 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
\r
4431 /** @brief Set RMVF bit to clear the reset flags.
\r
4432 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
\r
4433 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
\r
4436 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
\r
4438 /** @brief Check whether the selected RCC flag is set or not.
\r
4439 * @param __FLAG__ specifies the flag to check.
\r
4440 * This parameter can be one of the following values:
\r
4441 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
\r
4442 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
\r
4443 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
\r
4444 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
\r
4445 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1
\r
4446 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
\r
4448 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
\r
4451 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
\r
4453 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
\r
4454 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
\r
4455 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
\r
4456 * @arg @ref RCC_FLAG_BORRST BOR reset
\r
4457 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
\r
4458 * @arg @ref RCC_FLAG_PINRST Pin reset
\r
4459 * @arg @ref RCC_FLAG_FWRST FIREWALL reset
\r
4460 * @arg @ref RCC_FLAG_SFTRST Software reset
\r
4461 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
\r
4462 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
\r
4463 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
\r
4464 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
4466 #if defined(RCC_HSI48_SUPPORT)
\r
4467 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
\r
4468 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
\r
4469 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
4470 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
\r
4471 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
\r
4473 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
\r
4474 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
4475 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
\r
4476 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
\r
4477 #endif /* RCC_HSI48_SUPPORT */
\r
4487 /* Private constants ---------------------------------------------------------*/
\r
4488 /** @defgroup RCC_Private_Constants RCC Private Constants
\r
4491 /* Defines used for Flags */
\r
4492 #define CR_REG_INDEX 1U
\r
4493 #define BDCR_REG_INDEX 2U
\r
4494 #define CSR_REG_INDEX 3U
\r
4495 #if defined(RCC_HSI48_SUPPORT)
\r
4496 #define CRRCR_REG_INDEX 4U
\r
4497 #endif /* RCC_HSI48_SUPPORT */
\r
4499 #define RCC_FLAG_MASK 0x1FU
\r
4504 /* Private macros ------------------------------------------------------------*/
\r
4505 /** @addtogroup RCC_Private_Macros
\r
4509 #if defined(RCC_HSI48_SUPPORT)
\r
4510 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
\r
4511 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
\r
4512 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
\r
4513 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
\r
4514 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
\r
4515 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
\r
4516 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
\r
4518 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
\r
4519 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
\r
4520 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
\r
4521 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
\r
4522 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
\r
4523 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
\r
4524 #endif /* RCC_HSI48_SUPPORT */
\r
4526 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
\r
4527 ((__HSE__) == RCC_HSE_BYPASS))
\r
4529 #if defined(RCC_BDCR_LSESYSDIS)
\r
4530 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \
\r
4531 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))
\r
4533 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
\r
4534 ((__LSE__) == RCC_LSE_BYPASS))
\r
4535 #endif /* RCC_BDCR_LSESYSDIS */
\r
4537 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
\r
4539 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
\r
4541 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
\r
4543 #if defined(RCC_CSR_LSIPREDIV)
\r
4544 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
\r
4545 #endif /* RCC_CSR_LSIPREDIV */
\r
4547 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
\r
4549 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
\r
4551 #if defined(RCC_HSI48_SUPPORT)
\r
4552 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
\r
4553 #endif /* RCC_HSI48_SUPPORT */
\r
4555 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
\r
4556 ((__PLL__) == RCC_PLL_ON))
\r
4558 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
\r
4559 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
\r
4560 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
\r
4561 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
\r
4563 #if defined(RCC_PLLM_DIV_1_16_SUPPORT)
\r
4564 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
\r
4566 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
\r
4567 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */
\r
4569 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
\r
4571 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
\r
4572 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
\r
4574 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
\r
4575 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
\r
4577 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
\r
4578 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
\r
4580 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
\r
4581 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
\r
4583 #if defined(RCC_PLLSAI1_SUPPORT)
\r
4584 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
\r
4585 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
\r
4586 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
\r
4587 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
\r
4588 #endif /* RCC_PLLSAI1_SUPPORT */
\r
4590 #if defined(RCC_PLLSAI2_SUPPORT)
\r
4591 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
\r
4592 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
\r
4593 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
\r
4594 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
\r
4595 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
\r
4596 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
\r
4597 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \
\r
4598 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \
\r
4599 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))
\r
4600 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
\r
4601 #endif /* RCC_PLLSAI2_SUPPORT */
\r
4603 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
\r
4604 ((__RANGE__) == RCC_MSIRANGE_1) || \
\r
4605 ((__RANGE__) == RCC_MSIRANGE_2) || \
\r
4606 ((__RANGE__) == RCC_MSIRANGE_3) || \
\r
4607 ((__RANGE__) == RCC_MSIRANGE_4) || \
\r
4608 ((__RANGE__) == RCC_MSIRANGE_5) || \
\r
4609 ((__RANGE__) == RCC_MSIRANGE_6) || \
\r
4610 ((__RANGE__) == RCC_MSIRANGE_7) || \
\r
4611 ((__RANGE__) == RCC_MSIRANGE_8) || \
\r
4612 ((__RANGE__) == RCC_MSIRANGE_9) || \
\r
4613 ((__RANGE__) == RCC_MSIRANGE_10) || \
\r
4614 ((__RANGE__) == RCC_MSIRANGE_11))
\r
4616 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
\r
4617 ((__RANGE__) == RCC_MSIRANGE_5) || \
\r
4618 ((__RANGE__) == RCC_MSIRANGE_6) || \
\r
4619 ((__RANGE__) == RCC_MSIRANGE_7))
\r
4621 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
\r
4623 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
\r
4624 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
\r
4625 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
\r
4626 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
\r
4628 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
\r
4629 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
\r
4630 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
\r
4631 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
\r
4632 ((__HCLK__) == RCC_SYSCLK_DIV512))
\r
4634 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
\r
4635 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
\r
4636 ((__PCLK__) == RCC_HCLK_DIV16))
\r
4638 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
\r
4639 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
\r
4640 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
\r
4641 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
\r
4643 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
\r
4645 #if defined(RCC_HSI48_SUPPORT)
\r
4646 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
\r
4647 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
\r
4648 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
\r
4649 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
\r
4650 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
\r
4651 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
\r
4652 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
\r
4653 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
\r
4654 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
\r
4656 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
\r
4657 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
\r
4658 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
\r
4659 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
\r
4660 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
\r
4661 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
\r
4662 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
\r
4663 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
\r
4664 #endif /* RCC_HSI48_SUPPORT */
\r
4666 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
\r
4667 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
\r
4668 ((__DIV__) == RCC_MCODIV_16))
\r
4670 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
\r
4671 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
\r
4672 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
\r
4673 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
\r
4675 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
\r
4676 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
\r
4681 /* Include RCC HAL Extended module */
\r
4682 #include "stm32l4xx_hal_rcc_ex.h"
\r
4684 /* Exported functions --------------------------------------------------------*/
\r
4685 /** @addtogroup RCC_Exported_Functions
\r
4690 /** @addtogroup RCC_Exported_Functions_Group1
\r
4694 /* Initialization and de-initialization functions ******************************/
\r
4695 HAL_StatusTypeDef HAL_RCC_DeInit(void);
\r
4696 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
\r
4697 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
\r
4703 /** @addtogroup RCC_Exported_Functions_Group2
\r
4707 /* Peripheral Control functions ************************************************/
\r
4708 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
\r
4709 void HAL_RCC_EnableCSS(void);
\r
4710 uint32_t HAL_RCC_GetSysClockFreq(void);
\r
4711 uint32_t HAL_RCC_GetHCLKFreq(void);
\r
4712 uint32_t HAL_RCC_GetPCLK1Freq(void);
\r
4713 uint32_t HAL_RCC_GetPCLK2Freq(void);
\r
4714 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
\r
4715 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
\r
4716 /* CSS NMI IRQ handler */
\r
4717 void HAL_RCC_NMI_IRQHandler(void);
\r
4718 /* User Callbacks in non blocking mode (IT mode) */
\r
4719 void HAL_RCC_CSSCallback(void);
\r
4737 #ifdef __cplusplus
\r
4741 #endif /* __STM32L4xx_HAL_RCC_H */
\r
4743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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