2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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34 * @brief HET Register Definition
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36 * This structure is used to access the HET module egisters.
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38 /** @typedef hetBASE_t
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39 * @brief HET Register Frame Type Definition
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41 * This type is used to access the HET Registers.
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43 typedef volatile struct hetBase
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45 unsigned GCR; /**< 0x0000: Global control register */
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46 unsigned PFR; /**< 0x0004: Prescale factor register */
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47 unsigned ADDR; /**< 0x0008: Current address register */
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48 unsigned OFF1; /**< 0x000C: Interrupt offset register 1 */
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49 unsigned OFF2; /**< 0x0010: Interrupt offset register 2 */
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50 unsigned INTENAS; /**< 0x0014: Interrupt enable set register */
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51 unsigned INTENAC; /**< 0x0018: Interrupt enable clear register */
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52 unsigned EXC1; /**< 0x001C: Exeption control register 1 */
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53 unsigned EXC2; /**< 0x0020: Exeption control register 2 */
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54 unsigned PRY; /**< 0x0024: Interrupt priority register */
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55 unsigned FLG; /**< 0x0028: Interrupt flag register */
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56 unsigned : 32U; /**< 0x002C: Reserved */
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57 unsigned : 32U; /**< 0x0030: Reserved */
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58 unsigned HRSH; /**< 0x0034: High resoltion share register */
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59 unsigned XOR; /**< 0x0038: XOR share register */
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60 unsigned REQENS; /**< 0x003C: Request enable set register */
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61 unsigned REQENC; /**< 0x0040: Request enable clear register */
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62 unsigned REQDS; /**< 0x0044: Request destination select register */
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63 unsigned : 32U; /**< 0x0048: Reserved */
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64 unsigned DIR; /**< 0x004C: Direction register */
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65 unsigned DIN; /**< 0x0050: Data input register */
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66 unsigned DOUT; /**< 0x0054: Data output register */
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67 unsigned DSET; /**< 0x0058: Data output set register */
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68 unsigned DCLR; /**< 0x005C: Data output clear register */
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69 unsigned PDR; /**< 0x0060: Open drain register */
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70 unsigned PULDIS; /**< 0x0064: Pull disable register */
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71 unsigned PSL; /**< 0x0068: Pull select register */
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72 unsigned : 32U; /**< 0x006C: Reserved */
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73 unsigned : 32U; /**< 0x0070: Reserved */
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74 unsigned PCREG; /**< 0x0074: Parity control register */
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75 unsigned PAR; /**< 0x0078: Parity address register */
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76 unsigned PPR; /**< 0x007C: Parity pin select register */
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77 unsigned SFPRLD; /**< 0x0080: Suppression filter preload register */
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78 unsigned SFENA; /**< 0x0084: Suppression filter enable register */
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79 unsigned : 32U; /**< 0x0088: Reserved */
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80 unsigned LBPSEL; /**< 0x008C: Loop back pair select register */
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81 unsigned LBPDIR; /**< 0x0090: Loop back pair direction register */
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86 * @brief HET Register Frame Pointer
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88 * This pointer is used by the HET driver to access the het module registers.
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90 #define hetREG ((hetBASE_t *)0xFFF7B800U)
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94 * @brief HET GIO Port Register Pointer
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96 * Pointer used by the GIO driver to access I/O PORT of HET
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97 * (use the GIO drivers to access the port pins).
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99 #define hetPORT ((gioPORT_t *)0xFFF7B84CU)
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