2 * FreeRTOS Kernel V10.0.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software. If you wish to use our Amazon
\r
14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
\r
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
23 * http://www.FreeRTOS.org
\r
24 * http://aws.amazon.com/freertos
\r
26 * 1 tab == 4 spaces!
\r
35 * @brief HET Register Definition
\r
37 * This structure is used to access the HET module egisters.
\r
39 /** @typedef hetBASE_t
\r
40 * @brief HET Register Frame Type Definition
\r
42 * This type is used to access the HET Registers.
\r
44 typedef volatile struct hetBase
\r
46 unsigned GCR; /**< 0x0000: Global control register */
\r
47 unsigned PFR; /**< 0x0004: Prescale factor register */
\r
48 unsigned ADDR; /**< 0x0008: Current address register */
\r
49 unsigned OFF1; /**< 0x000C: Interrupt offset register 1 */
\r
50 unsigned OFF2; /**< 0x0010: Interrupt offset register 2 */
\r
51 unsigned INTENAS; /**< 0x0014: Interrupt enable set register */
\r
52 unsigned INTENAC; /**< 0x0018: Interrupt enable clear register */
\r
53 unsigned EXC1; /**< 0x001C: Exeption control register 1 */
\r
54 unsigned EXC2; /**< 0x0020: Exeption control register 2 */
\r
55 unsigned PRY; /**< 0x0024: Interrupt priority register */
\r
56 unsigned FLG; /**< 0x0028: Interrupt flag register */
\r
57 unsigned : 32U; /**< 0x002C: Reserved */
\r
58 unsigned : 32U; /**< 0x0030: Reserved */
\r
59 unsigned HRSH; /**< 0x0034: High resoltion share register */
\r
60 unsigned XOR; /**< 0x0038: XOR share register */
\r
61 unsigned REQENS; /**< 0x003C: Request enable set register */
\r
62 unsigned REQENC; /**< 0x0040: Request enable clear register */
\r
63 unsigned REQDS; /**< 0x0044: Request destination select register */
\r
64 unsigned : 32U; /**< 0x0048: Reserved */
\r
65 unsigned DIR; /**< 0x004C: Direction register */
\r
66 unsigned DIN; /**< 0x0050: Data input register */
\r
67 unsigned DOUT; /**< 0x0054: Data output register */
\r
68 unsigned DSET; /**< 0x0058: Data output set register */
\r
69 unsigned DCLR; /**< 0x005C: Data output clear register */
\r
70 unsigned PDR; /**< 0x0060: Open drain register */
\r
71 unsigned PULDIS; /**< 0x0064: Pull disable register */
\r
72 unsigned PSL; /**< 0x0068: Pull select register */
\r
73 unsigned : 32U; /**< 0x006C: Reserved */
\r
74 unsigned : 32U; /**< 0x0070: Reserved */
\r
75 unsigned PCREG; /**< 0x0074: Parity control register */
\r
76 unsigned PAR; /**< 0x0078: Parity address register */
\r
77 unsigned PPR; /**< 0x007C: Parity pin select register */
\r
78 unsigned SFPRLD; /**< 0x0080: Suppression filter preload register */
\r
79 unsigned SFENA; /**< 0x0084: Suppression filter enable register */
\r
80 unsigned : 32U; /**< 0x0088: Reserved */
\r
81 unsigned LBPSEL; /**< 0x008C: Loop back pair select register */
\r
82 unsigned LBPDIR; /**< 0x0090: Loop back pair direction register */
\r
87 * @brief HET Register Frame Pointer
\r
89 * This pointer is used by the HET driver to access the het module registers.
\r
91 #define hetREG ((hetBASE_t *)0xFFF7B800U)
\r
95 * @brief HET GIO Port Register Pointer
\r
97 * Pointer used by the GIO driver to access I/O PORT of HET
\r
98 * (use the GIO drivers to access the port pins).
\r
100 #define hetPORT ((gioPORT_t *)0xFFF7B84CU)
\r