git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/reg_test.asm

   1 ;/*\r
   2 ;    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
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  66 \r
  67 ;-------------------------------------------------\r
  68 ;\r
  69                 .def    vRegTestTask1\r
  70                 .ref    ulRegTest1Counter\r
  71 \r
  72                 .if (__TI_VFP_SUPPORT__)\r
  73                         .ref vPortTaskUsesFPU\r
  74                 .endif ;__TI_VFP_SUPPORT__\r
  75 \r
  76                 .text\r
  77                 .arm\r
  78 \r
  79 vRegTestTask1:\r
  80         .if (__TI_VFP_SUPPORT__)\r
  81                 ; Let the port layer know that this task needs its FPU context saving.\r
  82                 BL              vPortTaskUsesFPU\r
  83         .endif\r
  84 \r
  85                 ; Fill each general purpose register with a known value.\r
  86                 mov             r0,  #0xFF\r
  87                 mov             r1,  #0x11\r
  88                 mov             r2,  #0x22\r
  89                 mov             r3,  #0x33\r
  90                 mov     r4,  #0x44              \r
  91                 mov     r5,  #0x55\r
  92                 mov     r6,  #0x66\r
  93                 mov     r7,  #0x77\r
  94                 mov     r8,  #0x88\r
  95                 mov     r9,  #0x99\r
  96                 mov     r10, #0xAA\r
  97                 mov     r11, #0xBB\r
  98                 mov     r12, #0xCC\r
  99                 mov             r14, #0xEE\r
 100 \r
 101         .if (__TI_VFP_SUPPORT__)\r
 102                 ; Fill each FPU register with a known value.\r
 103                 vmov    d0, r0, r1\r
 104                 vmov    d1, r2, r3\r
 105                 vmov    d2, r4, r5\r
 106                 vmov    d3, r6, r7\r
 107                 vmov    d4, r8, r9\r
 108                 vmov    d5, r10, r11\r
 109                 vmov    d6, r0, r1\r
 110                 vmov    d7, r2, r3\r
 111                 vmov    d8, r4, r5\r
 112                 vmov    d9, r6, r7\r
 113                 vmov    d10, r8, r9\r
 114                 vmov    d11, r10, r11\r
 115                 vmov    d12, r0, r1\r
 116                 vmov    d13, r2, r3\r
 117                 vmov    d14, r4, r5\r
 118                 vmov    d15, r6, r7\r
 119         .endif\r
 120 \r
 121         \r
 122 vRegTestLoop1:\r
 123 \r
 124                 ; Force yeild\r
 125                 swi             #0\r
 126 \r
 127         .if (__TI_VFP_SUPPORT__)\r
 128                 ; Check all the VFP registers still contain the values set above.\r
 129                 ; First save registers that are clobbered by the test.\r
 130                 push { r0-r1 }\r
 131 \r
 132                 vmov    r0, r1, d0\r
 133                 cmp     r0, #0xFF\r
 134                 bne     reg1_error_loopf\r
 135                 cmp     r1, #0x11\r
 136                 bne     reg1_error_loopf\r
 137                 vmov    r0, r1, d1\r
 138                 cmp     r0, #0x22\r
 139                 bne     reg1_error_loopf\r
 140                 cmp     r1, #0x33\r
 141                 bne     reg1_error_loopf\r
 142                 vmov    r0, r1, d2\r
 143                 cmp     r0, #0x44\r
 144                 bne     reg1_error_loopf\r
 145                 cmp     r1, #0x55\r
 146                 bne     reg1_error_loopf\r
 147                 vmov    r0, r1, d3\r
 148                 cmp     r0, #0x66\r
 149                 bne     reg1_error_loopf\r
 150                 cmp     r1, #0x77\r
 151                 bne     reg1_error_loopf\r
 152                 vmov    r0, r1, d4\r
 153                 cmp     r0, #0x88\r
 154                 bne     reg1_error_loopf\r
 155                 cmp     r1, #0x99\r
 156                 bne     reg1_error_loopf\r
 157                 vmov    r0, r1, d5\r
 158                 cmp     r0, #0xAA\r
 159                 bne     reg1_error_loopf\r
 160                 cmp     r1, #0xBB\r
 161                 bne     reg1_error_loopf\r
 162                 vmov    r0, r1, d6\r
 163                 cmp     r0, #0xFF\r
 164                 bne     reg1_error_loopf\r
 165                 cmp     r1, #0x11\r
 166                 bne     reg1_error_loopf\r
 167                 vmov    r0, r1, d7\r
 168                 cmp     r0, #0x22\r
 169                 bne     reg1_error_loopf\r
 170                 cmp     r1, #0x33\r
 171                 bne     reg1_error_loopf\r
 172                 vmov    r0, r1, d8\r
 173                 cmp     r0, #0x44\r
 174                 bne     reg1_error_loopf\r
 175                 cmp     r1, #0x55\r
 176                 bne     reg1_error_loopf\r
 177                 vmov    r0, r1, d9\r
 178                 cmp     r0, #0x66\r
 179                 bne     reg1_error_loopf\r
 180                 cmp     r1, #0x77\r
 181                 bne     reg1_error_loopf\r
 182                 vmov    r0, r1, d10\r
 183                 cmp     r0, #0x88\r
 184                 bne     reg1_error_loopf\r
 185                 cmp     r1, #0x99\r
 186                 bne     reg1_error_loopf\r
 187                 vmov    r0, r1, d11\r
 188                 cmp     r0, #0xAA\r
 189                 bne     reg1_error_loopf\r
 190                 cmp     r1, #0xBB\r
 191                 bne     reg1_error_loopf\r
 192                 vmov    r0, r1, d12\r
 193                 cmp     r0, #0xFF\r
 194                 bne     reg1_error_loopf\r
 195                 cmp     r1, #0x11\r
 196                 bne     reg1_error_loopf\r
 197                 vmov    r0, r1, d13\r
 198                 cmp     r0, #0x22\r
 199                 bne     reg1_error_loopf\r
 200                 cmp     r1, #0x33\r
 201                 bne     reg1_error_loopf\r
 202                 vmov    r0, r1, d14\r
 203                 cmp     r0, #0x44\r
 204                 bne     reg1_error_loopf\r
 205                 cmp     r1, #0x55\r
 206                 bne     reg1_error_loopf\r
 207                 vmov    r0, r1, d15\r
 208                 cmp     r0, #0x66\r
 209                 bne     reg1_error_loopf\r
 210                 cmp     r1, #0x77\r
 211                 bne     reg1_error_loopf\r
 212 \r
 213                 ; Restore the registers that were clobbered by the test.\r
 214                 pop     {r0-r1}\r
 215 \r
 216                 ; VFP register test passed.  Jump to the core register test.\r
 217                 b               reg1_loopf_pass\r
 218 \r
 219 reg1_error_loopf:\r
 220                 ; If this line is hit then a VFP register value was found to be\r
 221                 ; incorrect.\r
 222                 b reg1_error_loopf\r
 223 \r
 224 reg1_loopf_pass:\r
 225 \r
 226         .endif ;__TI_VFP_SUPPORT__\r
 227 \r
 228                 ; Test each general purpose register to check that it still contains the\r
 229                 ; expected known value, jumping to vRegTestError1 if any register contains\r
 230                 ; an unexpected value.\r
 231                 cmp             r0, #0xFF\r
 232                 bne             vRegTestError1          \r
 233                 cmp             r1, #0x11\r
 234                 bne             vRegTestError1          \r
 235                 cmp             r2, #0x22\r
 236                 bne             vRegTestError1          \r
 237                 cmp             r3, #0x33\r
 238                 bne             vRegTestError1          \r
 239                 cmp             r4, #0x44\r
 240                 bne             vRegTestError1          \r
 241                 cmp             r5, #0x55\r
 242                 bne             vRegTestError1          \r
 243                 cmp             r6, #0x66\r
 244                 bne             vRegTestError1          \r
 245                 cmp             r7, #0x77\r
 246                 bne             vRegTestError1          \r
 247                 cmp             r8, #0x88\r
 248                 bne             vRegTestError1          \r
 249                 cmp             r9, #0x99\r
 250                 bne             vRegTestError1          \r
 251                 cmp             r10, #0xAA\r
 252                 bne             vRegTestError1          \r
 253                 cmp             r11, #0xBB\r
 254                 bne             vRegTestError1          \r
 255                 cmp             r12, #0xCC\r
 256                 bne             vRegTestError1          \r
 257                 cmp             r14, #0xEE\r
 258                 bne             vRegTestError1          \r
 259         \r
 260                 ; This task is still running without jumping to vRegTestError1, so increment\r
 261                 ; the loop counter so the check task knows the task is running error free.\r
 262                 stmfd   sp!, { r0-r1 }\r
 263                 ldr             r0, Count1Const\r
 264                 ldr             r1, [r0]\r
 265                 add             r1, r1, #1\r
 266                 str     r1, [r0]\r
 267                 ldmfd   sp!, { r0-r1 }\r
 268                 \r
 269                 ; Loop again, performing the same tests.\r
 270                 b               vRegTestLoop1\r
 271 \r
 272 Count1Const     .word   ulRegTest1Counter\r
 273         \r
 274 vRegTestError1:\r
 275                 b       vRegTestError1\r
 276 \r
 277 \r
 278 ;-------------------------------------------------\r
 279 ;\r
 280                 .def    vRegTestTask2\r
 281                 .ref    ulRegTest2Counter\r
 282                 .text\r
 283                 .arm\r
 284 ;\r
 285 vRegTestTask2:\r
 286         .if (__TI_VFP_SUPPORT__)\r
 287                 ; Let the port layer know that this task needs its FPU context saving.\r
 288                 BL              vPortTaskUsesFPU\r
 289         .endif\r
 290 \r
 291                 ; Fill each general purpose register with a known value.\r
 292                 mov             r0,  #0xFF000000\r
 293                 mov             r1,  #0x11000000\r
 294                 mov             r2,  #0x22000000\r
 295                 mov             r3,  #0x33000000\r
 296                 mov     r4,  #0x44000000                \r
 297                 mov     r5,  #0x55000000\r
 298                 mov     r6,  #0x66000000\r
 299                 mov     r7,  #0x77000000\r
 300                 mov     r8,  #0x88000000\r
 301                 mov     r9,  #0x99000000\r
 302                 mov     r10, #0xAA000000\r
 303                 mov     r11, #0xBB000000\r
 304                 mov     r12, #0xCC000000\r
 305                 mov     r14, #0xEE000000\r
 306         \r
 307         .if (__TI_VFP_SUPPORT__)\r
 308 \r
 309                 ; Fill each FPU register with a known value.\r
 310                 vmov    d0, r0, r1\r
 311                 vmov    d1, r2, r3\r
 312                 vmov    d2, r4, r5\r
 313                 vmov    d3, r6, r7\r
 314                 vmov    d4, r8, r9\r
 315                 vmov    d5, r10, r11\r
 316                 vmov    d6, r0, r1\r
 317                 vmov    d7, r2, r3\r
 318                 vmov    d8, r4, r5\r
 319                 vmov    d9, r6, r7\r
 320                 vmov    d10, r8, r9\r
 321                 vmov    d11, r10, r11\r
 322                 vmov    d12, r0, r1\r
 323                 vmov    d13, r2, r3\r
 324                 vmov    d14, r4, r5\r
 325                 vmov    d15, r6, r7\r
 326         .endif\r
 327 \r
 328 vRegTestLoop2:\r
 329 \r
 330         .if (__TI_VFP_SUPPORT__)\r
 331                 ; Check all the VFP registers still contain the values set above.\r
 332                 ; First save registers that are clobbered by the test.\r
 333                 push { r0-r1 }\r
 334 \r
 335                 vmov r0, r1, d0\r
 336                 cmp r0, #0xFF000000\r
 337                 bne reg2_error_loopf\r
 338                 cmp r1, #0x11000000\r
 339                 bne reg2_error_loopf\r
 340                 vmov r0, r1, d1\r
 341                 cmp r0, #0x22000000\r
 342                 bne reg2_error_loopf\r
 343                 cmp r1, #0x33000000\r
 344                 bne reg2_error_loopf\r
 345                 vmov r0, r1, d2\r
 346                 cmp r0, #0x44000000\r
 347                 bne reg2_error_loopf\r
 348                 cmp r1, #0x55000000\r
 349                 bne reg2_error_loopf\r
 350                 vmov r0, r1, d3\r
 351                 cmp r0, #0x66000000\r
 352                 bne reg2_error_loopf\r
 353                 cmp r1, #0x77000000\r
 354                 bne reg2_error_loopf\r
 355                 vmov r0, r1, d4\r
 356                 cmp r0, #0x88000000\r
 357                 bne reg2_error_loopf\r
 358                 cmp r1, #0x99000000\r
 359                 bne reg2_error_loopf\r
 360                 vmov r0, r1, d5\r
 361                 cmp r0, #0xAA000000\r
 362                 bne reg2_error_loopf\r
 363                 cmp r1, #0xBB000000\r
 364                 bne reg2_error_loopf\r
 365                 vmov r0, r1, d6\r
 366                 cmp r0, #0xFF000000\r
 367                 bne reg2_error_loopf\r
 368                 cmp r1, #0x11000000\r
 369                 bne reg2_error_loopf\r
 370                 vmov r0, r1, d7\r
 371                 cmp r0, #0x22000000\r
 372                 bne reg2_error_loopf\r
 373                 cmp r1, #0x33000000\r
 374                 bne reg2_error_loopf\r
 375                 vmov r0, r1, d8\r
 376                 cmp r0, #0x44000000\r
 377                 bne reg2_error_loopf\r
 378                 cmp r1, #0x55000000\r
 379                 bne reg2_error_loopf\r
 380                 vmov r0, r1, d9\r
 381                 cmp r0, #0x66000000\r
 382                 bne reg2_error_loopf\r
 383                 cmp r1, #0x77000000\r
 384                 bne reg2_error_loopf\r
 385                 vmov r0, r1, d10\r
 386                 cmp r0, #0x88000000\r
 387                 bne reg2_error_loopf\r
 388                 cmp r1, #0x99000000\r
 389                 bne reg2_error_loopf\r
 390                 vmov r0, r1, d11\r
 391                 cmp r0, #0xAA000000\r
 392                 bne reg2_error_loopf\r
 393                 cmp r1, #0xBB000000\r
 394                 bne reg2_error_loopf\r
 395                 vmov r0, r1, d12\r
 396                 cmp r0, #0xFF000000\r
 397                 bne reg2_error_loopf\r
 398                 cmp r1, #0x11000000\r
 399                 bne reg2_error_loopf\r
 400                 vmov r0, r1, d13\r
 401                 cmp r0, #0x22000000\r
 402                 bne reg2_error_loopf\r
 403                 cmp r1, #0x33000000\r
 404                 bne reg2_error_loopf\r
 405                 vmov r0, r1, d14\r
 406                 cmp r0, #0x44000000\r
 407                 bne reg2_error_loopf\r
 408                 cmp r1, #0x55000000\r
 409                 bne reg2_error_loopf\r
 410                 vmov r0, r1, d15\r
 411                 cmp r0, #0x66000000\r
 412                 bne reg2_error_loopf\r
 413                 cmp r1, #0x77000000\r
 414                 bne reg2_error_loopf\r
 415 \r
 416                 ; Restore the registers that were clobbered by the test.\r
 417                 pop {r0-r1}\r
 418 \r
 419                 ; VFP register test passed.  Jump to the core register test.\r
 420                 b reg2_loopf_pass\r
 421 \r
 422 reg2_error_loopf:\r
 423                 ; If this line is hit then a VFP register value was found to be\r
 424                 ; incorrect.\r
 425                 b       reg2_error_loopf\r
 426 \r
 427 reg2_loopf_pass:\r
 428 \r
 429         .endif ;__TI_VFP_SUPPORT__\r
 430 \r
 431                 ; Test each general purpose register to check that it still contains the\r
 432                 ; expected known value, jumping to vRegTestError2 if any register contains\r
 433                 ; an unexpected value.\r
 434                 cmp             r0, #0xFF000000\r
 435                 bne             vRegTestError2          \r
 436                 cmp             r1, #0x11000000\r
 437                 bne             vRegTestError2  \r
 438                 cmp             r2, #0x22000000\r
 439                 bne             vRegTestError2  \r
 440                 cmp             r3, #0x33000000\r
 441                 bne             vRegTestError2  \r
 442                 cmp             r4, #0x44000000\r
 443                 bne             vRegTestError2  \r
 444                 cmp             r5, #0x55000000\r
 445                 bne             vRegTestError2  \r
 446                 cmp             r6, #0x66000000\r
 447                 bne             vRegTestError2  \r
 448                 cmp             r7, #0x77000000\r
 449                 bne             vRegTestError2  \r
 450                 cmp             r8, #0x88000000\r
 451                 bne             vRegTestError2  \r
 452                 cmp             r9, #0x99000000\r
 453                 bne             vRegTestError2  \r
 454                 cmp             r10, #0xAA000000\r
 455                 bne             vRegTestError2  \r
 456                 cmp             r11, #0xBB000000\r
 457                 bne             vRegTestError2  \r
 458                 cmp             r12, #0xCC000000\r
 459                 bne             vRegTestError2  \r
 460                 cmp     r14, #0xEE000000\r
 461                 bne             vRegTestError2  \r
 462         \r
 463                 ; This task is still running without jumping to vRegTestError2, so increment\r
 464                 ; the loop counter so the check task knows the task is running error free.\r
 465                 stmfd   sp!, { r0-r1 }\r
 466                 ldr             r0, Count2Const\r
 467                 ldr             r1, [r0]\r
 468                 add             r1, r1, #1\r
 469                 str     r1, [r0]\r
 470                 ldmfd   sp!, { r0-r1 }\r
 471                 \r
 472                 ; Loop again, performing the same tests.\r
 473                 b               vRegTestLoop2\r
 474 \r
 475 Count2Const     .word   ulRegTest2Counter\r
 476         \r
 477 vRegTestError2:\r
 478                 b       vRegTestError2\r
 479 \r
 480 ;-------------------------------------------------\r
 481         \r
 482         \r
 483         \r