git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/reg_test.asm

   1 ;/*\r
   2 ; * FreeRTOS Kernel V10.3.0\r
   3 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4 ; *\r
   5 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6 ; * this software and associated documentation files (the "Software"), to deal in\r
   7 ; * the Software without restriction, including without limitation the rights to\r
   8 ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9 ; * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10 ; * subject to the following conditions:\r
  11 ; *\r
  12 ; * The above copyright notice and this permission notice shall be included in all\r
  13 ; * copies or substantial portions of the Software.\r
  14 ; *\r
  15 ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16 ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17 ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18 ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19 ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20 ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21 ; *\r
  22 ; * http://www.FreeRTOS.org\r
  23 ; * http://aws.amazon.com/freertos\r
  24 ; *\r
  25 ; * 1 tab == 4 spaces!\r
  26 ; */\r
  27 \r
  28 ;-------------------------------------------------\r
  29 ;\r
  30                 .def    vRegTestTask1\r
  31                 .ref    ulRegTest1Counter\r
  32 \r
  33                 .if (__TI_VFP_SUPPORT__)\r
  34                         .ref vPortTaskUsesFPU\r
  35                 .endif ;__TI_VFP_SUPPORT__\r
  36 \r
  37                 .text\r
  38                 .arm\r
  39 \r
  40 vRegTestTask1:\r
  41         .if (__TI_VFP_SUPPORT__)\r
  42                 ; Let the port layer know that this task needs its FPU context saving.\r
  43                 BL              vPortTaskUsesFPU\r
  44         .endif\r
  45 \r
  46                 ; Fill each general purpose register with a known value.\r
  47                 mov             r0,  #0xFF\r
  48                 mov             r1,  #0x11\r
  49                 mov             r2,  #0x22\r
  50                 mov             r3,  #0x33\r
  51                 mov     r4,  #0x44\r
  52                 mov     r5,  #0x55\r
  53                 mov     r6,  #0x66\r
  54                 mov     r7,  #0x77\r
  55                 mov     r8,  #0x88\r
  56                 mov     r9,  #0x99\r
  57                 mov     r10, #0xAA\r
  58                 mov     r11, #0xBB\r
  59                 mov     r12, #0xCC\r
  60                 mov             r14, #0xEE\r
  61 \r
  62         .if (__TI_VFP_SUPPORT__)\r
  63                 ; Fill each FPU register with a known value.\r
  64                 vmov    d0, r0, r1\r
  65                 vmov    d1, r2, r3\r
  66                 vmov    d2, r4, r5\r
  67                 vmov    d3, r6, r7\r
  68                 vmov    d4, r8, r9\r
  69                 vmov    d5, r10, r11\r
  70                 vmov    d6, r0, r1\r
  71                 vmov    d7, r2, r3\r
  72                 vmov    d8, r4, r5\r
  73                 vmov    d9, r6, r7\r
  74                 vmov    d10, r8, r9\r
  75                 vmov    d11, r10, r11\r
  76                 vmov    d12, r0, r1\r
  77                 vmov    d13, r2, r3\r
  78                 vmov    d14, r4, r5\r
  79                 vmov    d15, r6, r7\r
  80         .endif\r
  81 \r
  82 \r
  83 vRegTestLoop1:\r
  84 \r
  85                 ; Force yeild\r
  86                 swi             #0\r
  87 \r
  88         .if (__TI_VFP_SUPPORT__)\r
  89                 ; Check all the VFP registers still contain the values set above.\r
  90                 ; First save registers that are clobbered by the test.\r
  91                 push { r0-r1 }\r
  92 \r
  93                 vmov    r0, r1, d0\r
  94                 cmp     r0, #0xFF\r
  95                 bne     reg1_error_loopf\r
  96                 cmp     r1, #0x11\r
  97                 bne     reg1_error_loopf\r
  98                 vmov    r0, r1, d1\r
  99                 cmp     r0, #0x22\r
 100                 bne     reg1_error_loopf\r
 101                 cmp     r1, #0x33\r
 102                 bne     reg1_error_loopf\r
 103                 vmov    r0, r1, d2\r
 104                 cmp     r0, #0x44\r
 105                 bne     reg1_error_loopf\r
 106                 cmp     r1, #0x55\r
 107                 bne     reg1_error_loopf\r
 108                 vmov    r0, r1, d3\r
 109                 cmp     r0, #0x66\r
 110                 bne     reg1_error_loopf\r
 111                 cmp     r1, #0x77\r
 112                 bne     reg1_error_loopf\r
 113                 vmov    r0, r1, d4\r
 114                 cmp     r0, #0x88\r
 115                 bne     reg1_error_loopf\r
 116                 cmp     r1, #0x99\r
 117                 bne     reg1_error_loopf\r
 118                 vmov    r0, r1, d5\r
 119                 cmp     r0, #0xAA\r
 120                 bne     reg1_error_loopf\r
 121                 cmp     r1, #0xBB\r
 122                 bne     reg1_error_loopf\r
 123                 vmov    r0, r1, d6\r
 124                 cmp     r0, #0xFF\r
 125                 bne     reg1_error_loopf\r
 126                 cmp     r1, #0x11\r
 127                 bne     reg1_error_loopf\r
 128                 vmov    r0, r1, d7\r
 129                 cmp     r0, #0x22\r
 130                 bne     reg1_error_loopf\r
 131                 cmp     r1, #0x33\r
 132                 bne     reg1_error_loopf\r
 133                 vmov    r0, r1, d8\r
 134                 cmp     r0, #0x44\r
 135                 bne     reg1_error_loopf\r
 136                 cmp     r1, #0x55\r
 137                 bne     reg1_error_loopf\r
 138                 vmov    r0, r1, d9\r
 139                 cmp     r0, #0x66\r
 140                 bne     reg1_error_loopf\r
 141                 cmp     r1, #0x77\r
 142                 bne     reg1_error_loopf\r
 143                 vmov    r0, r1, d10\r
 144                 cmp     r0, #0x88\r
 145                 bne     reg1_error_loopf\r
 146                 cmp     r1, #0x99\r
 147                 bne     reg1_error_loopf\r
 148                 vmov    r0, r1, d11\r
 149                 cmp     r0, #0xAA\r
 150                 bne     reg1_error_loopf\r
 151                 cmp     r1, #0xBB\r
 152                 bne     reg1_error_loopf\r
 153                 vmov    r0, r1, d12\r
 154                 cmp     r0, #0xFF\r
 155                 bne     reg1_error_loopf\r
 156                 cmp     r1, #0x11\r
 157                 bne     reg1_error_loopf\r
 158                 vmov    r0, r1, d13\r
 159                 cmp     r0, #0x22\r
 160                 bne     reg1_error_loopf\r
 161                 cmp     r1, #0x33\r
 162                 bne     reg1_error_loopf\r
 163                 vmov    r0, r1, d14\r
 164                 cmp     r0, #0x44\r
 165                 bne     reg1_error_loopf\r
 166                 cmp     r1, #0x55\r
 167                 bne     reg1_error_loopf\r
 168                 vmov    r0, r1, d15\r
 169                 cmp     r0, #0x66\r
 170                 bne     reg1_error_loopf\r
 171                 cmp     r1, #0x77\r
 172                 bne     reg1_error_loopf\r
 173 \r
 174                 ; Restore the registers that were clobbered by the test.\r
 175                 pop     {r0-r1}\r
 176 \r
 177                 ; VFP register test passed.  Jump to the core register test.\r
 178                 b               reg1_loopf_pass\r
 179 \r
 180 reg1_error_loopf:\r
 181                 ; If this line is hit then a VFP register value was found to be\r
 182                 ; incorrect.\r
 183                 b reg1_error_loopf\r
 184 \r
 185 reg1_loopf_pass:\r
 186 \r
 187         .endif ;__TI_VFP_SUPPORT__\r
 188 \r
 189                 ; Test each general purpose register to check that it still contains the\r
 190                 ; expected known value, jumping to vRegTestError1 if any register contains\r
 191                 ; an unexpected value.\r
 192                 cmp             r0, #0xFF\r
 193                 bne             vRegTestError1\r
 194                 cmp             r1, #0x11\r
 195                 bne             vRegTestError1\r
 196                 cmp             r2, #0x22\r
 197                 bne             vRegTestError1\r
 198                 cmp             r3, #0x33\r
 199                 bne             vRegTestError1\r
 200                 cmp             r4, #0x44\r
 201                 bne             vRegTestError1\r
 202                 cmp             r5, #0x55\r
 203                 bne             vRegTestError1\r
 204                 cmp             r6, #0x66\r
 205                 bne             vRegTestError1\r
 206                 cmp             r7, #0x77\r
 207                 bne             vRegTestError1\r
 208                 cmp             r8, #0x88\r
 209                 bne             vRegTestError1\r
 210                 cmp             r9, #0x99\r
 211                 bne             vRegTestError1\r
 212                 cmp             r10, #0xAA\r
 213                 bne             vRegTestError1\r
 214                 cmp             r11, #0xBB\r
 215                 bne             vRegTestError1\r
 216                 cmp             r12, #0xCC\r
 217                 bne             vRegTestError1\r
 218                 cmp             r14, #0xEE\r
 219                 bne             vRegTestError1\r
 220 \r
 221                 ; This task is still running without jumping to vRegTestError1, so increment\r
 222                 ; the loop counter so the check task knows the task is running error free.\r
 223                 stmfd   sp!, { r0-r1 }\r
 224                 ldr             r0, Count1Const\r
 225                 ldr             r1, [r0]\r
 226                 add             r1, r1, #1\r
 227                 str     r1, [r0]\r
 228                 ldmfd   sp!, { r0-r1 }\r
 229 \r
 230                 ; Loop again, performing the same tests.\r
 231                 b               vRegTestLoop1\r
 232 \r
 233 Count1Const     .word   ulRegTest1Counter\r
 234 \r
 235 vRegTestError1:\r
 236                 b       vRegTestError1\r
 237 \r
 238 \r
 239 ;-------------------------------------------------\r
 240 ;\r
 241                 .def    vRegTestTask2\r
 242                 .ref    ulRegTest2Counter\r
 243                 .text\r
 244                 .arm\r
 245 ;\r
 246 vRegTestTask2:\r
 247         .if (__TI_VFP_SUPPORT__)\r
 248                 ; Let the port layer know that this task needs its FPU context saving.\r
 249                 BL              vPortTaskUsesFPU\r
 250         .endif\r
 251 \r
 252                 ; Fill each general purpose register with a known value.\r
 253                 mov             r0,  #0xFF000000\r
 254                 mov             r1,  #0x11000000\r
 255                 mov             r2,  #0x22000000\r
 256                 mov             r3,  #0x33000000\r
 257                 mov     r4,  #0x44000000\r
 258                 mov     r5,  #0x55000000\r
 259                 mov     r6,  #0x66000000\r
 260                 mov     r7,  #0x77000000\r
 261                 mov     r8,  #0x88000000\r
 262                 mov     r9,  #0x99000000\r
 263                 mov     r10, #0xAA000000\r
 264                 mov     r11, #0xBB000000\r
 265                 mov     r12, #0xCC000000\r
 266                 mov     r14, #0xEE000000\r
 267 \r
 268         .if (__TI_VFP_SUPPORT__)\r
 269 \r
 270                 ; Fill each FPU register with a known value.\r
 271                 vmov    d0, r0, r1\r
 272                 vmov    d1, r2, r3\r
 273                 vmov    d2, r4, r5\r
 274                 vmov    d3, r6, r7\r
 275                 vmov    d4, r8, r9\r
 276                 vmov    d5, r10, r11\r
 277                 vmov    d6, r0, r1\r
 278                 vmov    d7, r2, r3\r
 279                 vmov    d8, r4, r5\r
 280                 vmov    d9, r6, r7\r
 281                 vmov    d10, r8, r9\r
 282                 vmov    d11, r10, r11\r
 283                 vmov    d12, r0, r1\r
 284                 vmov    d13, r2, r3\r
 285                 vmov    d14, r4, r5\r
 286                 vmov    d15, r6, r7\r
 287         .endif\r
 288 \r
 289 vRegTestLoop2:\r
 290 \r
 291         .if (__TI_VFP_SUPPORT__)\r
 292                 ; Check all the VFP registers still contain the values set above.\r
 293                 ; First save registers that are clobbered by the test.\r
 294                 push { r0-r1 }\r
 295 \r
 296                 vmov r0, r1, d0\r
 297                 cmp r0, #0xFF000000\r
 298                 bne reg2_error_loopf\r
 299                 cmp r1, #0x11000000\r
 300                 bne reg2_error_loopf\r
 301                 vmov r0, r1, d1\r
 302                 cmp r0, #0x22000000\r
 303                 bne reg2_error_loopf\r
 304                 cmp r1, #0x33000000\r
 305                 bne reg2_error_loopf\r
 306                 vmov r0, r1, d2\r
 307                 cmp r0, #0x44000000\r
 308                 bne reg2_error_loopf\r
 309                 cmp r1, #0x55000000\r
 310                 bne reg2_error_loopf\r
 311                 vmov r0, r1, d3\r
 312                 cmp r0, #0x66000000\r
 313                 bne reg2_error_loopf\r
 314                 cmp r1, #0x77000000\r
 315                 bne reg2_error_loopf\r
 316                 vmov r0, r1, d4\r
 317                 cmp r0, #0x88000000\r
 318                 bne reg2_error_loopf\r
 319                 cmp r1, #0x99000000\r
 320                 bne reg2_error_loopf\r
 321                 vmov r0, r1, d5\r
 322                 cmp r0, #0xAA000000\r
 323                 bne reg2_error_loopf\r
 324                 cmp r1, #0xBB000000\r
 325                 bne reg2_error_loopf\r
 326                 vmov r0, r1, d6\r
 327                 cmp r0, #0xFF000000\r
 328                 bne reg2_error_loopf\r
 329                 cmp r1, #0x11000000\r
 330                 bne reg2_error_loopf\r
 331                 vmov r0, r1, d7\r
 332                 cmp r0, #0x22000000\r
 333                 bne reg2_error_loopf\r
 334                 cmp r1, #0x33000000\r
 335                 bne reg2_error_loopf\r
 336                 vmov r0, r1, d8\r
 337                 cmp r0, #0x44000000\r
 338                 bne reg2_error_loopf\r
 339                 cmp r1, #0x55000000\r
 340                 bne reg2_error_loopf\r
 341                 vmov r0, r1, d9\r
 342                 cmp r0, #0x66000000\r
 343                 bne reg2_error_loopf\r
 344                 cmp r1, #0x77000000\r
 345                 bne reg2_error_loopf\r
 346                 vmov r0, r1, d10\r
 347                 cmp r0, #0x88000000\r
 348                 bne reg2_error_loopf\r
 349                 cmp r1, #0x99000000\r
 350                 bne reg2_error_loopf\r
 351                 vmov r0, r1, d11\r
 352                 cmp r0, #0xAA000000\r
 353                 bne reg2_error_loopf\r
 354                 cmp r1, #0xBB000000\r
 355                 bne reg2_error_loopf\r
 356                 vmov r0, r1, d12\r
 357                 cmp r0, #0xFF000000\r
 358                 bne reg2_error_loopf\r
 359                 cmp r1, #0x11000000\r
 360                 bne reg2_error_loopf\r
 361                 vmov r0, r1, d13\r
 362                 cmp r0, #0x22000000\r
 363                 bne reg2_error_loopf\r
 364                 cmp r1, #0x33000000\r
 365                 bne reg2_error_loopf\r
 366                 vmov r0, r1, d14\r
 367                 cmp r0, #0x44000000\r
 368                 bne reg2_error_loopf\r
 369                 cmp r1, #0x55000000\r
 370                 bne reg2_error_loopf\r
 371                 vmov r0, r1, d15\r
 372                 cmp r0, #0x66000000\r
 373                 bne reg2_error_loopf\r
 374                 cmp r1, #0x77000000\r
 375                 bne reg2_error_loopf\r
 376 \r
 377                 ; Restore the registers that were clobbered by the test.\r
 378                 pop {r0-r1}\r
 379 \r
 380                 ; VFP register test passed.  Jump to the core register test.\r
 381                 b reg2_loopf_pass\r
 382 \r
 383 reg2_error_loopf:\r
 384                 ; If this line is hit then a VFP register value was found to be\r
 385                 ; incorrect.\r
 386                 b       reg2_error_loopf\r
 387 \r
 388 reg2_loopf_pass:\r
 389 \r
 390         .endif ;__TI_VFP_SUPPORT__\r
 391 \r
 392                 ; Test each general purpose register to check that it still contains the\r
 393                 ; expected known value, jumping to vRegTestError2 if any register contains\r
 394                 ; an unexpected value.\r
 395                 cmp             r0, #0xFF000000\r
 396                 bne             vRegTestError2\r
 397                 cmp             r1, #0x11000000\r
 398                 bne             vRegTestError2\r
 399                 cmp             r2, #0x22000000\r
 400                 bne             vRegTestError2\r
 401                 cmp             r3, #0x33000000\r
 402                 bne             vRegTestError2\r
 403                 cmp             r4, #0x44000000\r
 404                 bne             vRegTestError2\r
 405                 cmp             r5, #0x55000000\r
 406                 bne             vRegTestError2\r
 407                 cmp             r6, #0x66000000\r
 408                 bne             vRegTestError2\r
 409                 cmp             r7, #0x77000000\r
 410                 bne             vRegTestError2\r
 411                 cmp             r8, #0x88000000\r
 412                 bne             vRegTestError2\r
 413                 cmp             r9, #0x99000000\r
 414                 bne             vRegTestError2\r
 415                 cmp             r10, #0xAA000000\r
 416                 bne             vRegTestError2\r
 417                 cmp             r11, #0xBB000000\r
 418                 bne             vRegTestError2\r
 419                 cmp             r12, #0xCC000000\r
 420                 bne             vRegTestError2\r
 421                 cmp     r14, #0xEE000000\r
 422                 bne             vRegTestError2\r
 423 \r
 424                 ; This task is still running without jumping to vRegTestError2, so increment\r
 425                 ; the loop counter so the check task knows the task is running error free.\r
 426                 stmfd   sp!, { r0-r1 }\r
 427                 ldr             r0, Count2Const\r
 428                 ldr             r1, [r0]\r
 429                 add             r1, r1, #1\r
 430                 str     r1, [r0]\r
 431                 ldmfd   sp!, { r0-r1 }\r
 432 \r
 433                 ; Loop again, performing the same tests.\r
 434                 b               vRegTestLoop2\r
 435 \r
 436 Count2Const     .word   ulRegTest2Counter\r
 437 \r
 438 vRegTestError2:\r
 439                 b       vRegTestError2\r
 440 \r
 441 ;-------------------------------------------------\r
 442 \r
 443 \r
 444 \r