2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
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32 The implementation provided in this file is intended to demonstrate using
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33 queues to pass data into and out of interrupts, and to demonstrate context
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34 switching from inside an interrupt service routine. It is *not* intended to
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35 represent an efficient implementation. Real implementations should not pass
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36 individual characters on queues, but instead use RAM buffers, DMA and/or
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37 FIFO features as appropriate. Semaphores can be used to signal a task that
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38 data is available to be processed.
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41 /* Scheduler includes. */
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42 #include "FreeRTOS.h"
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46 /* Demo application includes. */
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49 /*-----------------------------------------------------------*/
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51 /* Registers required to configure the SCI. */
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52 #define serialSCI_GCR0_REG ( * ( ( volatile unsigned long * ) 0xFFF7E400 ) )
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53 #define serialSCI_GCR1_REG ( * ( ( volatile unsigned long * ) 0xFFF7E404 ) )
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54 #define serialSCI_GCR2_REG ( * ( ( volatile unsigned long * ) 0xFFF7E408 ) )
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55 #define serialSCI_SETINT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E40C ) )
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56 #define serialSCI_CLRINT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E410 ) )
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57 #define serialSCI_SETINTLVL_REG ( * ( ( volatile unsigned long * ) 0xFFF7E414 ) )
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58 #define serialSCI_CLRINTLVL_REG ( * ( ( volatile unsigned long * ) 0xFFF7E418 ) )
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59 #define serialSCI_FLR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E41C ) )
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60 #define serialSCI_INTVEC0_REG ( * ( ( volatile unsigned long * ) 0xFFF7E420 ) )
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61 #define serialSCI_INTVEC1_REG ( * ( ( volatile unsigned long * ) 0xFFF7E424 ) )
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62 #define serialSCI_LENGTH_REG ( * ( ( volatile unsigned long * ) 0xFFF7E428 ) )
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63 #define serialSCI_BAUD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E42C ) )
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64 #define serialSCI_RD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E434 ) )
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65 #define serialSCI_TD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E438 ) )
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66 #define serialSCI_FUN_REG ( * ( ( volatile unsigned long * ) 0xFFF7E43C ) )
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67 #define serialSCI_DIR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E440 ) )
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68 #define serialSCI_DIN_REG ( * ( ( volatile unsigned long * ) 0xFFF7E444 ) )
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69 #define serialSCI_DOUT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E448 ) )
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70 #define serialSCI_DSET_REG ( * ( ( volatile unsigned long * ) 0xFFF7E44C ) )
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71 #define serialSCI_DCLR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E450 ) )
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74 #define serialSCI_FE_INT ( 0x04000000 ) /* framming error */
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75 #define serialSCI_OE_INT ( 0x02000000 ) /* overrun error */
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76 #define serialSCI_PE_INT ( 0x01000000 ) /* parity error */
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77 #define serialSCI_RX_INT ( 0x00000200 ) /* receive buffer ready */
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78 #define serialSCI_TX_INT ( 0x00000100 ) /* transmit buffer ready */
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79 #define serialSCI_WAKE_INT ( 0x00000002 ) /* wakeup */
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80 #define serialSCI_BREAK_INT ( 0x00000001 ) /* break detect */
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81 #define serialSCI_IDLE_FLG ( 0x00000004 ) /* IDLE flasg */
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83 /* Registers required to configure the VIM. */
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84 #define serialVIM_REQMASKSET0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFE30 ) )
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85 #define serialVIM_SCIHINT_RAM ( * ( ( void (**)(void) ) 0xFFF82038 ) )
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88 #define serialBAURATE 19200.0 /* Baudrate in Hz */
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90 /*-----------------------------------------------------------*/
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93 #define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
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94 #define serNO_BLOCK ( ( TickType_t ) 0 )
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95 #define serTX_BLOCK_TIME ( 40 / portTICK_PERIOD_MS )
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97 /*-----------------------------------------------------------*/
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99 /* The queue used to hold received characters. */
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100 static QueueHandle_t xRxedChars = NULL;
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101 static QueueHandle_t xCharsForTx = NULL;
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103 /*-----------------------------------------------------------*/
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105 /* UART interrupt handler. */
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106 __interrupt void vSCIInterruptHandler( void );
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108 /*-----------------------------------------------------------*/
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111 * See the serial2.h header file.
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113 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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115 xComPortHandle xReturn = ( xComPortHandle ) 0;
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117 /* unused parameters, demo has a fixed baud rate (19200) */
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118 ( void ) ulWantedBaud;
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120 /* Create the queues used to hold Rx/Tx characters. */
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121 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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122 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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124 /* If the queue/semaphore was created correctly then setup the serial port
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126 if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
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128 /* Initalise SCI1 */
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129 /* Bring SCI out of reset */
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130 serialSCI_GCR0_REG = 0x00000001UL;
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131 /* Disable all interrupts */
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132 serialSCI_CLRINT_REG = 0xFFFFFFFFUL;
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133 /* All Interrupt to SCI High Level */
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134 serialSCI_CLRINTLVL_REG = 0xFFFFFFFFUL;
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135 /* Global control 1 */
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136 serialSCI_GCR1_REG = 0x03010032UL;
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138 serialSCI_BAUD_REG = ((unsigned long)((configCPU_CLOCK_HZ / (16.0 * serialBAURATE) + 0.5)) - 1) & 0x00FFFFFF;
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139 /* Transmission length (8-bit) */
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140 serialSCI_LENGTH_REG = 8 - 1;
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141 /* Set SCI pins functional mode */
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142 serialSCI_FUN_REG = 0x00000006UL;
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143 /* Enable RX interrupt */
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144 serialSCI_SETINT_REG = 0x00000200UL;
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145 /* Finally start SCI1 */
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146 serialSCI_GCR1_REG |= 0x00000080UL;
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148 /* Setup interrupt routine address in VIM table */
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149 serialVIM_SCIHINT_RAM = &vSCIInterruptHandler;
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150 /* Enable SCI interrupt in VIM */
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151 serialVIM_REQMASKSET0_REG = 0x00002000UL;
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154 /* This demo file only supports a single port but we have to return
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155 something to comply with the standard demo header file. */
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158 /*-----------------------------------------------------------*/
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160 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
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162 /* The port handle is not required as this driver only supports one port. */
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165 /* Get the next character from the buffer. Return false if no characters
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166 are available, or arrive before xBlockTime expires. */
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167 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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176 /*-----------------------------------------------------------*/
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178 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
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180 signed char *pxNext;
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182 /* A couple of parameters that this port does not use. */
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183 ( void ) usStringLength;
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185 /* NOTE: This implementation does not handle the queue being full as no
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186 block time is used! */
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188 /* Send each character in the string, one at a time. */
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189 pxNext = ( signed char * ) pcString;
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192 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
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196 /*-----------------------------------------------------------*/
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198 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
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200 signed portBASE_TYPE xReturn;
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202 /* check if we are already transmitting */
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203 if ( (serialSCI_SETINT_REG & serialSCI_TX_INT) == 0)
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207 /* Wait until IDLE idle period is finished */
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208 while ( (serialSCI_FLR_REG & serialSCI_IDLE_FLG) != 0 )
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213 /* Need to send first byte before interrupts flags are set. */
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214 serialSCI_TD_REG = cOutChar;
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216 /* Enable the TX interrupt. */
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217 serialSCI_SETINT_REG = serialSCI_TX_INT;
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221 else if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
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232 /*-----------------------------------------------------------*/
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234 void vSerialClose( xComPortHandle xPort )
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236 /* Not supported as not required by the demo application. */
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238 /*-----------------------------------------------------------*/
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240 __interrupt void vSCIInterruptHandler( void )
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242 /* xHigherPriorityTaskWoken must be initialised to pdFALSE. */
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243 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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245 portBASE_TYPE xVectorValue = serialSCI_INTVEC0_REG;
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247 switch( xVectorValue )
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250 /* Receive buffer full interrupt, send received char to queue */
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251 cChar = serialSCI_RD_REG;
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252 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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256 /* Transmit buffer empty interrupt received */
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257 /* Are there any more characters to transmit? */
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258 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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260 /* A character was retrieved from the queue so can be sent to
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262 serialSCI_TD_REG = cChar;
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266 /* no more bytes, clear the TX interrupt */
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267 serialSCI_CLRINT_REG = serialSCI_TX_INT;
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272 /* unused interrupt, clear flags */
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273 serialSCI_FLR_REG = 0x07000003;
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276 /* If calling xQueueSendFromISR() above caused a task to leave the blocked
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277 state, and the task that left the blocked state has a priority above the
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278 task that this interrupt interrupted, then xHighPriorityTaskWoken will have
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279 been set to pdTRUE. If xHigherPriorityTaskWoken equals true then calling
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280 portYIELD_FROM_ISR() will result in this interrupt returning directly to the
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282 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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