1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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9 /* Description : ARM-v7 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
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17 _SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
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18 _IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
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19 _FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
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20 _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
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22 /* Define Memories in the system */
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26 psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
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27 psu_ocm_S_AXI_BASEADDR : ORIGIN = 0xFF960000, LENGTH = 0x10000
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28 psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
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29 psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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30 psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
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31 psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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32 psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000
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33 psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000
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34 psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000
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35 psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000
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36 psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000
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37 psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000
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38 psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000
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39 psu_r5_tcm_ram_0_S_AXI_BASEADDR : ORIGIN = 0x100, LENGTH = 0x1FF01
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42 /* Specify the default entry point to the program */
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46 /* Define the sections, and where they are mapped in memory */
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51 KEEP (*(.freertos_vectors))
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59 *(.gnu.linkonce.t.*)
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62 *(.gcc_execpt_table)
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67 *(.gnu.linkonce.armextab.*)
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68 } > psu_r5_ddr_0_S_AXI_BASEADDR
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72 } > psu_r5_ddr_0_S_AXI_BASEADDR
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76 } > psu_r5_ddr_0_S_AXI_BASEADDR
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80 } > psu_r5_ddr_0_S_AXI_BASEADDR
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83 KEEP (*(.note-ABI-tag))
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84 } > psu_r5_ddr_0_S_AXI_BASEADDR
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90 *(.gnu.linkonce.r.*)
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92 } > psu_r5_ddr_0_S_AXI_BASEADDR
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95 __rodata1_start = .;
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99 } > psu_r5_ddr_0_S_AXI_BASEADDR
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102 __sdata2_start = .;
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105 *(.gnu.linkonce.s2.*)
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107 } > psu_r5_ddr_0_S_AXI_BASEADDR
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113 *(.gnu.linkonce.sb2.*)
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115 } > psu_r5_ddr_0_S_AXI_BASEADDR
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121 *(.gnu.linkonce.d.*)
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126 } > psu_r5_ddr_0_S_AXI_BASEADDR
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133 } > psu_r5_ddr_0_S_AXI_BASEADDR
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137 } > psu_r5_ddr_0_S_AXI_BASEADDR
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141 ___CTORS_LIST___ = .;
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142 KEEP (*crtbegin.o(.ctors))
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143 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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144 KEEP (*(SORT(.ctors.*)))
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147 ___CTORS_END___ = .;
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148 } > psu_r5_ddr_0_S_AXI_BASEADDR
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152 ___DTORS_LIST___ = .;
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153 KEEP (*crtbegin.o(.dtors))
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154 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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155 KEEP (*(SORT(.dtors.*)))
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158 ___DTORS_END___ = .;
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159 } > psu_r5_ddr_0_S_AXI_BASEADDR
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165 } > psu_r5_ddr_0_S_AXI_BASEADDR
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169 } > psu_r5_ddr_0_S_AXI_BASEADDR
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172 __eh_framehdr_start = .;
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174 __eh_framehdr_end = .;
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175 } > psu_r5_ddr_0_S_AXI_BASEADDR
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177 .gcc_except_table : {
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178 *(.gcc_except_table)
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179 } > psu_r5_ddr_0_S_AXI_BASEADDR
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181 .mmu_tbl (ALIGN(16384)) : {
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182 __mmu_tbl_start = .;
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185 } > psu_r5_ddr_0_S_AXI_BASEADDR
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190 *(.gnu.linkonce.armexidix.*.*)
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192 } > psu_r5_ddr_0_S_AXI_BASEADDR
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195 __preinit_array_start = .;
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196 KEEP (*(SORT(.preinit_array.*)))
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197 KEEP (*(.preinit_array))
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198 __preinit_array_end = .;
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199 } > psu_r5_ddr_0_S_AXI_BASEADDR
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202 __init_array_start = .;
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203 KEEP (*(SORT(.init_array.*)))
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204 KEEP (*(.init_array))
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205 __init_array_end = .;
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206 } > psu_r5_ddr_0_S_AXI_BASEADDR
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209 __fini_array_start = .;
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210 KEEP (*(SORT(.fini_array.*)))
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211 KEEP (*(.fini_array))
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212 __fini_array_end = .;
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213 } > psu_r5_ddr_0_S_AXI_BASEADDR
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215 .ARM.attributes : {
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216 __ARM.attributes_start = .;
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218 __ARM.attributes_end = .;
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219 } > psu_r5_ddr_0_S_AXI_BASEADDR
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225 *(.gnu.linkonce.s.*)
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227 } > psu_r5_ddr_0_S_AXI_BASEADDR
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233 *(.gnu.linkonce.sb.*)
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235 } > psu_r5_ddr_0_S_AXI_BASEADDR
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241 *(.gnu.linkonce.td.*)
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243 } > psu_r5_ddr_0_S_AXI_BASEADDR
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249 *(.gnu.linkonce.tb.*)
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251 } > psu_r5_ddr_0_S_AXI_BASEADDR
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258 *(.gnu.linkonce.b.*)
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262 } > psu_r5_ddr_0_S_AXI_BASEADDR
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264 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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266 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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268 /* Generate Stack and Heap definitions */
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278 } > psu_r5_ddr_0_S_AXI_BASEADDR
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280 .stack (NOLOAD) : {
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287 _irq_stack_end = .;
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288 . += _IRQ_STACK_SIZE;
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290 _supervisor_stack_end = .;
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291 . += _SUPERVISOR_STACK_SIZE;
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293 __supervisor_stack = .;
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294 _abort_stack_end = .;
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295 . += _ABORT_STACK_SIZE;
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298 _fiq_stack_end = .;
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299 . += _FIQ_STACK_SIZE;
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302 _undef_stack_end = .;
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303 . += _UNDEF_STACK_SIZE;
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306 } > psu_r5_ddr_0_S_AXI_BASEADDR
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