Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / include / xparameters.h

/* Definition for CPU ID */\r
#define XPAR_CPU_ID 0\r
\r
/* Definitions for peripheral PSU_CORTEXR5_0 */\r
#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_CORTEXR5_0 */\r
#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995\r
\r
\r
/******************************************************************/\r
\r
 /* Definition for PSS REF CLK FREQUENCY */\r
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U\r
\r
#include "xparameters_ps.h"\r
\r
/******************************************************************/\r
\r
/*\r
 * Definitions of PSU_TTC_3 counter 0 base address and frequency used\r
 * by sleep and usleep APIs\r
 */\r
\r
#define SLEEP_TIMER_BASEADDR 0xFF140000\r
#define SLEEP_TIMER_FREQUENCY 100000000\r
\r
/******************************************************************/\r
\r
\r
/* Number of Fabric Resets */\r
#define XPAR_NUM_FABRIC_RESETS 1\r
\r
#define STDIN_BASEADDRESS 0xFF000000\r
#define STDOUT_BASEADDRESS 0xFF000000\r
\r
/******************************************************************/\r
\r
/* Definitions for driver AXIPMON */\r
#define XPAR_XAXIPMON_NUM_INSTANCES 4\r
\r
/* Definitions for peripheral PSU_APM_0 */\r
#define XPAR_PSU_APM_0_DEVICE_ID 0\r
#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000\r
#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF\r
#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1\r
#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6\r
#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10\r
#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0\r
#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32\r
#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1\r
#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1\r
#define XPAR_PSU_APM_0_ENABLE_PROFILE 0\r
#define XPAR_PSU_APM_0_ENABLE_TRACE 0\r
#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1\r
\r
\r
/* Definitions for peripheral PSU_APM_1 */\r
#define XPAR_PSU_APM_1_DEVICE_ID 1\r
#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000\r
#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF\r
#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1\r
#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1\r
#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3\r
#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0\r
#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32\r
#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1\r
#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1\r
#define XPAR_PSU_APM_1_ENABLE_PROFILE 0\r
#define XPAR_PSU_APM_1_ENABLE_TRACE 0\r
#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1\r
\r
\r
/* Definitions for peripheral PSU_APM_2 */\r
#define XPAR_PSU_APM_2_DEVICE_ID 2\r
#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000\r
#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF\r
#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1\r
#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1\r
#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3\r
#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0\r
#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32\r
#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1\r
#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1\r
#define XPAR_PSU_APM_2_ENABLE_PROFILE 0\r
#define XPAR_PSU_APM_2_ENABLE_TRACE 0\r
#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1\r
\r
\r
/* Definitions for peripheral PSU_APM_5 */\r
#define XPAR_PSU_APM_5_DEVICE_ID 3\r
#define XPAR_PSU_APM_5_BASEADDR 0xFD490000\r
#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF\r
#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1\r
#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1\r
#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3\r
#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0\r
#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32\r
#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1\r
#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1\r
#define XPAR_PSU_APM_5_ENABLE_PROFILE 0\r
#define XPAR_PSU_APM_5_ENABLE_TRACE 0\r
#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_APM_0 */\r
#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID\r
#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000\r
#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF\r
#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1\r
#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6\r
#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10\r
#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0\r
#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32\r
#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1\r
#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1\r
#define XPAR_AXIPMON_0_ENABLE_PROFILE 0\r
#define XPAR_AXIPMON_0_ENABLE_TRACE 0\r
#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1\r
\r
/* Canonical definitions for peripheral PSU_APM_1 */\r
#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID\r
#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000\r
#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF\r
#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1\r
#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1\r
#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3\r
#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0\r
#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32\r
#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1\r
#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1\r
#define XPAR_AXIPMON_1_ENABLE_PROFILE 0\r
#define XPAR_AXIPMON_1_ENABLE_TRACE 0\r
#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1\r
\r
/* Canonical definitions for peripheral PSU_APM_2 */\r
#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID\r
#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000\r
#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF\r
#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1\r
#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1\r
#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3\r
#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0\r
#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32\r
#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1\r
#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1\r
#define XPAR_AXIPMON_2_ENABLE_PROFILE 0\r
#define XPAR_AXIPMON_2_ENABLE_TRACE 0\r
#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1\r
\r
/* Canonical definitions for peripheral PSU_APM_5 */\r
#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID\r
#define XPAR_AXIPMON_3_BASEADDR 0xFD490000\r
#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF\r
#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32\r
#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1\r
#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1\r
#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3\r
#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1\r
#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0\r
#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32\r
#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56\r
#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1\r
#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1\r
#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1\r
#define XPAR_AXIPMON_3_ENABLE_PROFILE 0\r
#define XPAR_AXIPMON_3_ENABLE_TRACE 0\r
#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000\r
#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000\r
#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver CANPS */\r
#define XPAR_XCANPS_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_CAN_1 */\r
#define XPAR_PSU_CAN_1_DEVICE_ID 0\r
#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000\r
#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF\r
#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_CAN_1 */\r
#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID\r
#define XPAR_XCANPS_0_BASEADDR 0xFF070000\r
#define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF\r
#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver CSUDMA */\r
#define XPAR_XCSUDMA_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_CSUDMA */\r
#define XPAR_PSU_CSUDMA_DEVICE_ID 0\r
#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000\r
#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF\r
#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_CSUDMA */\r
#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID\r
#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000\r
#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF\r
#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver DDRCPSU */\r
#define XPAR_XDDRCPSU_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_DDRC_0 */\r
#define XPAR_PSU_DDRC_0_DEVICE_ID 0\r
#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000\r
#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF\r
#define XPAR_PSU_DDRC_0_HAS_ECC 0\r
#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_DDRC_0 */\r
#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID\r
#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000\r
#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF\r
#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver EMACPS */\r
#define XPAR_XEMACPS_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_ETHERNET_3 */\r
#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0\r
#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000\r
#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF\r
#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60\r
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_ETHERNET_3 */\r
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID\r
#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000\r
#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF\r
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749\r
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12\r
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1\r
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60\r
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1\r
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60\r
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10\r
\r
\r
/******************************************************************/\r
\r
\r
/* Definitions for peripheral PSU_AFI_0 */\r
#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000\r
#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_1 */\r
#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000\r
#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_2 */\r
#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000\r
#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_3 */\r
#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000\r
#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_4 */\r
#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000\r
#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_5 */\r
#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000\r
#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF\r
\r
\r
/* Definitions for peripheral PSU_AFI_6 */\r
#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000\r
#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF\r
\r
\r
/* Definitions for peripheral PSU_APU */\r
#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000\r
#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF\r
\r
\r
/* Definitions for peripheral PSU_CCI_GPV */\r
#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000\r
#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF\r
\r
\r
/* Definitions for peripheral PSU_CCI_REG */\r
#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000\r
#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF\r
\r
\r
/* Definitions for peripheral PSU_CRF_APB */\r
#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000\r
#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF\r
\r
\r
/* Definitions for peripheral PSU_CRL_APB */\r
#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000\r
#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF\r
\r
\r
/* Definitions for peripheral PSU_CSU_0 */\r
#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000\r
#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_PHY */\r
#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000\r
#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_QOS_CTRL */\r
#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000\r
#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU0_CFG */\r
#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000\r
#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU1_CFG */\r
#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000\r
#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU2_CFG */\r
#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000\r
#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU3_CFG */\r
#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000\r
#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU4_CFG */\r
#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000\r
#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF\r
\r
\r
/* Definitions for peripheral PSU_DDR_XMPU5_CFG */\r
#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000\r
#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF\r
\r
\r
/* Definitions for peripheral PSU_DP */\r
#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000\r
#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF\r
\r
\r
/* Definitions for peripheral PSU_DPDMA */\r
#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000\r
#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF\r
\r
\r
/* Definitions for peripheral PSU_EFUSE */\r
#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000\r
#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF\r
\r
\r
/* Definitions for peripheral PSU_FPD_GPV */\r
#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000\r
#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF\r
\r
\r
/* Definitions for peripheral PSU_FPD_SLCR */\r
#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000\r
#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF\r
\r
\r
/* Definitions for peripheral PSU_FPD_SLCR_SECURE */\r
#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000\r
#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF\r
\r
\r
/* Definitions for peripheral PSU_FPD_XMPU_CFG */\r
#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000\r
#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF\r
\r
\r
/* Definitions for peripheral PSU_FPD_XMPU_SINK */\r
#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000\r
#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF\r
\r
\r
/* Definitions for peripheral PSU_GPU */\r
#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000\r
#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF\r
\r
\r
/* Definitions for peripheral PSU_IOU_SCNTR */\r
#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000\r
#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF\r
\r
\r
/* Definitions for peripheral PSU_IOU_SCNTRS */\r
#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000\r
#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF\r
\r
\r
/* Definitions for peripheral PSU_IOUSECURE_SLCR */\r
#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000\r
#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF\r
\r
\r
/* Definitions for peripheral PSU_IOUSLCR_0 */\r
#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000\r
#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF\r
\r
\r
/* Definitions for peripheral PSU_LPD_SLCR */\r
#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000\r
#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF\r
\r
\r
/* Definitions for peripheral PSU_LPD_SLCR_SECURE */\r
#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000\r
#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF\r
\r
\r
/* Definitions for peripheral PSU_LPD_XPPU */\r
#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000\r
#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF\r
\r
\r
/* Definitions for peripheral PSU_LPD_XPPU_SINK */\r
#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000\r
#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF\r
\r
\r
/* Definitions for peripheral PSU_MBISTJTAG */\r
#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000\r
#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF\r
\r
\r
/* Definitions for peripheral PSU_OCM */\r
#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000\r
#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF\r
\r
\r
/* Definitions for peripheral PSU_OCM_RAM_0 */\r
#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000\r
#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF\r
\r
\r
/* Definitions for peripheral PSU_OCM_XMPU_CFG */\r
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000\r
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF\r
\r
\r
/* Definitions for peripheral PSU_PCIE */\r
#define XPAR_PSU_PCIE_S_AXI_BASEADDR 0xFD0E0000\r
#define XPAR_PSU_PCIE_S_AXI_HIGHADDR 0xFD0EFFFF\r
\r
\r
/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */\r
#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_BASEADDR 0xFD480000\r
#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_HIGHADDR 0xFD48FFFF\r
\r
\r
/* Definitions for peripheral PSU_PCIE_DMA */\r
#define XPAR_PSU_PCIE_DMA_S_AXI_BASEADDR 0xFD0F0000\r
#define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF\r
\r
\r
/* Definitions for peripheral PSU_PCIE_LOW */\r
#define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000\r
#define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF\r
\r
\r
/* Definitions for peripheral PSU_PMU_GLOBAL_0 */\r
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000\r
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF\r
\r
\r
/* Definitions for peripheral PSU_PMU_IOMODULE */\r
#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000\r
#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF\r
\r
\r
/* Definitions for peripheral PSU_QSPI_LINEAR_0 */\r
#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000\r
#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_0_ATCM */\r
#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000\r
#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_0_BTCM */\r
#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000\r
#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_DDR_0 */\r
#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000\r
#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_TCM_RAM_0 */\r
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000\r
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF\r
\r
\r
/* Definitions for peripheral PSU_RPU */\r
#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000\r
#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF\r
\r
\r
/* Definitions for peripheral PSU_RSA */\r
#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000\r
#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF\r
\r
\r
/* Definitions for peripheral PSU_SATA */\r
#define XPAR_PSU_SATA_S_AXI_BASEADDR 0xFD0C0000\r
#define XPAR_PSU_SATA_S_AXI_HIGHADDR 0xFD0CFFFF\r
\r
\r
/* Definitions for peripheral PSU_SERDES */\r
#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000\r
#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF\r
\r
\r
/* Definitions for peripheral PSU_SIOU */\r
#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000\r
#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF\r
\r
\r
/* Definitions for peripheral PSU_SMMU_GPV */\r
#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000\r
#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF\r
\r
\r
/* Definitions for peripheral PSU_SMMU_REG */\r
#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000\r
#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver GPIOPS */\r
#define XPAR_XGPIOPS_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_GPIO_0 */\r
#define XPAR_PSU_GPIO_0_DEVICE_ID 0\r
#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000\r
#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_GPIO_0 */\r
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID\r
#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000\r
#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver IICPS */\r
#define XPAR_XIICPS_NUM_INSTANCES 2\r
\r
/* Definitions for peripheral PSU_I2C_0 */\r
#define XPAR_PSU_I2C_0_DEVICE_ID 0\r
#define XPAR_PSU_I2C_0_BASEADDR 0xFF020000\r
#define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF\r
#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999\r
\r
\r
/* Definitions for peripheral PSU_I2C_1 */\r
#define XPAR_PSU_I2C_1_DEVICE_ID 1\r
#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000\r
#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF\r
#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_I2C_0 */\r
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID\r
#define XPAR_XIICPS_0_BASEADDR 0xFF020000\r
#define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF\r
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999\r
\r
/* Canonical definitions for peripheral PSU_I2C_1 */\r
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID\r
#define XPAR_XIICPS_1_BASEADDR 0xFF030000\r
#define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF\r
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999\r
\r
\r
/******************************************************************/\r
\r
#define  XPAR_XIPIPSU_NUM_INSTANCES  2\r
\r
/* Parameter definitions for peripheral psu_ipi_1 */\r
#define  XPAR_PSU_IPI_1_DEVICE_ID  0\r
#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000\r
#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100\r
#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0\r
#define  XPAR_PSU_IPI_1_INT_ID  65\r
\r
/* Parameter definitions for peripheral psu_ipi_2 */\r
#define  XPAR_PSU_IPI_2_DEVICE_ID  1\r
#define  XPAR_PSU_IPI_2_BASE_ADDRESS  0xFF320000\r
#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200\r
#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1\r
#define  XPAR_PSU_IPI_2_INT_ID  66\r
\r
/* Canonical definitions for peripheral psu_ipi_1 */\r
#define  XPAR_XIPIPSU_0_DEVICE_ID       XPAR_PSU_IPI_1_DEVICE_ID\r
#define  XPAR_XIPIPSU_0_BASE_ADDRESS    XPAR_PSU_IPI_1_BASE_ADDRESS\r
#define  XPAR_XIPIPSU_0_BIT_MASK        XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPSU_0_BUFFER_INDEX    XPAR_PSU_IPI_1_BUFFER_INDEX\r
#define  XPAR_XIPIPSU_0_INT_ID  XPAR_PSU_IPI_1_INT_ID\r
\r
/* Canonical definitions for peripheral psu_ipi_2 */\r
#define  XPAR_XIPIPSU_1_DEVICE_ID       XPAR_PSU_IPI_2_DEVICE_ID\r
#define  XPAR_XIPIPSU_1_BASE_ADDRESS    XPAR_PSU_IPI_2_BASE_ADDRESS\r
#define  XPAR_XIPIPSU_1_BIT_MASK        XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPSU_1_BUFFER_INDEX    XPAR_PSU_IPI_2_BUFFER_INDEX\r
#define  XPAR_XIPIPSU_1_INT_ID  XPAR_PSU_IPI_2_INT_ID\r
\r
#define  XPAR_XIPIPSU_NUM_TARGETS  11\r
\r
#define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001\r
#define  XPAR_PSU_IPI_0_BUFFER_INDEX  2\r
#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100\r
#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0\r
#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200\r
#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1\r
#define  XPAR_PSU_IPI_3_BIT_MASK  0x00010000\r
#define  XPAR_PSU_IPI_3_BUFFER_INDEX  7\r
#define  XPAR_PSU_IPI_4_BIT_MASK  0x00020000\r
#define  XPAR_PSU_IPI_4_BUFFER_INDEX  7\r
#define  XPAR_PSU_IPI_5_BIT_MASK  0x00040000\r
#define  XPAR_PSU_IPI_5_BUFFER_INDEX  7\r
#define  XPAR_PSU_IPI_6_BIT_MASK  0x00080000\r
#define  XPAR_PSU_IPI_6_BUFFER_INDEX  7\r
#define  XPAR_PSU_IPI_7_BIT_MASK  0x01000000\r
#define  XPAR_PSU_IPI_7_BUFFER_INDEX  3\r
#define  XPAR_PSU_IPI_8_BIT_MASK  0x02000000\r
#define  XPAR_PSU_IPI_8_BUFFER_INDEX  4\r
#define  XPAR_PSU_IPI_9_BIT_MASK  0x04000000\r
#define  XPAR_PSU_IPI_9_BUFFER_INDEX  5\r
#define  XPAR_PSU_IPI_10_BIT_MASK  0x08000000\r
#define  XPAR_PSU_IPI_10_BUFFER_INDEX  6\r
/* Target List for referring to processor IPI Targets */\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2\r
\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK\r
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6\r
\r
/* Definitions for driver QSPIPSU */\r
#define XPAR_XQSPIPSU_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_QSPI_0 */\r
#define XPAR_PSU_QSPI_0_DEVICE_ID 0\r
#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000\r
#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF\r
#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749\r
#define XPAR_PSU_QSPI_0_QSPI_MODE 2\r
#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_QSPI_0 */\r
#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID\r
#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000\r
#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF\r
#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749\r
#define XPAR_XQSPIPSU_0_QSPI_MODE 2\r
#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver RTCPSU */\r
#define XPAR_XRTCPSU_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_RTC */\r
#define XPAR_PSU_RTC_DEVICE_ID 0\r
#define XPAR_PSU_RTC_BASEADDR 0xFFA60000\r
#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_RTC */\r
#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID\r
#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000\r
#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver SCUGIC */\r
#define XPAR_XSCUGIC_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_RCPU_GIC */\r
#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0\r
#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000\r
#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFF\r
#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_RCPU_GIC */\r
#define XPAR_SCUGIC_0_DEVICE_ID 0\r
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000\r
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF\r
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver SDPS */\r
#define XPAR_XSDPS_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_SD_1 */\r
#define XPAR_PSU_SD_1_DEVICE_ID 0\r
#define XPAR_PSU_SD_1_BASEADDR 0xFF170000\r
#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF\r
#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006\r
#define XPAR_PSU_SD_1_HAS_CD 1\r
#define XPAR_PSU_SD_1_HAS_WP 1\r
#define XPAR_PSU_SD_1_BUS_WIDTH 4\r
#define XPAR_PSU_SD_1_MIO_BANK 1\r
#define XPAR_PSU_SD_1_HAS_EMIO 0\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_SD_1 */\r
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID\r
#define XPAR_XSDPS_0_BASEADDR 0xFF170000\r
#define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF\r
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006\r
#define XPAR_XSDPS_0_HAS_CD 1\r
#define XPAR_XSDPS_0_HAS_WP 1\r
#define XPAR_XSDPS_0_BUS_WIDTH 4\r
#define XPAR_XSDPS_0_MIO_BANK 1\r
#define XPAR_XSDPS_0_HAS_EMIO 0\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver SYSMONPSU */\r
#define XPAR_XSYSMONPSU_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_AMS */\r
#define XPAR_PSU_AMS_DEVICE_ID 0\r
#define XPAR_PSU_AMS_BASEADDR 0xFFA50000\r
#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_AMS */\r
#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID\r
#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000\r
#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver TTCPS */\r
#define XPAR_XTTCPS_NUM_INSTANCES 12\r
\r
/* Definitions for peripheral PSU_TTC_0 */\r
#define XPAR_PSU_TTC_0_DEVICE_ID 0\r
#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000\r
#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_1_DEVICE_ID 1\r
#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004\r
#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_2_DEVICE_ID 2\r
#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008\r
#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0\r
\r
\r
/* Definitions for peripheral PSU_TTC_1 */\r
#define XPAR_PSU_TTC_3_DEVICE_ID 3\r
#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000\r
#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_4_DEVICE_ID 4\r
#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004\r
#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_5_DEVICE_ID 5\r
#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008\r
#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0\r
\r
\r
/* Definitions for peripheral PSU_TTC_2 */\r
#define XPAR_PSU_TTC_6_DEVICE_ID 6\r
#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000\r
#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_7_DEVICE_ID 7\r
#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004\r
#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_8_DEVICE_ID 8\r
#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008\r
#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0\r
\r
\r
/* Definitions for peripheral PSU_TTC_3 */\r
#define XPAR_PSU_TTC_9_DEVICE_ID 9\r
#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000\r
#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_10_DEVICE_ID 10\r
#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004\r
#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0\r
#define XPAR_PSU_TTC_11_DEVICE_ID 11\r
#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008\r
#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_TTC_0 */\r
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID\r
#define XPAR_XTTCPS_0_BASEADDR 0xFF110000\r
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID\r
#define XPAR_XTTCPS_1_BASEADDR 0xFF110004\r
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID\r
#define XPAR_XTTCPS_2_BASEADDR 0xFF110008\r
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0\r
\r
/* Canonical definitions for peripheral PSU_TTC_1 */\r
#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID\r
#define XPAR_XTTCPS_3_BASEADDR 0xFF120000\r
#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID\r
#define XPAR_XTTCPS_4_BASEADDR 0xFF120004\r
#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID\r
#define XPAR_XTTCPS_5_BASEADDR 0xFF120008\r
#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0\r
\r
/* Canonical definitions for peripheral PSU_TTC_2 */\r
#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID\r
#define XPAR_XTTCPS_6_BASEADDR 0xFF130000\r
#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID\r
#define XPAR_XTTCPS_7_BASEADDR 0xFF130004\r
#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID\r
#define XPAR_XTTCPS_8_BASEADDR 0xFF130008\r
#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0\r
\r
/* Canonical definitions for peripheral PSU_TTC_3 */\r
#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID\r
#define XPAR_XTTCPS_9_BASEADDR 0xFF140000\r
#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID\r
#define XPAR_XTTCPS_10_BASEADDR 0xFF140004\r
#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0\r
\r
#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID\r
#define XPAR_XTTCPS_11_BASEADDR 0xFF140008\r
#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000\r
#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver UARTPS */\r
#define XPAR_XUARTPS_NUM_INSTANCES 2\r
\r
/* Definitions for peripheral PSU_UART_0 */\r
#define XPAR_PSU_UART_0_DEVICE_ID 0\r
#define XPAR_PSU_UART_0_BASEADDR 0xFF000000\r
#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF\r
#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999\r
#define XPAR_PSU_UART_0_HAS_MODEM 0\r
\r
\r
/* Definitions for peripheral PSU_UART_1 */\r
#define XPAR_PSU_UART_1_DEVICE_ID 1\r
#define XPAR_PSU_UART_1_BASEADDR 0xFF010000\r
#define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF\r
#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999\r
#define XPAR_PSU_UART_1_HAS_MODEM 0\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_UART_0 */\r
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID\r
#define XPAR_XUARTPS_0_BASEADDR 0xFF000000\r
#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF\r
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999\r
#define XPAR_XUARTPS_0_HAS_MODEM 0\r
\r
/* Canonical definitions for peripheral PSU_UART_1 */\r
#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID\r
#define XPAR_XUARTPS_1_BASEADDR 0xFF010000\r
#define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF\r
#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999\r
#define XPAR_XUARTPS_1_HAS_MODEM 0\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver USBPSU */\r
#define XPAR_XUSBPSU_NUM_INSTANCES 1\r
\r
/* Definitions for peripheral PSU_USB_0 */\r
#define XPAR_PSU_USB_0_DEVICE_ID 0\r
#define XPAR_PSU_USB_0_BASEADDR 0xFE200000\r
#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_USB_0 */\r
#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID\r
#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000\r
#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver WDTPS */\r
#define XPAR_XWDTPS_NUM_INSTANCES 2\r
\r
/* Definitions for peripheral PSU_WDT_0 */\r
#define XPAR_PSU_WDT_0_DEVICE_ID 0\r
#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000\r
#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF\r
#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/* Definitions for peripheral PSU_WDT_1 */\r
#define XPAR_PSU_WDT_1_DEVICE_ID 1\r
#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000\r
#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF\r
#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_WDT_0 */\r
#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID\r
#define XPAR_XWDTPS_0_BASEADDR 0xFF150000\r
#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF\r
#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001\r
\r
/* Canonical definitions for peripheral PSU_WDT_1 */\r
#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID\r
#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000\r
#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF\r
#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/******************************************************************/\r
\r
/* Definitions for driver ZDMA */\r
#define XPAR_XZDMA_NUM_INSTANCES 16\r
\r
/* Definitions for peripheral PSU_ADMA_0 */\r
#define XPAR_PSU_ADMA_0_DEVICE_ID 0\r
#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000\r
#define XPAR_PSU_ADMA_0_DMA_MODE 1\r
#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF\r
#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_1 */\r
#define XPAR_PSU_ADMA_1_DEVICE_ID 1\r
#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000\r
#define XPAR_PSU_ADMA_1_DMA_MODE 1\r
#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF\r
#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_2 */\r
#define XPAR_PSU_ADMA_2_DEVICE_ID 2\r
#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000\r
#define XPAR_PSU_ADMA_2_DMA_MODE 1\r
#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF\r
#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_3 */\r
#define XPAR_PSU_ADMA_3_DEVICE_ID 3\r
#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000\r
#define XPAR_PSU_ADMA_3_DMA_MODE 1\r
#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF\r
#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_4 */\r
#define XPAR_PSU_ADMA_4_DEVICE_ID 4\r
#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000\r
#define XPAR_PSU_ADMA_4_DMA_MODE 1\r
#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF\r
#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_5 */\r
#define XPAR_PSU_ADMA_5_DEVICE_ID 5\r
#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000\r
#define XPAR_PSU_ADMA_5_DMA_MODE 1\r
#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF\r
#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_6 */\r
#define XPAR_PSU_ADMA_6_DEVICE_ID 6\r
#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000\r
#define XPAR_PSU_ADMA_6_DMA_MODE 1\r
#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF\r
#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_ADMA_7 */\r
#define XPAR_PSU_ADMA_7_DEVICE_ID 7\r
#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000\r
#define XPAR_PSU_ADMA_7_DMA_MODE 1\r
#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF\r
#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_0 */\r
#define XPAR_PSU_GDMA_0_DEVICE_ID 8\r
#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000\r
#define XPAR_PSU_GDMA_0_DMA_MODE 0\r
#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF\r
#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_1 */\r
#define XPAR_PSU_GDMA_1_DEVICE_ID 9\r
#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000\r
#define XPAR_PSU_GDMA_1_DMA_MODE 0\r
#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF\r
#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_2 */\r
#define XPAR_PSU_GDMA_2_DEVICE_ID 10\r
#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000\r
#define XPAR_PSU_GDMA_2_DMA_MODE 0\r
#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF\r
#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_3 */\r
#define XPAR_PSU_GDMA_3_DEVICE_ID 11\r
#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000\r
#define XPAR_PSU_GDMA_3_DMA_MODE 0\r
#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF\r
#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_4 */\r
#define XPAR_PSU_GDMA_4_DEVICE_ID 12\r
#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000\r
#define XPAR_PSU_GDMA_4_DMA_MODE 0\r
#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF\r
#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_5 */\r
#define XPAR_PSU_GDMA_5_DEVICE_ID 13\r
#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000\r
#define XPAR_PSU_GDMA_5_DMA_MODE 0\r
#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF\r
#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_6 */\r
#define XPAR_PSU_GDMA_6_DEVICE_ID 14\r
#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000\r
#define XPAR_PSU_GDMA_6_DMA_MODE 0\r
#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF\r
#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/* Definitions for peripheral PSU_GDMA_7 */\r
#define XPAR_PSU_GDMA_7_DEVICE_ID 15\r
#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000\r
#define XPAR_PSU_GDMA_7_DMA_MODE 0\r
#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF\r
#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/******************************************************************/\r
\r
/* Canonical definitions for peripheral PSU_ADMA_0 */\r
#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID\r
#define XPAR_XZDMA_0_BASEADDR 0xFFA80000\r
#define XPAR_XZDMA_0_DMA_MODE 1\r
#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF\r
#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_1 */\r
#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID\r
#define XPAR_XZDMA_1_BASEADDR 0xFFA90000\r
#define XPAR_XZDMA_1_DMA_MODE 1\r
#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF\r
#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_2 */\r
#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID\r
#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000\r
#define XPAR_XZDMA_2_DMA_MODE 1\r
#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF\r
#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_3 */\r
#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID\r
#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000\r
#define XPAR_XZDMA_3_DMA_MODE 1\r
#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF\r
#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_4 */\r
#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID\r
#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000\r
#define XPAR_XZDMA_4_DMA_MODE 1\r
#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF\r
#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_5 */\r
#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID\r
#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000\r
#define XPAR_XZDMA_5_DMA_MODE 1\r
#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF\r
#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_6 */\r
#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID\r
#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000\r
#define XPAR_XZDMA_6_DMA_MODE 1\r
#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF\r
#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_ADMA_7 */\r
#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID\r
#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000\r
#define XPAR_XZDMA_7_DMA_MODE 1\r
#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF\r
#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_0 */\r
#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID\r
#define XPAR_XZDMA_8_BASEADDR 0xFD500000\r
#define XPAR_XZDMA_8_DMA_MODE 0\r
#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF\r
#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_1 */\r
#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID\r
#define XPAR_XZDMA_9_BASEADDR 0xFD510000\r
#define XPAR_XZDMA_9_DMA_MODE 0\r
#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF\r
#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_2 */\r
#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID\r
#define XPAR_XZDMA_10_BASEADDR 0xFD520000\r
#define XPAR_XZDMA_10_DMA_MODE 0\r
#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF\r
#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_3 */\r
#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID\r
#define XPAR_XZDMA_11_BASEADDR 0xFD530000\r
#define XPAR_XZDMA_11_DMA_MODE 0\r
#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF\r
#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_4 */\r
#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID\r
#define XPAR_XZDMA_12_BASEADDR 0xFD540000\r
#define XPAR_XZDMA_12_DMA_MODE 0\r
#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF\r
#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_5 */\r
#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID\r
#define XPAR_XZDMA_13_BASEADDR 0xFD550000\r
#define XPAR_XZDMA_13_DMA_MODE 0\r
#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF\r
#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_6 */\r
#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID\r
#define XPAR_XZDMA_14_BASEADDR 0xFD560000\r
#define XPAR_XZDMA_14_DMA_MODE 0\r
#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF\r
#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0\r
\r
/* Canonical definitions for peripheral PSU_GDMA_7 */\r
#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID\r
#define XPAR_XZDMA_15_BASEADDR 0xFD570000\r
#define XPAR_XZDMA_15_DMA_MODE 0\r
#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF\r
#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0\r
\r
\r
/******************************************************************/\r
\r