1 /******************************************************************************
3 * Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved.
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31 ******************************************************************************/
32 /*****************************************************************************/
35 * The CSU_DMA is present inside CSU (Configuration Security Unit) module which
36 * is located within the Low-Power Subsystem (LPS) internal to the PS.
37 * CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
38 * AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
39 * Stream Switch (SSS).
41 * The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
42 * (read) channel and DST (write) channel. The DMA is effectively able to
44 * - From PS-side to the SSS-side (SRC DMA only)
45 * - From SSS-side to the PS-side (DST DMA only)
46 * - Simultaneous PS-side to SSS_side and SSS-side to the PS-side
48 * <b>Initialization & Configuration</b>
50 * The device driver enables higher layer software (e.g., an application) to
51 * communicate to the CSU_DMA core.
53 * XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
54 * The user needs to first call the XCsuDma_LookupConfig() API which returns
55 * the Configuration structure pointer which is passed as a parameter to the
56 * XCsuDma_CfgInitialize() API.
59 * This driver will not support handling of interrupts user should write handler
60 * to handle the interrupts.
62 * <b> Virtual Memory </b>
64 * This driver supports Virtual Memory. The RTOS is responsible for calculating
65 * the correct device base address in Virtual Memory space.
69 * This driver is not thread safe. Any needs for threads or thread mutual
70 * exclusion must be satisfied by the layer above this driver.
74 * Asserts are used within all Xilinx drivers to enforce constraints on argument
75 * values. Asserts can be turned off on a system-wide basis by defining, at
76 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
77 * is recommended that users leave asserts on during development.
79 * <b> Building the driver </b>
81 * The XCsuDma driver is composed of several source files. This allows the user
82 * to build and link only those parts of the driver that are necessary.
85 * @addtogroup csudma_v1_2
89 * This header file contains identifiers and register-level driver functions (or
90 * macros), range macros, structure typedefs that can be used to access the
91 * Xilinx CSU_DMA core instance.
95 * MODIFICATION HISTORY:
97 * Ver Who Date Changes
98 * ----- ------ -------- -----------------------------------------------------
99 * 1.0 vnsld 22/10/14 First release
100 * 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
101 * source and destination points to the same buffer.
102 * ms 03/17/17 Added readme.txt file in examples folder for doxygen
104 * ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to
105 * include the file in doxygen examples.
106 * 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver.
107 * adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit
108 * dma transfers through PMU processor(CR#996201).
111 ******************************************************************************/
114 #define XCSUDMA_H_ /**< Prevent circular inclusions
115 * by using protection macros */
121 /***************************** Include Files *********************************/
123 #include "xcsudma_hw.h"
124 #include "xil_types.h"
125 #include "xil_assert.h"
127 #include "xil_cache.h"
129 /************************** Constant Definitions *****************************/
131 /** @name CSU_DMA Channels
135 XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */
136 XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */
140 /** @name CSU_DMA pause types
144 XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer
146 XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer
153 /** @name Ranges of Size
156 #define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */
160 /***************** Macros (Inline Functions) Definitions *********************/
162 /*****************************************************************************/
165 * This function resets the CSU_DMA core.
173 * void XCsuDma_Reset()
175 ******************************************************************************/
176 #define XCsuDma_Reset() \
177 Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
178 (u32)(XCSUDMA_RESET_SET_MASK)); \
179 Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
180 (u32)(XCSUDMA_RESET_UNSET_MASK));
182 /*****************************************************************************/
184 * This function will be in busy while loop until the data transfer is
187 * @param InstancePtr is a pointer to XCsuDma instance to be worked on.
188 * @param Channel represents the type of channel either it is Source or
190 * Source channel - XCSUDMA_SRC_CHANNEL
191 * Destination Channel - XCSUDMA_DST_CHANNEL
195 * @note This function should be called after XCsuDma_Transfer in polled
196 * mode to wait until the data gets transfered completely.
198 * void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
199 * XCsuDma_Channel Channel)
201 ******************************************************************************/
202 #define XCsuDma_WaitForDone(InstancePtr,Channel) \
203 while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
204 ((u32)(XCSUDMA_I_STS_OFFSET) + \
205 ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
206 (u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
208 /*****************************************************************************/
211 * This function returns the number of completed SRC/DST DMA transfers that
212 * have not been acknowledged by software based on the channel selection.
214 * @param InstancePtr is a pointer to XCsuDma instance to be worked on.
215 * @param Channel represents the type of channel either it is Source or
217 * Source channel - XCSUDMA_SRC_CHANNEL
218 * Destination Channel - XCSUDMA_DST_CHANNEL
220 * @return Count is number of completed DMA transfers but not acknowledged
222 * - 000 - All finished transfers have been acknowledged.
223 * - Count - Count number of finished transfers are still
228 * u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
229 * XCsuDma_Channel Channel)
231 ******************************************************************************/
232 #define XCsuDma_GetDoneCount(InstancePtr, Channel) \
233 ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
234 ((u32)(XCSUDMA_STS_OFFSET) + \
235 ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
236 (u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
237 (u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
239 /*****************************************************************************/
242 * This function returns the current SRC/DST FIFO level in 32 bit words of the
244 * @param InstancePtr is a pointer to XCsuDma instance to be worked on.
245 * @param Channel represents the type of channel either it is Source or
247 * Source channel - XCSUDMA_SRC_CHANNEL
248 * Destination Channel - XCSUDMA_DST_CHANNEL
250 * @return FIFO level. (Range is 0 to 128)
251 * - 0 Indicates empty
252 * - Any number 1 to 128 indicates the number of entries in FIFO.
256 * u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
257 * XCsuDma_Channel Channel)
259 ******************************************************************************/
260 #define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \
261 ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
262 ((u32)(XCSUDMA_STS_OFFSET) + \
263 ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
264 (u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
265 (u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
267 /*****************************************************************************/
270 * This function returns the current number of read(src)/write(dst) outstanding
271 * commands based on the type of channel selected.
273 * @param InstancePtr is a pointer to XCsuDma instance to be worked on.
274 * @param Channel represents the type of channel either it is Source or
276 * Source channel - XCSUDMA_SRC_CHANNEL
277 * Destination Channel - XCSUDMA_DST_CHANNEL
279 * @return Count of outstanding commands. (Range is 0 to 9).
283 * u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
284 * XCsuDma_Channel Channel)
286 ******************************************************************************/
287 #define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \
288 ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
289 ((u32)(XCSUDMA_STS_OFFSET) + \
290 ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
291 (u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
292 (u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
294 /*****************************************************************************/
297 * This function returns the status of Channel either it is busy or not.
299 * @param InstancePtr is a pointer to XCsuDma instance to be worked on.
300 * @param Channel represents the type of channel either it is Source or
302 * Source channel - XCSUDMA_SRC_CHANNEL
303 * Destination Channel - XCSUDMA_DST_CHANNEL
305 * @return Returns the current status of the core.
306 * - TRUE represents core is currently busy.
307 * - FALSE represents core is not involved in any transfers.
311 * s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
313 ******************************************************************************/
315 #define XCsuDma_IsBusy(InstancePtr, Channel) \
316 ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
317 ((u32)(XCSUDMA_STS_OFFSET) + \
318 ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
319 (u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
323 /**************************** Type Definitions *******************************/
326 * This typedef contains configuration information for a CSU_DMA core.
327 * Each CSU_DMA core should have a configuration structure associated.
330 u16 DeviceId; /**< DeviceId is the unique ID of the
332 u32 BaseAddress; /**< BaseAddress is the physical base address
333 * of the device's registers */
337 /******************************************************************************/
340 * The XCsuDma driver instance data structure. A pointer to an instance data
341 * structure is passed around by functions to refer to a specific driver
345 XCsuDma_Config Config; /**< Hardware configuration */
346 u32 IsReady; /**< Device and the driver instance
351 /******************************************************************************/
353 * This typedef contains all the configuration feilds which needs to be set
354 * before the start of the data transfer. All these feilds of CSU_DMA can be
355 * configured by using XCsuDma_SetConfig API.
358 u8 SssFifoThesh; /**< SSS FIFO threshold value */
359 u8 ApbErr; /**< ABP invalid access error */
360 u8 EndianType; /**< Type of endianess */
361 u8 AxiBurstType; /**< Type of AXI bus */
362 u32 TimeoutValue; /**< Time out value */
363 u8 FifoThresh; /**< FIFO threshold value */
364 u8 Acache; /**< AXI CACHE selection */
365 u8 RouteBit; /**< Selection of Route */
366 u8 TimeoutEn; /**< Enable of time out counters */
367 u16 TimeoutPre; /**< Pre scaler value */
368 u8 MaxOutCmds; /**< Maximum number of outstanding
372 /*****************************************************************************/
375 /************************** Function Prototypes ******************************/
377 XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
379 s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
381 void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
382 UINTPTR Addr, u32 Size, u8 EnDataLast);
383 void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
384 u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast);
385 void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
387 u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
388 u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
390 void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
391 XCsuDma_PauseType Type);
392 s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
393 XCsuDma_PauseType Type);
394 void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
395 XCsuDma_PauseType Type);
397 u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
398 void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
400 void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
401 XCsuDma_Configure *ConfigurValues);
402 void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
403 XCsuDma_Configure *ConfigurValues);
404 void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
406 void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
407 u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
409 /* Interrupt related APIs */
410 u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
411 void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
413 void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
415 void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
417 u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
419 s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
421 /******************************************************************************/
428 #endif /* End of protection macro */