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36 * @addtogroup emacps_v3_7
40 * The Xilinx Embedded Processor Block Ethernet driver.
42 * For a full description of XEMACPS features, please see the hardware spec.
43 * This driver supports the following features:
44 * - Memory mapped access to host interface registers
45 * - Statistics counter registers for RMON/MIB
46 * - API for interrupt driven frame transfers for hardware configured DMA
47 * - Virtual memory support
48 * - Unicast, broadcast, and multicast receive address filtering
49 * - Full and half duplex operation
50 * - Automatic PAD & FCS insertion and stripping
52 * - Support up to four 48bit addresses
53 * - Address checking for four specific 48bit addresses
54 * - VLAN frame support
55 * - Pause frame support
56 * - Large frame support up to 1536 bytes
59 * <b>Driver Description</b>
61 * The device driver enables higher layer software (e.g., an application) to
62 * communicate to the XEmacPs. The driver handles transmission and reception
63 * of Ethernet frames, as well as configuration and control. No pre or post
64 * processing of frame data is performed. The driver does not validate the
65 * contents of an incoming frame in addition to what has already occurred in
67 * A single device driver can support multiple devices even when those devices
68 * have significantly different configurations.
70 * <b>Initialization & Configuration</b>
72 * The XEmacPs_Config structure is used by the driver to configure itself.
73 * This configuration structure is typically created by the tool-chain based
74 * on hardware build properties.
76 * The driver instance can be initialized in
78 * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
79 * configuration structure provided by the caller. If running in a system
80 * with address translation, the provided virtual memory base address
81 * replaces the physical address present in the configuration structure.
83 * The device supports DMA only as current development plan. No FIFO mode is
84 * supported. The driver expects to start the DMA channels and expects that
85 * the user has set up the buffer descriptor lists.
87 * <b>Interrupts and Asynchronous Callbacks</b>
89 * The driver has no dependencies on the interrupt controller. When an
90 * interrupt occurs, the handler will perform a small amount of
91 * housekeeping work, determine the source of the interrupt, and call the
92 * appropriate callback function. All callbacks are registered by the user
95 * <b>Virtual Memory</b>
97 * All virtual to physical memory mappings must occur prior to accessing the
100 * For DMA transactions, user buffers supplied to the driver must be in terms
101 * of their physical address.
105 * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
106 * These BDs are typically chained together into a list the hardware follows
107 * when transferring data in and out of the packet buffers. Each BD describes
108 * a memory region containing either a full or partial Ethernet packet.
110 * Interrupt coalescing is not suppoted from this built-in DMA engine.
112 * This API requires the user to understand how the DMA operates. The
113 * following paragraphs provide some explanation, but the user is encouraged
114 * to read documentation in xemacps_bdring.h as well as study example code
115 * that accompanies this driver.
117 * The API is designed to get BDs to and from the DMA engine in the most
118 * efficient means possible. The first step is to establish a memory region
119 * to contain all BDs for a specific channel. This is done with
120 * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
121 * follow as BDs are processed. The ring will consist of a user defined number
122 * of BDs which will all be partially initialized. For example on the transmit
123 * channel, the driver will initialize all BDs' so that they are configured
124 * for transmit. The more fields that can be permanently setup at
125 * initialization, then the fewer accesses will be needed to each BD while
126 * the DMA engine is in operation resulting in better throughput and CPU
127 * utilization. The best case initialization would require the user to set
128 * only a frame buffer address and length prior to submitting the BD to the
131 * BDs move through the engine with the help of functions
132 * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
133 * and XEmacPs_BdRingFree().
134 * All these functions handle BDs that are in place. That is, there are no
135 * copies of BDs kept anywhere and any BD the user interacts with is an actual
136 * BD from the same ring hardware accesses.
138 * BDs in the ring go through a series of states as follows:
139 * 1. Idle. The driver controls BDs in this state.
140 * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
141 * reserve BD(s). Once allocated, the user may setup the BD(s) with
142 * frame buffer address, length, and other attributes. The user controls
144 * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
145 * in this state are either waiting to be processed by hardware, are in
146 * process, or have been processed. The DMA engine controls BDs in this
148 * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
149 * user. Once retrieved, the user can examine each BD for the outcome of
150 * the DMA transfer. The user controls BDs in this state. After examining
151 * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
154 * Each of the four BD accessor functions operate on a set of BDs. A set is
155 * defined as a segment of the BD ring consisting of one or more BDs. The user
156 * views the set as a pointer to the first BD along with the number of BDs for
157 * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
158 * user must exercise extreme caution when changing BDs in a set as there is
159 * nothing to prevent doing a mBdNext past the end of the set and modifying a
162 * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
163 * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
164 * tandem. The same BD set retrieved with BdRingAlloc should be the same one
165 * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
168 * <b>Alignment & Data Cache Restrictions</b>
170 * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
171 * aligned. Please reference xemacps_bd.h for cache related macros.
175 * - If frame buffers exist in cached memory, then they must be flushed
176 * prior to committing them to hardware.
180 * - If frame buffers exist in cached memory, then the cache must be
181 * invalidated for the memory region containing the frame prior to data
184 * Both cache invalidate/flush are taken care of in driver code.
186 * <b>Buffer Copying</b>
188 * The driver is designed for a zero-copy buffer scheme. That is, the driver
189 * will not copy buffers. This avoids potential throughput bottlenecks within
190 * the driver. If byte copying is required, then the transfer will take longer
193 * <b>Checksum Offloading</b>
195 * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
196 * and UDP checksum offloading in both receive and transmit directions.
198 * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
199 * complement of the 1s complement sum of all 16-bit words in the header.
200 * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
201 * 1s complement of the 1s complement sum of all 16-bit words in the header,
202 * the data and a conceptual pseudo header.
204 * To calculate these checksums in software requires each byte of the packet
205 * to be read. For TCP and UDP this can use a large amount of processing power.
206 * Offloading the checksum calculation to hardware can result in significant
207 * performance improvements.
209 * The transmit checksum offload is only available to use DMA in packet buffer
210 * mode. This is because the complete frame to be transmitted must be read
211 * into the packet buffer memory before the checksum can be calculated and
212 * written to the header at the beginning of the frame.
214 * For IP, TCP or UDP receive checksum offload to be useful, the operating
215 * system containing the protocol stack must be aware that this offload is
216 * available so that it can make use of the fact that the hardware has verified
219 * When receive checksum offloading is enabled in the hardware, the IP header
220 * checksum is checked, where the packet meets the following criteria:
222 * 1. If present, the VLAN header must be four octets long and the CFI bit
224 * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
227 * 4. IP header is of a valid length.
228 * 5. Good IP header checksum.
229 * 6. No IP fragmentation.
230 * 7. TCP or UDP packet.
232 * When an IP, TCP or UDP frame is received, the receive buffer descriptor
233 * gives an indication if the hardware was able to verify the checksums.
234 * There is also an indication if the frame had SNAP encapsulation. These
235 * indication bits will replace the type ID match indication bits when the
236 * receive checksum offload is enabled.
238 * If any of the checksums are verified incorrect by the hardware, the packet
239 * is discarded and the appropriate statistics counter incremented.
241 * <b>PHY Interfaces</b>
243 * RGMII 1.3 is the only interface supported.
247 * Asserts are used within all Xilinx drivers to enforce constraints on
248 * parameters. Asserts can be turned off on a system-wide basis by defining,
249 * at compile time, the NDEBUG identifier. By default, asserts are turned on
250 * and it is recommended that users leave asserts on during development. For
251 * deployment use -DNDEBUG compiler switch to remove assert code.
255 * Xilinx drivers are typically composed of two parts, one is the driver
256 * and the other is the adapter. The driver is independent of OS and processor
257 * and is intended to be highly portable. The adapter is OS-specific and
258 * facilitates communication between the driver and an OS.
259 * This driver is intended to be RTOS and processor independent. Any needs for
260 * dynamic memory management, threads or thread mutual exclusion, or cache
261 * control must be satisfied bythe layer above this driver.
264 * MODIFICATION HISTORY:
266 * Ver Who Date Changes
267 * ----- ---- -------- -------------------------------------------------------
268 * 1.00a wsy 01/10/10 First release
269 * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
270 * xemacps_bdring.c is modified. Earlier it was checking for
271 * "BdLimit"(passed argument) number of BDs for finding out
272 * which BDs are successfully processed. Now one more check
273 * is added. It looks for BDs till the current BD pointer
274 * reaches HwTail. By doing this processing time is saved.
275 * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
276 * xemacps_bdring.c is modified. Now start of packet is
277 * searched for returning the number of BDs processed.
278 * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
279 * registers. Added a new API to set the bust length.
280 * Added some new hash-defines.
281 * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
282 * Rx errors. Under heavy Rx traffic, there will be a large
283 * number of errors related to receive buffer not available.
284 * Because of a HW bug (SI #692601), under such heavy errors,
285 * the Rx data path can become unresponsive. To reduce the
286 * probabilities for hitting this HW bug, the SW writes to
287 * bit 18 to flush a packet from Rx DPRAM immediately. The
288 * changes for it are done in the function
289 * XEmacPs_IntrHandler.
290 * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
291 * removed. It is expected that all BDs are allocated in
292 * from uncached area.
293 * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
294 * to 0x1fff. This fixes the CR#744902.
295 * Made changes in example file xemacps_example.h to fix compilation
296 * issues with iarcc compiler.
297 * 2.0 adk 10/12/13 Updated as per the New Tcl API's
298 * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
299 * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
300 * address in xparameters.h when GMII to RGMII converter
302 * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
304 * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
305 * 1000BASE-X mode export proper values to the xparameters.h
306 * file. Changes are made in the driver tcl file.
307 * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
308 * configured with PCS/PMA Core. Changes are made in the
309 * test app tcl(CR:827686).
310 * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
311 * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
312 * Disable extended mode. Perform all 64 bit changes under
314 * Remove "used bit set" from TX error interrupt masks.
315 * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
316 * there is no error. CR# 869403
317 * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
318 * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
319 * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
320 * examples to ensure that "Successfully ran" and "Failed"
321 * strings are available in all examples. This is a fix
323 * ms 03/17/17 Modified text file in examples folder for doxygen
325 * ms 04/05/17 Added tabspace for return statements in functions of
326 * xemacps_ieee1588_example.c for proper documentation
327 * while generating doxygen.
328 * 3.5 hk 08/14/17 Update cache coherency information of the interface in
329 * its config structure.
330 * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
331 * changed to volatile.
332 * Add API XEmacPs_BdRingPtrReset() to reset pointers
336 ****************************************************************************/
338 #ifndef XEMACPS_H /* prevent circular inclusions */
339 #define XEMACPS_H /* by using protection macros */
345 /***************************** Include Files ********************************/
347 #include "xil_types.h"
348 #include "xil_assert.h"
350 #include "xemacps_hw.h"
351 #include "xemacps_bd.h"
352 #include "xemacps_bdring.h"
354 /************************** Constant Definitions ****************************/
359 #define XEMACPS_DEVICE_NAME "xemacps"
360 #define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
363 /** @name Configuration options
365 * Device configuration options. See the XEmacPs_SetOptions(),
366 * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
369 * The default state of the options are noted and are what the device and
370 * driver will be set to after calling XEmacPs_Reset() or
371 * XEmacPs_Initialize().
376 #define XEMACPS_PROMISC_OPTION 0x00000001U
377 /**< Accept all incoming packets.
378 * This option defaults to disabled (cleared) */
380 #define XEMACPS_FRAME1536_OPTION 0x00000002U
381 /**< Frame larger than 1516 support for Tx & Rx.
382 * This option defaults to disabled (cleared) */
384 #define XEMACPS_VLAN_OPTION 0x00000004U
385 /**< VLAN Rx & Tx frame support.
386 * This option defaults to disabled (cleared) */
388 #define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
389 /**< Enable recognition of flow control frames on Rx
390 * This option defaults to enabled (set) */
392 #define XEMACPS_FCS_STRIP_OPTION 0x00000020U
393 /**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
395 * This option defaults to enabled (set) */
397 #define XEMACPS_FCS_INSERT_OPTION 0x00000040U
398 /**< Generate FCS field and add PAD automatically for outgoing frames.
399 * This option defaults to disabled (cleared) */
401 #define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
402 /**< Enable Length/Type error checking for incoming frames. When this option is
403 * set, the MAC will filter frames that have a mismatched type/length field
404 * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
405 * types of frames are encountered. When this option is cleared, the MAC will
406 * allow these types of frames to be received.
408 * This option defaults to disabled (cleared) */
410 #define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
411 /**< Enable the transmitter.
412 * This option defaults to enabled (set) */
414 #define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
415 /**< Enable the receiver
416 * This option defaults to enabled (set) */
418 #define XEMACPS_BROADCAST_OPTION 0x00000400U
419 /**< Allow reception of the broadcast address
420 * This option defaults to enabled (set) */
422 #define XEMACPS_MULTICAST_OPTION 0x00000800U
423 /**< Allows reception of multicast addresses programmed into hash
424 * This option defaults to disabled (clear) */
426 #define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
427 /**< Enable the RX checksum offload
428 * This option defaults to enabled (set) */
430 #define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
431 /**< Enable the TX checksum offload
432 * This option defaults to enabled (set) */
434 #define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
435 #define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
437 #define XEMACPS_DEFAULT_OPTIONS \
438 ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
439 (u32)XEMACPS_FCS_INSERT_OPTION | \
440 (u32)XEMACPS_FCS_STRIP_OPTION | \
441 (u32)XEMACPS_BROADCAST_OPTION | \
442 (u32)XEMACPS_LENTYPE_ERR_OPTION | \
443 (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
444 (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
445 (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
446 (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
448 /**< Default options set when device is initialized or reset */
451 /** @name Callback identifiers
453 * These constants are used as parameters to XEmacPs_SetHandler()
456 #define XEMACPS_HANDLER_DMASEND 1U
457 #define XEMACPS_HANDLER_DMARECV 2U
458 #define XEMACPS_HANDLER_ERROR 3U
461 /* Constants to determine the configuration of the hardware device. They are
462 * used to allow the driver to verify it can operate with the hardware.
464 #define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
466 /* The next few constants help upper layers determine the size of memory
467 * pools used for Ethernet buffers and descriptor lists.
469 #define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
471 #define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
472 #define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
473 #define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
474 #define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
475 #define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
476 #define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
478 #define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
479 XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
480 #define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
481 XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
483 /* DMACR Bust length hash defines */
485 #define XEMACPS_SINGLE_BURST 0x00000001
486 #define XEMACPS_4BYTE_BURST 0x00000004
487 #define XEMACPS_8BYTE_BURST 0x00000008
488 #define XEMACPS_16BYTE_BURST 0x00000010
491 /**************************** Type Definitions ******************************/
492 /** @name Typedefs for callback functions
494 * These callbacks are invoked in interrupt context.
498 * Callback invoked when frame(s) have been sent or received in interrupt
499 * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
501 * @param CallBackRef is user data assigned when the callback was set.
504 * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
505 * further information on their meaning.
508 typedef void (*XEmacPs_Handler) (void *CallBackRef);
511 * Callback when an asynchronous error occurs. To set this callback, invoke
512 * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
515 * @param CallBackRef is user data assigned when the callback was set.
516 * @param Direction defines either receive or transmit error(s) has occurred.
517 * @param ErrorWord definition varies with Direction
520 typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
526 * This typedef contains configuration information for a device.
529 u16 DeviceId; /**< Unique ID of device */
530 UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
531 u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
532 * describes whether Cache Coherent or not */
537 * The XEmacPs driver instance data. The user is required to allocate a
538 * structure of this type for every XEmacPs device in the system. A pointer
539 * to a structure of this type is then passed to the driver API functions.
541 typedef struct XEmacPs_Instance {
542 XEmacPs_Config Config; /* Hardware configuration */
543 u32 IsStarted; /* Device is currently started */
544 u32 IsReady; /* Device is initialized and ready */
545 u32 Options; /* Current options word */
547 XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
548 XEmacPs_BdRing RxBdRing; /* Receive BD ring */
550 XEmacPs_Handler SendHandler;
551 XEmacPs_Handler RecvHandler;
555 XEmacPs_ErrHandler ErrorHandler;
561 u32 MaxVlanFrameSize;
566 /***************** Macros (Inline Functions) Definitions ********************/
568 /****************************************************************************/
570 * Retrieve the Tx ring object. This object can be used in the various Ring
573 * @param InstancePtr is the DMA channel to operate on.
575 * @return TxBdRing attribute
579 * XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
581 *****************************************************************************/
582 #define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
584 /****************************************************************************/
586 * Retrieve the Rx ring object. This object can be used in the various Ring
589 * @param InstancePtr is the DMA channel to operate on.
591 * @return RxBdRing attribute
595 * XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
597 *****************************************************************************/
598 #define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
600 /****************************************************************************/
603 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
604 * each bit set to 1 in <i>Mask</i>, will be enabled.
606 * @param InstancePtr is a pointer to the instance to be worked on.
607 * @param Mask contains a bit mask of interrupts to enable. The mask can
608 * be formed using a set of bitwise or'd values.
611 * The state of the transmitter and receiver are not modified by this function.
613 * void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
615 *****************************************************************************/
616 #define XEmacPs_IntEnable(InstancePtr, Mask) \
617 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
618 XEMACPS_IER_OFFSET, \
619 ((Mask) & XEMACPS_IXR_ALL_MASK));
621 /****************************************************************************/
624 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
625 * each bit set to 1 in <i>Mask</i>, will be enabled.
627 * @param InstancePtr is a pointer to the instance to be worked on.
628 * @param Mask contains a bit mask of interrupts to disable. The mask can
629 * be formed using a set of bitwise or'd values.
632 * The state of the transmitter and receiver are not modified by this function.
634 * void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
636 *****************************************************************************/
637 #define XEmacPs_IntDisable(InstancePtr, Mask) \
638 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
639 XEMACPS_IDR_OFFSET, \
640 ((Mask) & XEMACPS_IXR_ALL_MASK));
642 /****************************************************************************/
645 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
646 * each bit set to 1 in <i>Mask</i>, will be enabled.
648 * @param InstancePtr is a pointer to the instance to be worked on.
649 * @param Mask contains a bit mask of interrupts to enable. The mask can
650 * be formed using a set of bitwise or'd values.
653 * The state of the transmitter and receiver are not modified by this function.
655 * void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
657 *****************************************************************************/
658 #define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
659 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
660 XEMACPS_INTQ1_IER_OFFSET, \
661 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
663 /****************************************************************************/
666 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
667 * each bit set to 1 in <i>Mask</i>, will be enabled.
669 * @param InstancePtr is a pointer to the instance to be worked on.
670 * @param Mask contains a bit mask of interrupts to disable. The mask can
671 * be formed using a set of bitwise or'd values.
674 * The state of the transmitter and receiver are not modified by this function.
676 * void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
678 *****************************************************************************/
679 #define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
680 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
681 XEMACPS_INTQ1_IDR_OFFSET, \
682 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
684 /****************************************************************************/
687 * This macro triggers trasmit circuit to send data currently in TX buffer(s).
689 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
695 * Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
697 *****************************************************************************/
698 #define XEmacPs_Transmit(InstancePtr) \
699 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
700 XEMACPS_NWCTRL_OFFSET, \
701 (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
702 XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
704 /****************************************************************************/
707 * This macro determines if the device is configured with checksum offloading
708 * on the receive channel
710 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
714 * Boolean TRUE if the device is configured with checksum offloading, or
719 * Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
721 *****************************************************************************/
722 #define XEmacPs_IsRxCsum(InstancePtr) \
723 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
724 XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
727 /****************************************************************************/
730 * This macro determines if the device is configured with checksum offloading
731 * on the transmit channel
733 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
737 * Boolean TRUE if the device is configured with checksum offloading, or
742 * Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
744 *****************************************************************************/
745 #define XEmacPs_IsTxCsum(InstancePtr) \
746 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
747 XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
750 /************************** Function Prototypes *****************************/
753 * Initialization functions in xemacps.c
755 LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
756 UINTPTR EffectiveAddress);
757 void XEmacPs_Start(XEmacPs *InstancePtr);
758 void XEmacPs_Stop(XEmacPs *InstancePtr);
759 void XEmacPs_Reset(XEmacPs *InstancePtr);
760 void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
764 * Lookup configuration in xemacps_sinit.c
766 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
769 * Interrupt-related functions in xemacps_intr.c
770 * DMA only and FIFO is not supported. This DMA does not support coalescing.
772 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
773 void *FuncPointer, void *CallBackRef);
774 void XEmacPs_IntrHandler(void *XEmacPsPtr);
777 * MAC configuration/control functions in XEmacPs_control.c
779 LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
780 LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
781 u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
783 LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
784 LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
785 void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
787 LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
788 void XEmacPs_ClearHash(XEmacPs *InstancePtr);
789 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
791 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
792 XEmacPs_MdcDiv Divisor);
793 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
794 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
795 LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
796 u32 RegisterNum, u16 *PhyDataPtr);
797 LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
798 u32 RegisterNum, u16 PhyData);
799 LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
801 LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
802 void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
808 #endif /* end of protection macro */