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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
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   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
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  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xgpiops_hw.c
  36 * @addtogroup gpiops_v3_1
  37 * @{
  38 *
  39 * This file contains low level GPIO functions.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who  Date     Changes
  45 * ----- ---- -------- -----------------------------------------------
  46 * 1.02a hk   08/22/13 First Release
  47 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
  48 * 3.1   kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
  49 *
  50 * </pre>
  51 *
  52 ******************************************************************************/
  53
  54 /***************************** Include Files *********************************/
  55
  56 #include "xgpiops_hw.h"
  57 #include "xgpiops.h"
  58
  59 /************************** Constant Definitions *****************************/
  60
  61 /**************************** Type Definitions *******************************/
  62
  63 /***************** Macros (Inline Functions) Definitions *********************/
  64
  65 /************************** Variable Definitions *****************************/
  66
  67 /************************** Function Prototypes ******************************/
  68
  69
  70 /*****************************************************************************/
  71 /*
  72 *
  73 * This function resets the GPIO module by writing reset values to
  74 * all registers
  75 *
  76 * @param        Base address of GPIO module
  77 *
  78 * @return       None
  79 *
  80 * @note         None.
  81 *
  82 ******************************************************************************/
  83 void XGpioPs_ResetHw(u32 BaseAddress)
  84 {
  85         u32 BankCount;
  86         u32 Platform,MaxBanks;
  87
  88         Platform = XGetPlatform_Info();
  89         if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
  90                 MaxBanks = (u32)6;
  91         } else {
  92                 MaxBanks = (u32)4;
  93         }
  94         /* Write reset values to all mask data registers */
  95         for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
  96
  97                 XGpioPs_WriteReg(BaseAddress,
  98                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
  99                                  XGPIOPS_DATA_LSW_OFFSET), 0x0U);
 100                 XGpioPs_WriteReg(BaseAddress,
 101                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
 102                                  XGPIOPS_DATA_MSW_OFFSET), 0x0U);
 103         }
 104         /* Write reset values to all output data registers */
 105         for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
 106
 107                 XGpioPs_WriteReg(BaseAddress,
 108                                 ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
 109                                  XGPIOPS_DATA_OFFSET), 0x0U);
 110         }
 111
 112         /* Reset all registers of all GPIO banks */
 113         for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
 114
 115                 XGpioPs_WriteReg(BaseAddress,
 116                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 117                                  XGPIOPS_DIRM_OFFSET), 0x0U);
 118                 XGpioPs_WriteReg(BaseAddress,
 119                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 120                                  XGPIOPS_OUTEN_OFFSET), 0x0U);
 121                 XGpioPs_WriteReg(BaseAddress,
 122                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 123                                  XGPIOPS_INTMASK_OFFSET), 0x0U);
 124                 XGpioPs_WriteReg(BaseAddress,
 125                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 126                                  XGPIOPS_INTEN_OFFSET), 0x0U);
 127                 XGpioPs_WriteReg(BaseAddress,
 128                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 129                                  XGPIOPS_INTDIS_OFFSET), 0x0U);
 130                 XGpioPs_WriteReg(BaseAddress,
 131                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 132                                  XGPIOPS_INTSTS_OFFSET), 0x0U);
 133                 XGpioPs_WriteReg(BaseAddress,
 134                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 135                                  XGPIOPS_INTPOL_OFFSET), 0x0U);
 136                 XGpioPs_WriteReg(BaseAddress,
 137                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 138                                  XGPIOPS_INTANY_OFFSET), 0x0U);
 139         }
 140
 141         /* Bank 0 Int type */
 142         XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
 143                         XGPIOPS_INTTYPE_BANK0_RESET);
 144         /* Bank 1 Int type */
 145         XGpioPs_WriteReg(BaseAddress,
 146                         ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
 147                         XGPIOPS_INTTYPE_BANK1_RESET);
 148         /* Bank 2 Int type */
 149         XGpioPs_WriteReg(BaseAddress,
 150                         (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 151                         XGPIOPS_INTTYPE_BANK2_RESET);
 152         /* Bank 3 Int type */
 153         XGpioPs_WriteReg(BaseAddress,
 154                         (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 155                         XGPIOPS_INTTYPE_BANK3_RESET);
 156
 157         if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
 158                 /* Bank 4 Int type */
 159                 XGpioPs_WriteReg(BaseAddress,
 160                                 (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 161                                 XGPIOPS_INTTYPE_BANK4_RESET);
 162                 /* Bank 5 Int type */
 163                 XGpioPs_WriteReg(BaseAddress,
 164                                 (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 165                                 XGPIOPS_INTTYPE_BANK5_RESET);
 166         }
 167
 168 }
 169 /** @} */