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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v3_3
39 * This file contains low level GPIO functions.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ---- -------- -----------------------------------------------
46 * 1.02a hk 08/22/13 First Release
47 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
48 * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
52 ******************************************************************************/
54 /***************************** Include Files *********************************/
56 #include "xgpiops_hw.h"
59 /************************** Constant Definitions *****************************/
61 /**************************** Type Definitions *******************************/
63 /***************** Macros (Inline Functions) Definitions *********************/
65 /************************** Variable Definitions *****************************/
67 /************************** Function Prototypes ******************************/
70 /*****************************************************************************/
73 * This function resets the GPIO module by writing reset values to
76 * @param Base address of GPIO module
82 ******************************************************************************/
83 void XGpioPs_ResetHw(u32 BaseAddress)
86 u32 Platform,MaxBanks;
88 Platform = XGetPlatform_Info();
89 if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
94 /* Write reset values to all mask data registers */
95 for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
97 XGpioPs_WriteReg(BaseAddress,
98 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
99 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
100 XGpioPs_WriteReg(BaseAddress,
101 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
102 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
104 /* Write reset values to all output data registers */
105 for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
107 XGpioPs_WriteReg(BaseAddress,
108 ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
109 XGPIOPS_DATA_OFFSET), 0x0U);
112 /* Reset all registers of all GPIO banks */
113 for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
115 XGpioPs_WriteReg(BaseAddress,
116 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
117 XGPIOPS_DIRM_OFFSET), 0x0U);
118 XGpioPs_WriteReg(BaseAddress,
119 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
120 XGPIOPS_OUTEN_OFFSET), 0x0U);
121 XGpioPs_WriteReg(BaseAddress,
122 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
123 XGPIOPS_INTMASK_OFFSET), 0x0U);
124 XGpioPs_WriteReg(BaseAddress,
125 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
126 XGPIOPS_INTEN_OFFSET), 0x0U);
127 XGpioPs_WriteReg(BaseAddress,
128 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
129 XGPIOPS_INTDIS_OFFSET), 0x0U);
130 XGpioPs_WriteReg(BaseAddress,
131 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
132 XGPIOPS_INTSTS_OFFSET), 0x0U);
133 XGpioPs_WriteReg(BaseAddress,
134 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
135 XGPIOPS_INTPOL_OFFSET), 0x0U);
136 XGpioPs_WriteReg(BaseAddress,
137 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
138 XGPIOPS_INTANY_OFFSET), 0x0U);
141 /* Bank 0 Int type */
142 XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
143 XGPIOPS_INTTYPE_BANK0_RESET);
144 /* Bank 1 Int type */
145 XGpioPs_WriteReg(BaseAddress,
146 ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
147 XGPIOPS_INTTYPE_BANK1_RESET);
148 /* Bank 2 Int type */
149 XGpioPs_WriteReg(BaseAddress,
150 (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
151 XGPIOPS_INTTYPE_BANK2_RESET);
152 /* Bank 3 Int type */
153 XGpioPs_WriteReg(BaseAddress,
154 (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
155 XGPIOPS_INTTYPE_BANK3_RESET);
157 if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
158 /* Bank 4 Int type */
159 XGpioPs_WriteReg(BaseAddress,
160 (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
161 XGPIOPS_INTTYPE_BANK4_RESET);
162 /* Bank 5 Int type */
163 XGpioPs_WriteReg(BaseAddress,
164 (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
165 XGPIOPS_INTTYPE_BANK5_RESET);