git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************
  33 *
  34 * @file sleep.c
  35 *
  36 * This function provides a second delay using the Global Timer register in
  37 * the ARM Cortex R5 MP core.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who      Date     Changes
  43 * ----- -------- -------- -----------------------------------------------
  44 * 5.00  pkp      02/20/14 First release
  45 * 5.04  pkp              02/19/16 sleep routine is modified to use TTC3 if present
  46 *                                                 else it will use set of assembly instructions to
  47 *                                                 provide the required delay
  48 * 5.04  pkp              03/09/16 Assembly routine for sleep is modified to avoid
  49 *                                                 disabling the interrupt
  50 * 5.04  pkp              03/11/16 Compare the counter value to previously read value
  51 *                                                 to detect the overflow for TTC3
  52 * 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
  53 * </pre>
  54 *
  55 ******************************************************************************/
  56 /***************************** Include Files *********************************/
  57
  58 #include "sleep.h"
  59 #include "xtime_l.h"
  60 #include "xparameters.h"
  61
  62 /*****************************************************************************/
  63 /*
  64 *
  65 * This API is used to provide delays in seconds.
  66 *
  67 * @param        seconds requested
  68 *
  69 * @return       0 always
  70 *
  71 * @note         The sleep API is implemented using TTC3 counter 0 timer if present.
  72 *                       When TTC3 is absent, sleep is implemented using assembly
  73 *                       instructions which is tested with instruction and data caches
  74 *                       enabled and it gives proper delay. It may give more delay than
  75 *                       exepcted when caches are disabled. If interrupt comes when sleep
  76 *                       using assembly instruction is being executed, the delay may be
  77 *                       greater than what is expected since once the interrupt is served
  78 *                       count resumes from where it was interrupted unlike the case of TTC3
  79 *                       where counter keeps running while interrupt is being served.
  80 *
  81 ****************************************************************************/
  82
  83 unsigned sleep(unsigned int seconds)
  84 {
  85 #ifdef SLEEP_TIMER_BASEADDR
  86         u64 tEnd;
  87         u64 tCur;
  88         u32 TimeHighVal;
  89         XTime TimeLowVal1;
  90         XTime TimeLowVal2;
  91
  92         TimeHighVal = 0;
  93
  94         XTime_GetTime(&TimeLowVal1);
  95         tEnd  = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND);
  96
  97         do
  98         {
  99
 100             XTime_GetTime(&TimeLowVal2);
 101             if (TimeLowVal2 < TimeLowVal1) {
 102                                 TimeHighVal++;
 103                 }
 104
 105                 TimeLowVal1 = TimeLowVal2;
 106             tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
 107
 108         } while (tCur < tEnd);
 109
 110         return 0;
 111 #else
 112         __asm__ __volatile__ (
 113                         " push {r0,r1}          \n\t"
 114                         " mov r0, %[sec]        \n\t"
 115                         " 1: \n\t"
 116                         " mov r1, %[iter]       \n\t"
 117                         " 2:                            \n\t"
 118                         " subs r1, r1, #0x1 \n\t"
 119                         " bne   2b              \n\t"
 120                         " subs r0,r0,#0x1       \n\t"
 121                         "  bne 1b                       \n\t"
 122                         " pop {r0,r1}           \n\t"
 123                         :: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
 124         );
 125 #endif
 126 }