1 /*****************************************************************************
2 * MODIFICATION HISTORY:
5 * ----- ---- -------- ---------------------------------------------------
6 * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
7 * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
8 * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
10 * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
11 * generated by the cpu driver, for enabling caches
12 * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
14 * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
15 * Updated the MMU table to mark OCM in high address space
16 * as inner cacheable and reserved space as Invalid
17 * 3.03a sdm 08/20/11 Changes to support FreeRTOS
18 * Updated the MMU table to mark upper half of the DDR as
20 * Setup supervisor and abort mode stacks
21 * Do not initialize/enable L2CC in case of AMP
22 * Initialize UART1 for 9600bps in case of AMP
23 * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
25 * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
27 * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
28 * xparameters.h file for CR630532 - Xil_DCacheFlush()/
29 * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
30 * for MicroBlaze will invalidate data in the cache instead
31 * of flushing it for writeback caches
32 * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
33 * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
34 * Remove redundant dsb/dmb instructions in cache maintenance
36 * Remove redundant dsb in mcr instruction
37 * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
38 * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
39 * driver tcl in xparameters.h. Update the gcc/translationtable.s
40 * for the QSPI complete address range - DT644567
41 * Removed profile directory for armcc compiler and changed
42 * profiling setting to false in standalone_v2_1_0.tcl file
43 * Deleting boot.S file after preprocessing for armcc compiler
44 * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
45 * invalidate the caches before enabling back the MMU and
47 * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
48 * xil_mmu.c. Now we invalidate UTLB, Branch predictor
49 * array, flush the D-cache before changing the attributes
50 * in translation table. The user need not call Xil_DisableMMU
51 * before calling Xil_SetTlbAttributes.
52 * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
53 * sgd initialization is present. Changes for this were done in
54 * uart.c and xil-crt0.s.
55 * Made changes in xil_io.c to use volatile pointers.
56 * Made changes in xil_mmu.c to correct the function
57 * Xil_SetTlbAttributes.
58 * Changes are made xil-crt0.s to initialize the static
60 * Changes are made in boot.s, to fix the TTBR settings,
61 * correct the L2 Cache Auxiliary register settings, L2 cache
63 * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
64 * sgd usleep.c to use global timer intstead of CP15.
65 * Made changes in cortexa9/gcc/translation_table.s to map
66 * the peripheral devices as shareable device memory.
67 * Made changes in cortexa9/gcc/xil-crt0.s to initialize
69 * Made changes in cortexa9/armcc/boot.S to initialize
71 * Made changes in cortexa9/armcc/translation_table.s to
72 * map the peripheral devices as shareable device memory.
73 * Made changes in cortexa9/gcc/boot.S to optimize the
74 * L2 cache settings. Changes the section properties for
75 * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
76 * and cortexa9/gcc/translation_table.S.
77 * Made changes in cortexa9/xil_cache.c to change the
78 * cache invalidation order.
79 * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
80 * compilation/linking issues for C++ compiler.
81 * Made changes in mb_interface.h to remove compilation/
82 * linking issues for C++ compiler.
83 * Added macros for swapb and swaph microblaze instructions
85 * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
87 * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
88 * 3.07a asa 08/31/12 Added xil_printf.h include
89 * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
90 * Corrected L2 cache sequence disable sequence
91 * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
92 * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
94 * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
95 * fixes the CR #692094.
96 * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
97 * 3.10a srt 04/18/13 Implemented ARM Erratas.
98 * Cortex A9 Errata - 742230, 743622, 775420, 794073
99 * L2Cache PL310 Errata - 588369, 727915, 759370
100 * Please refer to file 'xil_errata.h' for errata
102 * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
103 * cache APIs were corresponding to only Layer 1 cache
104 * memories. New APIs were now added and the existing cache
105 * related APIs were changed to provide a uniform interface
106 * to flush/invalidate/enable/disable the complete cache
107 * system which includes both L1 and L2 caches. The changes
108 * for these were done in:
109 * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
111 * Four new files were added for supporting L2 cache. They are:
112 * microblaze_flush_cache_ext.S-> Flushes L2 cache
113 * microblaze_flush_cache_ext_range.S -> Flushes a range of
114 * memory in L2 cache.
115 * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
116 * microblaze_invalidate_cache_ext_range -> Invalidates a
117 * range of memory in L2 cache.
118 * These changes are done to implement PR #697214.
119 * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
120 * fix the CR #706464. L2 cache disabling happens independent
121 * of L1 data cache disable operation. Changes are done in the
122 * same file in cache handling APIs to do a L2 cache sync
123 * (poll reg7_?cache_?sync). This fixes CR #700542.
124 * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
125 * interrupts for ARM. These are done to fix the CR#699680.
126 * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
127 * sync operation. This fixes the CR# 716781.
128 * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
129 * for armcc toolchain.
130 * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
131 * fix issues related to NEON context saving. The assembly
132 * routines for IRQ and FIQ handling are modified.
133 * Deprecated the older BSP (3.10a).
134 * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
135 * various potential issues. Made changes in the function
136 * Xil_SetAttributes in file xil_mmu.c.
137 * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
138 * in src\cortexa9 and src\microblaze folders.
139 * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
140 * L2 cache sync operation and to fix issues around complete
141 * L2 cache flush/invalidation by ways.
142 * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
143 * to fix linking issues with armcc/DS-5. Modified the armcc
144 * makefile to fix issues.
145 * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
146 * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
147 * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
148 * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
149 * src\cortexa9\armcc\) to fix CR#767251
150 * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
151 * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
152 * Few cache lines were missed to invalidate when unaligned address
153 * invalidation was accommodated in Xil_DCacheInvalidateRange.
154 * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
155 * stack memory (which contains return address) was invalidated. So
156 * stack memory is flushed first and then L1D cache is invalidated.
157 * This is done to fix CR #763829
158 * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
159 * mblaze_nt_types.h file and replace uint32_t with u32 in the
160 * profile_hist.c to fix the above CR.
161 * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
162 * instead of libxil.a and added prototypes for
163 * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
165 * 4.1 hk 04/18/14 Add sleep function.
166 * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
167 * some of the *.s files inMB BSP source to *.S.
168 * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
169 * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
171 * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
172 * common/xil_testcache.c
174 * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
175 * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
176 * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
177 * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
178 * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
179 * cortexa9/armcc/boot.s. Added default exception handlers for data
180 * abort and prefetch abort using handlers called
181 * DataAbortHandler and PrefetchAbortHandler respectively in
182 * cortexa9/xil_exception.c to fix CR#802862.
183 * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
184 * issue of improper linking of translation_table.s
185 * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
186 * in tool chain to avoid conflicts into some special cases
187 * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
188 * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
189 * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
190 * containing type def u32 defined in xil_types.g to resolve issue of
192 * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
193 * it is not possible to generate timer in nanosecond due to limited
195 * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
196 * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
197 * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
198 * removed function definition of XSmc_NorInit and XSmc_NorInit from
200 * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
201 * cache_ext_range declarations in mb_interface.h CR#783821.
202 * Modified profile_mcount_mb.S to fix CR#808412.
203 * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
204 * cortexa9/iccarm to fix CR#816701
205 * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
206 * armcc/translation_table.s and iccarm/translation_table.s
207 * to properly defined reserved entries according to address map for
209 * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
210 * and cortexa9/armcc/translation_table.s to resolve compilation
211 * error for solving CR#822897
212 * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
213 * MISRA-C:2012 compliance.
214 * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
215 * adding src/common/xplatform_info.*s
216 * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
217 * removed incorrect initialization of TLB lockdown register to fix
218 * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
220 * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
221 * for iccarm and armcc compiler of cortexA9
222 * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
223 * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
224 * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
225 * of L2Cache is done later.
226 * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
227 * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
228 * taking long time to fix CR#853097. L2CacheSync is added into
229 * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
230 * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
231 * instead of just System Stack
232 * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
233 * to update ECC_FLAGS and also take the compiler and archiver as specified
234 * in settings instead of hardcoding it.
235 * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
236 * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
237 * accordingly generate the translation table
238 * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
239 * to update ECC_FLAGS to fix a bug introduced during new version creation
241 * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
242 * functionalities are avoided for the OpenAMP slave application(when
243 * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
244 * cache for its operation. Also file operations such as read, write,
245 * close, open are also avoided for OpenAMP support(when USE_AMP flag is
246 * defined for BSP) because XilOpenAMP library contains own file operation.
247 * The xil-crt0.S file is modified for not initializing global timer for
248 * OpenAMP application as it might be already in use by master CPU
249 * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
250 * definition for dsb, isb and dmb to fix the compilation error when used
251 * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
252 * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
253 * R5 deadlock for errata 780125
254 * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
255 * 32 bit BSP in the initialization
256 * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
257 * for XOcm_Remap function
258 * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
259 * for XOcm_Remap function
260 * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
261 * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
262 * required for MISRA-C:2012 Compliance.
263 * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
264 * in cortexa9/xil_mmu.h
265 * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
266 * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
267 * checking the current executing platform
268 * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
269 * to initialize global constructor for C++ applications
270 * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
272 * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
273 * translation_table.S to update the translation table according to proper
275 * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
277 * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
278 * equivalent to vector table base address
279 * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
280 * as per the toolchain update
281 * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
282 * for Cortex-A53 32bit mode
283 * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
284 * and usleep.c to correct routines to avoid hardcoding the timer frequency,
285 * instead take it from xparameters.h to properly configure the timestamp
287 * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
288 * new instructions for MB address extension feature
289 * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
291 * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
292 * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
293 * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
294 * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
295 * use set of assembly instructions to provide required delay to fix
297 * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
298 * _exit with exit. We should not be directly calling _exit and should
299 * always use the library exit. This fixes the CR#937036.
300 * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
301 * registers, banked registers for various modes and enabled
302 * the cache ECC check before enabling the fault log for lock step mode
303 * Also modified the cortexr5/gcc/Makefile to support floating point
304 * registers initialization in boot code.
305 * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
306 * logic in case of lock-step mode when fault log is enabled to fix
308 * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
309 * header file instrinsics.h which contains assembly instructions
310 * definitions which can be used by C
311 * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
312 * proto for all print.c across the BSPs. This patch fixes CR#938738.
313 * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
314 * interrupts when sleep/usleep is being executed using assembly
315 * instructions to fix CR#913249.
316 * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
317 * instead modified cortexr5/sleep.c and usleep.c to poll the counter
318 * value and compare it with previous value to detect the overflow
320 * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
321 * the fault log to avoid intervention for lock-step mode and cortexr5/
322 * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
324 * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
325 * in lock-step to avoid resetting the debug logic which restricts the
326 * access for debugger and removed enabling back of debug modules in
328 * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
329 * read buffer is filled and removed the redundant NULL checking for
330 * buffer to simplify the code
331 * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
332 * to return correct number of bytes when read buffer is filled and
333 * removed the redundant NULL checking for buffer to simplify the code
334 * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
335 * read buffer is filled and removed the redundant NULL checking for
336 * buffer to simplify the code
337 * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
338 * instruction macros to disable certain optimizations which may move
339 * code out of loops if optimizers believe that the code will always
340 * return the same result or discard asm statements if optimizers
341 * determine there is no need for the output variables
342 * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
343 * starts the timer if it is disabled and modified XTime_GetTime to
344 * enable the timer if it is not enabled. Also modified cortexa53/64bit/
345 * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
346 * disabled and read the counter value directly from register instead
347 * of using XTime_GetTime for optimization
348 * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
349 * starts the timer if it is disabled and modified XTime_GetTime to
350 * enable the timer if it is not enabled. Also modified cortexa53/32bit/
351 * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
352 * disabled and read the counter value directly from register instead
353 * of using XTime_GetTime for optimization
354 * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
355 * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
356 * Xil_DCacheInvalidateRange functions description for proper
357 * explaination to fix CR#949801
358 * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
359 * file mb_interface.h. This fixes the CR#949503.
360 * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
361 * memory is not included for MicroBlaze.
362 * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
363 * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
364 * the issue of lr being corrupted to resolve CR#950468
365 * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
366 * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
367 * the issue of lr being corrupted to resolve CR#950468
368 * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
369 * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
370 * section since it is part of boot process to fix CR#949555
371 * hk 07/12/16 Correct masks for IOU SLCR GEM registers
372 * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
373 * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
374 * the accuracy of MB sleep functionality. This fixes the CR#954191.
375 * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
376 * Source code directories specific to ARM processor's are moved to src/arm
377 * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
378 * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
379 * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
380 * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
381 * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
382 * into common file each and consolidated files are kept at src/arm/common directory.
383 * GCC source files related to file operations are consolidated and kept
384 * at src/arm/common/gcc directory.
385 * All io interfacing functions (i.e. All variants of xil_out, xil_in )
386 * are made as static inline and implementation is kept in consolidated common/xil_io.h,
387 * xil_io.h must be included as a header file to access io interfacing functions.
388 * Added undefined exception handler for A53 32 bit and R5 processor
389 * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
390 * TTC counter value register is read only.
391 * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
393 * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
394 * in cortexr5/xparameters_ps.h
395 * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
396 * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
397 * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
398 * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
399 * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
400 * these APIs and modifications are done on top of it to handle stdout/stdin
401 * parameters for design which doesnt have UART.It fixes CR#953681
402 * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
403 * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
404 * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
405 * and rest of the memory in that 32GB region is marked as reserved to avoid
406 * any speculative access
407 * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
408 * asm_vectors.S to implement lazy floating point context saving i.e. floating point
409 * access is enabled if there is any floating point operation, it is disabled by
410 * default. Also FPU is initally disabled for IRQ and none of the floating point
411 * registers are saved during normal context saving. If IRQ handler does not require
412 * floating point operation, the floating point registers are untouched and no need
413 * for saving/restoring. If IRQ handler uses any floating point operation, then floating
414 * point registers are saved and FPU is enabled for IRQ handler. Then floating point
415 * registers are restored back after servicing IRQ during normal context restoring.
416 * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
417 * target.It fixes the CR#966900
418 * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
419 * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
420 * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
421 * as false i.e. default bsp is EL3.
422 * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
423 * contains initial status of FPU i.e. disabled. In case of a warm restart execution
424 * when bss sections are not cleared, it may contain previously updated value which
425 * does not hold true once processor resumes. This fixes CR#966826.
426 * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
427 * D caches and then disables it. The problem with that is,
428 * potentially there will be a small window after the cache
429 * flush operation and before the we disable D caches where
430 * we might have valid data in cache lines. In such a
431 * scenario disabling the D cache can lead to unknown behavior.
432 * The ideal solution to this is to use assembly code for
433 * the complete API and avoid any memory accesses. But with
434 * that we will end up having a huge amount on assembly code
435 * which is not maintainable. Changes are done to use a mix
436 * of assembly and C code. All local variables are put in
437 * registers. Also function calls are avoided in the API to
438 * avoid using stack memory.
439 * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
440 * scenarios when an invalidated cache line can get pre fetched to cache.
441 * If that happens, the coherency between cache and memory is lost
442 * resulting in lost data. To avoid this kind of issue either
443 * user has to use dsb() or disable pre-fetching for L1 cache
444 * or else reduce maximum number of outstanding data prefetches allowed.
445 * Using dsb() while comparing data costing more performance compared to
446 * disabling pre-fetching/reducing maximum number of outstanding data
447 * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
448 * to disable pre-fetching/configure maximum number of outstanding data
449 * prefetches allowed in L1 cache system.This fixes CR#967864.
450 * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
451 * used by cortex-A53 64bit EL1 Non-secure application.
452 * 6.2 kvn 03/03/17 Added support thumb mode
453 * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
455 * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
456 * profiling we see a crash. That is because the the tcl uses invalid
457 * HSI command. This change fixes it.
458 * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
459 * any FPD peripheral is configured to use CCI.It fixes CR#972638
460 * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
461 * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
462 * the HW coherency enablement. It fixes the CR#973287
463 * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
464 * L2CTLR_EL1 register. It fixes the CR#974698
465 * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
466 * of ARM 32 bit processor's.
467 * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
468 * snippet, which checks for the FPEN bit of CPACR_EL1 register.
469 * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
470 * XGetPSVersion_Info function for PMUFW.
471 * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
472 * function for PMUFW.
473 * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
474 * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
475 * operations.Now,VFP is being enabled in FPEXC register, through boot code
476 * and FPU registers are being saved/restored when irq/fiq vector is invoked.
477 * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
478 * if h/w design configured with HPC port.
479 * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
480 * EL1 NS execution. This change has been done to support CCI enabled IP's.
481 * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
483 * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
484 * make RPU MPU handling user-friendly. This also fixes the CR-981028.
485 * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
486 * version register through SMC call, over EL1 NS mode. This change has been done to
487 * support these APIs over EL1 NS mode.
488 * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
489 * it fixes CR#987464.
490 * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
491 * It fixes CR#989132.
492 * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
493 * will use the timer specified by the user to provide delay. A9 and A53 can use
494 * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
495 * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
496 * to support the sleep configuration Added new API's for the Axi timer in
497 * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
498 * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
499 * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
500 * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
501 * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
502 * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
503 * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
504 * after writing to cpacr_el1/cptr_el3 registers. It would ensure
505 * disabling/enabling of floating-point unit, before any subsequent
507 * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
508 * support. Now, xil_printf would use PV console instead of UART in case of
509 * hypervisor enabled BSP.
510 * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
511 * configured with smart interconnect.It fixes CR#990318.
512 * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
513 * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
514 * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
516 * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
517 * non-JTAG boot mode, when processor is in lockstep configuration.
518 * This behavior is restricting application debugging in non-JTAG boot
519 * mode. To get rid of this restriction, added new mld parameter
520 * "lockstep_mode_debug", to enable/disable debug logic from BSP
521 * settings. Now, debug logic can be enabled through BSP settings,
522 * by modifying value of parameter "lockstep_mode_debug" as "true".
523 * It fixes CR#993896.
524 * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
525 * Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
526 * in handling upper DDR addresses.It fixes CR#995581.
527 * 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
528 * in the list of include paths. This change allows applications/BSP
529 * files to include .h files in include_ps directory.
530 * 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
531 * results into abort if accessed from EL1 non secure privilege
532 * level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
533 * to avoid CPUACTLR_EL1 access from privile levels other than EL3.
534 * 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
535 * XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
536 * use UART console, PV console can be enabled by appending
537 "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
539 *****************************************************************************************/
projects / freertos / blob