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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
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   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
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  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xpm_counter.c
  36 *
  37 * This file contains APIs for configuring and controlling the Cortex-R5
  38 * Performance Monitor Events. For more information about the event counters,
  39 * see xpm_counter.h.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who  Date     Changes
  45 * ----- ---- -------- -----------------------------------------------
  46 * 5.00  pkp  02/10/14 Initial version
  47 * 6.2   mus  01/27/17 Updated to support IAR compiler
  48 * </pre>
  49 *
  50 ******************************************************************************/
  51
  52 /***************************** Include Files *********************************/
  53
  54 #include "xpm_counter.h"
  55
  56 /************************** Constant Definitions ****************************/
  57
  58 /**************************** Type Definitions ******************************/
  59
  60 typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
  61
  62 /***************** Macros (Inline Functions) Definitions ********************/
  63
  64 /************************** Variable Definitions *****************************/
  65
  66
  67
  68 /************************** Function Prototypes ******************************/
  69
  70 void Xpm_DisableEventCounters(void);
  71 void Xpm_EnableEventCounters (void);
  72 void Xpm_ResetEventCounters (void);
  73
  74 /******************************************************************************/
  75
  76 /****************************************************************************/
  77 /**
  78 *
  79 * @brief    This function disables the Cortex R5 event counters.
  80 *
  81 * @param        None.
  82 *
  83 * @return       None.
  84 *
  85 *****************************************************************************/
  86 void Xpm_DisableEventCounters(void)
  87 {
  88         /* Disable the event counters */
  89         mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
  90 }
  91
  92 /****************************************************************************/
  93 /**
  94 *
  95 * @brief    This function enables the Cortex R5 event counters.
  96 *
  97 * @param        None.
  98 *
  99 * @return       None.
 100 *
 101 *****************************************************************************/
 102 void Xpm_EnableEventCounters(void)
 103 {
 104         /* Enable the event counters */
 105         mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
 106 }
 107
 108 /****************************************************************************/
 109 /**
 110 *
 111 * @brief    This function resets the Cortex R5 event counters.
 112 *
 113 * @param        None.
 114 *
 115 * @return       None.
 116 *
 117 *****************************************************************************/
 118 void Xpm_ResetEventCounters(void)
 119 {
 120         u32 Reg;
 121
 122 #ifdef __GNUC__
 123         Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
 124 #elif defined (__ICCARM__)
 125     mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
 126 #else
 127         { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
 128           Reg = C15Reg; }
 129 #endif
 130         Reg |= (1U << 2U); /* reset event counters */
 131         mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
 132 }
 133
 134 /****************************************************************************/
 135 /**
 136 *
 137 * @brief    This function configures the Cortex R5 event counters controller,
 138 *           with the event codes, in a configuration selected by the user and
 139 *           enables the counters.
 140 *
 141 * @param        PmcrCfg: Configuration value based on which the event counters
 142 *                   are configured.XPM_CNTRCFG* values defined in xpm_counter.h can
 143 *                   be utilized for setting configuration
 144 *
 145 * @return       None.
 146 *
 147 *****************************************************************************/
 148 void Xpm_SetEvents(s32 PmcrCfg)
 149 {
 150         u32 Counter;
 151         static PmcrEventCfg32 PmcrEvents[] = {
 152                 {
 153                         XPM_EVENT_SOFTINCR,
 154                         XPM_EVENT_INSRFETCH_CACHEREFILL,
 155                         XPM_EVENT_INSTRFECT_TLBREFILL,
 156                         XPM_EVENT_DATA_CACHEREFILL,
 157                         XPM_EVENT_DATA_CACHEACCESS,
 158                         XPM_EVENT_DATA_TLBREFILL
 159                 },
 160                 {
 161                         XPM_EVENT_DATA_READS,
 162                         XPM_EVENT_DATA_WRITE,
 163                         XPM_EVENT_EXCEPTION,
 164                         XPM_EVENT_EXCEPRETURN,
 165                         XPM_EVENT_CHANGECONTEXT,
 166                         XPM_EVENT_SW_CHANGEPC
 167                 },
 168                 {
 169                         XPM_EVENT_IMMEDBRANCH,
 170                         XPM_EVENT_UNALIGNEDACCESS,
 171                         XPM_EVENT_BRANCHMISS,
 172                         XPM_EVENT_CLOCKCYCLES,
 173                         XPM_EVENT_BRANCHPREDICT,
 174                         XPM_EVENT_JAVABYTECODE
 175                 },
 176                 {
 177                         XPM_EVENT_SWJAVABYTECODE,
 178                         XPM_EVENT_JAVABACKBRANCH,
 179                         XPM_EVENT_COHERLINEMISS,
 180                         XPM_EVENT_COHERLINEHIT,
 181                         XPM_EVENT_INSTRSTALL,
 182                         XPM_EVENT_DATASTALL
 183                 },
 184                 {
 185                         XPM_EVENT_MAINTLBSTALL,
 186                         XPM_EVENT_STREXPASS,
 187                         XPM_EVENT_STREXFAIL,
 188                         XPM_EVENT_DATAEVICT,
 189                         XPM_EVENT_NODISPATCH,
 190                         XPM_EVENT_ISSUEEMPTY
 191                 },
 192                 {
 193                         XPM_EVENT_INSTRRENAME,
 194                         XPM_EVENT_PREDICTFUNCRET,
 195                         XPM_EVENT_MAINEXEC,
 196                         XPM_EVENT_SECEXEC,
 197                         XPM_EVENT_LDRSTR,
 198                         XPM_EVENT_FLOATRENAME
 199                 },
 200                 {
 201                         XPM_EVENT_NEONRENAME,
 202                         XPM_EVENT_PLDSTALL,
 203                         XPM_EVENT_WRITESTALL,
 204                         XPM_EVENT_INSTRTLBSTALL,
 205                         XPM_EVENT_DATATLBSTALL,
 206                         XPM_EVENT_INSTR_uTLBSTALL
 207                 },
 208                 {
 209                         XPM_EVENT_DATA_uTLBSTALL,
 210                         XPM_EVENT_DMB_STALL,
 211                         XPM_EVENT_INT_CLKEN,
 212                         XPM_EVENT_DE_CLKEN,
 213                         XPM_EVENT_INSTRISB,
 214                         XPM_EVENT_INSTRDSB
 215                 },
 216                 {
 217                         XPM_EVENT_INSTRDMB,
 218                         XPM_EVENT_EXTINT,
 219                         XPM_EVENT_PLE_LRC,
 220                         XPM_EVENT_PLE_LRS,
 221                         XPM_EVENT_PLE_FLUSH,
 222                         XPM_EVENT_PLE_CMPL
 223                 },
 224                 {
 225                         XPM_EVENT_PLE_OVFL,
 226                         XPM_EVENT_PLE_PROG,
 227                         XPM_EVENT_PLE_LRC,
 228                         XPM_EVENT_PLE_LRS,
 229                         XPM_EVENT_PLE_FLUSH,
 230                         XPM_EVENT_PLE_CMPL
 231                 },
 232                 {
 233                         XPM_EVENT_DATASTALL,
 234                         XPM_EVENT_INSRFETCH_CACHEREFILL,
 235                         XPM_EVENT_INSTRFECT_TLBREFILL,
 236                         XPM_EVENT_DATA_CACHEREFILL,
 237                         XPM_EVENT_DATA_CACHEACCESS,
 238                         XPM_EVENT_DATA_TLBREFILL
 239                 },
 240         };
 241         const u32 *ptr = PmcrEvents[PmcrCfg];
 242
 243         Xpm_DisableEventCounters();
 244
 245         for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
 246
 247                 /* Selecet event counter */
 248                 mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
 249
 250                 /* Set the event */
 251                 mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
 252         }
 253
 254         Xpm_ResetEventCounters();
 255         Xpm_EnableEventCounters();
 256 }
 257
 258 /****************************************************************************/
 259 /**
 260 *
 261 * @brief    This function disables the event counters and returns the counter
 262 *           values.
 263 *
 264 * @param        PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
 265 *                   It is an output parameter which is used to return the PM
 266 *                   counter values.
 267 *
 268 * @return       None.
 269 *
 270 *****************************************************************************/
 271 void Xpm_GetEventCounters(u32 *PmCtrValue)
 272 {
 273         u32 Counter;
 274
 275         Xpm_DisableEventCounters();
 276
 277         for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
 278
 279                 mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
 280 #ifdef __GNUC__
 281                 PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
 282 #elif defined (__ICCARM__)
 283         mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
 284 #else
 285                 { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
 286                   PmCtrValue[Counter] = Cp15Reg; }
 287 #endif
 288         }
 289 }