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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  22 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xsysmonpsu.c
  36 *
  37 * Functions in this file are the minimum required functions for the XSysMonPsu
  38 * driver. See xsysmonpsu.h for a detailed description of the driver.
  39 *
  40 * @note         None.
  41 *
  42 * <pre>
  43 *
  44 * MODIFICATION HISTORY:
  45 *
  46 * Ver   Who    Date         Changes
  47 * ----- -----  -------- -----------------------------------------------
  48 * 1.0   kvn    12/15/15 First release.
  49 *              02/15/16 Corrected Assert function call in
  50 *                       XSysMonPsu_GetMonitorStatus API.
  51 *              03/03/16 Added Temperature remote channel for Setsingle
  52 *                       channel API. Also corrected external mux channel
  53 *                       numbers.
  54 * 1.1   kvn    05/05/16 Modified code for MISRA-C:2012 Compliance.
  55 * 2.0   vns    08/14/16 Fixed CR #956780, added support for enabling/disabling
  56 *                       SEQ_CH2 and SEQ_AVG2 registers, modified function
  57 *                       prototypes of XSysMonPsu_GetSeqAvgEnables,
  58 *                       XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
  59 *                       XSysMonPsu_GetSeqChEnables,
  60 *                       XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
  61 *                       XSysMonPsu_SetSeqAcqTime
  62 *                       and XSysMonPsu_GetSeqAcqTime to provide support for
  63 *                       set/get 64 bit value.
  64 *
  65 * </pre>
  66 *
  67 ******************************************************************************/
  68
  69 /***************************** Include Files *********************************/
  70
  71 #include "xsysmonpsu.h"
  72
  73 /************************** Constant Definitions ****************************/
  74
  75 /**************************** Type Definitions ******************************/
  76
  77 /***************** Macros (Inline Functions) Definitions ********************/
  78
  79 /************************** Function Prototypes *****************************/
  80
  81 static void XSysMonPsu_StubHandler(void *CallBackRef);
  82
  83 /************************** Variable Definitions ****************************/
  84
  85 /*****************************************************************************/
  86 /**
  87 *
  88 * This function initializes XSysMonPsu device/instance. This function
  89 * must be called prior to using the System Monitor device.
  90 *
  91 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
  92 * @param        ConfigPtr points to the XSysMonPsu device configuration structure.
  93 * @param        EffectiveAddr is the device base address in the virtual memory
  94 *               address space. If the address translation is not used then the
  95 *               physical address is passed.
  96 *               Unexpected errors may occur if the address mapping is changed
  97 *               after this function is invoked.
  98 *
  99 * @return
 100 *               - XST_SUCCESS if successful.
 101 *
 102 * @note         The user needs to first call the XSysMonPsu_LookupConfig() API
 103 *               which returns the Configuration structure pointer which is
 104 *               passed as a parameter to the XSysMonPsu_CfgInitialize() API.
 105 *
 106 ******************************************************************************/
 107 s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
 108                           u32 EffectiveAddr)
 109 {
 110         u32 PsSysmonControlStatus;
 111         u32 PlSysmonControlStatus;
 112
 113         /* Assert the input arguments. */
 114         Xil_AssertNonvoid(InstancePtr != NULL);
 115         Xil_AssertNonvoid(ConfigPtr != NULL);
 116
 117         /* Set the values read from the device config and the base address. */
 118         InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
 119         InstancePtr->Config.BaseAddress = EffectiveAddr;
 120
 121
 122         /* Set all handlers to stub values, let user configure this data later. */
 123         InstancePtr->Handler = XSysMonPsu_StubHandler;
 124
 125         /* Reset the device such that it is in a known state. */
 126         XSysMonPsu_Reset(InstancePtr);
 127
 128         PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
 129                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
 130
 131         /* Check if the PS Sysmon is in Idle / ready state or not */
 132         while(PsSysmonControlStatus != XSYSMONPSU_PS_SYSMON_READY) {
 133                 PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
 134                                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
 135         }
 136
 137         PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
 138                         XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
 139
 140         /* Check if the PL Sysmon is accessible to PS Sysmon or not */
 141         while((PlSysmonControlStatus & XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK)
 142                                 != XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK) {
 143                 PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
 144                                         XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
 145         }
 146
 147         /* Indicate the instance is now ready to use, initialized without error */
 148         InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 149
 150         return XST_SUCCESS;
 151 }
 152
 153 /****************************************************************************/
 154 /**
 155 *
 156 * This function is a stub handler that is the default handler such that if the
 157 * application has not set the handler when interrupts are enabled, this
 158 * function will be called.
 159 *
 160 * @param        CallBackRef is unused by this function.
 161 *
 162 * @return       None.
 163 *
 164 * @note         None.
 165 *
 166 *****************************************************************************/
 167 static void XSysMonPsu_StubHandler(void *CallBackRef)
 168 {
 169         (void *) CallBackRef;
 170
 171         /* Assert occurs always since this is a stub and should never be called */
 172         Xil_AssertVoidAlways();
 173 }
 174
 175 /*****************************************************************************/
 176 /**
 177 *
 178 * This function resets the SystemMonitor
 179 *
 180 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 181 *
 182 * @return       None.
 183 *
 184 * @note         Upon reset, all Maximum and Minimum status registers will be
 185 *               reset to their default values. Currently running and any averaging
 186 *               will restart. Refer to the device data sheet for the device status and
 187 *               register values after the reset.
 188 *
 189 ******************************************************************************/
 190 void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
 191 {
 192         /* Assert the arguments. */
 193         Xil_AssertVoid(InstancePtr != NULL);
 194
 195         /* RESET the PS SYSMON */
 196         XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET +
 197                         XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
 198
 199         /* RESET the PL SYSMON */
 200         XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
 201                         XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
 202
 203 }
 204
 205 /****************************************************************************/
 206 /**
 207 *
 208 * This function reads the contents of the Status Register.
 209 *
 210 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 211 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 212 *       block or PL Sysmon block register region.
 213 *
 214 * @return       A 32-bit value representing the contents of the Status Register.
 215 *               Use the XSYSMONPSU_MON_STS_* constants defined in xsysmonpsu_hw.h to
 216 *               interpret the returned value.
 217 *
 218 * @note         None.
 219 *****************************************************************************/
 220 u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 221 {
 222         u32 Status;
 223         u32 EffectiveBaseAddress;
 224
 225         /* Assert the arguments. */
 226         Xil_AssertNonvoid(InstancePtr != NULL);
 227         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 228         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 229
 230         /* Calculate the effective baseaddress based on the Sysmon instance. */
 231         EffectiveBaseAddress =
 232                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 233                                         SysmonBlk);
 234
 235         /* Read the Sysmon Status Register and return the value. */
 236         Status = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_MON_STS_OFFSET);
 237
 238         return Status;
 239 }
 240
 241 /****************************************************************************/
 242 /**
 243 *
 244 * This function starts the ADC conversion in the Single Channel event driven
 245 * sampling mode. The EOC bit in Status Register will be set once the conversion
 246 * is finished. Refer to the device specification for more details.
 247 *
 248 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 249 *
 250 * @return       None.
 251 *
 252 * @note         The default state of the CONVST bit is a logic 0. The conversion
 253 *               is started when the CONVST bit is set to 1 from 0.
 254 *               This bit is self-clearing so that the next conversion
 255 *               can be started by setting this bit.
 256 *
 257 *****************************************************************************/
 258 void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr)
 259 {
 260         u32 ControlStatus;
 261
 262         /* Assert the arguments. */
 263         Xil_AssertVoid(InstancePtr != NULL);
 264         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 265
 266         /*
 267          * Start the conversion by setting the CONVST bit to 1 only if auto-convst
 268          * bit is not enabled. This convst bit is self-clearing.
 269          */
 270         ControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
 271                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
 272
 273         if ((ControlStatus & XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK )
 274                         != XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK) {
 275                 XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
 276                                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET,
 277                                         (ControlStatus | (u32)XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK));
 278         }
 279 }
 280
 281 /****************************************************************************/
 282 /**
 283 *
 284 * Get the ADC converted data for the specified channel.
 285 *
 286 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 287 * @param        Channel is the channel number. Use the XSM_CH_* defined in
 288 *               the file xsysmonpsu.h. The valid channels for PS / PL SysMon are 0 - 6,
 289 *               8 - 10 and 13 - 37. For AMS, 38 - 53 channels are valid.
 290 * @param        Block is the value that tells whether it is for PS Sysmon block
 291 *       or PL Sysmon block or the AMS controller register region.
 292 *
 293 * @return       A 16-bit value representing the ADC converted data for the
 294 *               specified channel. The System Monitor device guarantees
 295 *               a 10 bit resolution for the ADC converted data and data is the
 296 *               10 MSB bits of the 16 data read from the device.
 297 *
 298 * @note         Please make sure that the proper channel number is passed.
 299 *
 300 *****************************************************************************/
 301 u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block)
 302 {
 303         u16 AdcData;
 304         u32 EffectiveBaseAddress;
 305
 306         /* Assert the arguments. */
 307         Xil_AssertNonvoid(InstancePtr != NULL);
 308         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 309         Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
 310                           ((Channel >= XSM_CH_SUPPLY_CALIB) &&
 311                           (Channel <= XSM_CH_GAINERR_CALIB)) ||
 312                           ((Channel >= XSM_CH_SUPPLY4) &&
 313                           (Channel <= XSM_CH_RESERVE1)));
 314         Xil_AssertNonvoid((Block == XSYSMON_PS)||(Block == XSYSMON_PL)
 315                                                 ||(Block == XSYSMON_AMS));
 316
 317         /* Calculate the effective baseaddress based on the Sysmon instance. */
 318         EffectiveBaseAddress =
 319                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 320                                         Block);
 321
 322         /*
 323          * Read the selected ADC converted data for the specified channel
 324          * and return the value.
 325          */
 326         if (Channel <= XSM_CH_AUX_MAX) {
 327                 AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + ((u32)Channel << 2U)));
 328         } else if ((Channel >= XSM_CH_SUPPLY7) && (Channel <= XSM_CH_TEMP_REMTE)){
 329                 AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_ADC_CH_OFFSET +
 330                                 (((u32)Channel - XSM_CH_SUPPLY7) << 2U)));
 331         } else {
 332                 AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_AMS_CH_OFFSET +
 333                                 (((u32)Channel - XSM_CH_VCC_PSLL0) << 2U)));
 334         }
 335
 336         return AdcData;
 337 }
 338
 339 /****************************************************************************/
 340 /**
 341 *
 342 * This function gets the calibration coefficient data for the specified
 343 * parameter.
 344 *
 345 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 346 * @param        CoeffType specifies the calibration coefficient
 347 *               to be read. Use XSM_CALIB_* constants defined in xsysmonpsu.h to
 348 *               specify the calibration coefficient to be read.
 349 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 350 *       block or PL Sysmon block register region.
 351 *
 352 * @return       A 16-bit value representing the calibration coefficient.
 353 *               The System Monitor device guarantees a 10 bit resolution for
 354 *               the ADC converted data and data is the 10 MSB bits of the 16
 355 *               data read from the device.
 356 *
 357 * @note         None.
 358 *
 359 *****************************************************************************/
 360 u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType,
 361                 u32 SysmonBlk)
 362 {
 363         u16 CalibData;
 364         u32 EffectiveBaseAddress;
 365
 366         /* Assert the arguments. */
 367         Xil_AssertNonvoid(InstancePtr != NULL);
 368         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 369         Xil_AssertNonvoid(CoeffType <= XSM_CALIB_GAIN_ERROR_COEFF);
 370         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 371
 372         /* Calculate the effective baseaddress based on the Sysmon instance. */
 373         EffectiveBaseAddress =
 374                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 375                                         SysmonBlk);
 376
 377         /* Read the selected calibration coefficient. */
 378         CalibData = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
 379                         XSYSMONPSU_CAL_SUP_OFF_OFFSET + ((u32)CoeffType << 2U));
 380
 381         return CalibData;
 382 }
 383
 384 /****************************************************************************/
 385 /**
 386 *
 387 * This function reads the Minimum/Maximum measurement for one of the
 388 * XSM_MIN_* or XSM_MAX_* constants defined in xsysmonpsu.h
 389 *
 390 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 391 * @param        MeasurementType specifies the parameter for which the
 392 *               Minimum/Maximum measurement has to be read.
 393 *               Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmonpsu.h to
 394 *               specify the data to be read.
 395 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 396 *       block or PL Sysmon block register region.
 397 *
 398 * @return       A 16-bit value representing the maximum/minimum measurement for
 399 *               specified parameter.
 400 *               The System Monitor device guarantees a 10 bit resolution for
 401 *               the ADC converted data and data is the 10 MSB bits of  16 bit
 402 *               data read from the device.
 403 *
 404 *****************************************************************************/
 405 u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
 406                 u32 SysmonBlk)
 407 {
 408         u16 MinMaxData;
 409         u32 EffectiveBaseAddress;
 410
 411         /* Assert the arguments. */
 412         Xil_AssertNonvoid(InstancePtr != NULL);
 413         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 414         Xil_AssertNonvoid((MeasurementType <= XSM_MAX_SUPPLY6) ||
 415                         ((MeasurementType >= XSM_MIN_SUPPLY4) &&
 416                         (MeasurementType <= XSM_MIN_SUPPLY6)) ||
 417                         ((MeasurementType >= XSM_MAX_SUPPLY7) &&
 418                         (MeasurementType <= XSM_MAX_TEMP_REMOTE)) ||
 419                         ((MeasurementType >= XSM_MIN_SUPPLY7) &&
 420                         (MeasurementType <= XSM_MIN_TEMP_REMOTE)));
 421         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 422
 423         /* Calculate the effective baseaddress based on the Sysmon instance. */
 424         EffectiveBaseAddress =
 425                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 426                                         SysmonBlk);
 427
 428         /* Read and return the specified Minimum/Maximum measurement. */
 429         MinMaxData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress +
 430                                                         XSM_MIN_MAX_CH_OFFSET + ((u32)MeasurementType << 2U)));
 431
 432         return MinMaxData;
 433 }
 434
 435 /****************************************************************************/
 436 /**
 437 *
 438 * This function sets the number of samples of averaging that is to be done for
 439 * all the channels in both the single channel mode and sequence mode of
 440 * operations.
 441 *
 442 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 443 * @param        Average is the number of samples of averaging programmed to the
 444 *               Configuration Register 0. Use the XSM_AVG_* definitions defined
 445 *               in xsysmonpsu.h file :
 446 *               - XSM_AVG_0_SAMPLES for no averaging
 447 *               - XSM_AVG_16_SAMPLES for 16 samples of averaging
 448 *               - XSM_AVG_64_SAMPLES for 64 samples of averaging
 449 *               - XSM_AVG_256_SAMPLES for 256 samples of averaging
 450 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 451 *       block or PL Sysmon block register region.
 452 *
 453 * @return       None.
 454 *
 455 * @note         None.
 456 *
 457 *****************************************************************************/
 458 void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk)
 459 {
 460         u32 RegValue;
 461         u32 EffectiveBaseAddress;
 462
 463         /* Assert the arguments. */
 464         Xil_AssertVoid(InstancePtr != NULL);
 465         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 466         Xil_AssertVoid(Average <= XSM_AVG_256_SAMPLES);
 467         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 468
 469         /* Calculate the effective baseaddress based on the Sysmon instance. */
 470         EffectiveBaseAddress =
 471                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 472                                         SysmonBlk);
 473
 474         /* Write the averaging value into the Configuration Register 0. */
 475         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET)
 476                                                 & (u32)(~XSYSMONPSU_CFG_REG0_AVRGNG_MASK);
 477         RegValue |= (((u32) Average << XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT));
 478         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
 479                          RegValue);
 480 }
 481
 482 /****************************************************************************/
 483 /**
 484 *
 485 * This function returns the number of samples of averaging configured for all
 486 * the channels in the Configuration Register 0.
 487 *
 488 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 489 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 490 *       block or PL Sysmon block register region.
 491 *
 492 * @return       The averaging read from the Configuration Register 0 is
 493 *               returned. Use the XSM_AVG_* bit definitions defined in xsysmonpsu.h
 494 *               file to interpret the returned value :
 495 *               - XSM_AVG_0_SAMPLES means no averaging
 496 *               - XSM_AVG_16_SAMPLES means 16 samples of averaging
 497 *               - XSM_AVG_64_SAMPLES means 64 samples of averaging
 498 *               - XSM_AVG_256_SAMPLES means 256 samples of averaging
 499 *
 500 * @note         None.
 501 *
 502 *****************************************************************************/
 503 u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 504 {
 505         u32 Average;
 506         u32 EffectiveBaseAddress;
 507
 508         /* Assert the arguments. */
 509         Xil_AssertNonvoid(InstancePtr != NULL);
 510         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 511         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 512
 513         /* Calculate the effective baseaddress based on the Sysmon instance. */
 514         EffectiveBaseAddress =
 515                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 516                                         SysmonBlk);
 517
 518         /* Read the averaging value from the Configuration Register 0. */
 519         Average = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 520                                 XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
 521
 522         return (u8)(Average >> XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT);
 523 }
 524
 525 /****************************************************************************/
 526 /**
 527 *
 528 * The function sets the given parameters in the Configuration Register 0 in
 529 * the single channel mode.
 530 *
 531 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 532 * @param        Channel is the channel number for conversion. The valid
 533 *               channels are 0 - 6, 8 - 10, 13 - 37.
 534 * @param        IncreaseAcqCycles is a boolean parameter which specifies whether
 535 *               the Acquisition time for the external channels has to be
 536 *               increased to 10 ADCCLK cycles (specify TRUE) or remain at the
 537 *               default 4 ADCCLK cycles (specify FALSE). This parameter is
 538 *               only valid for the external channels.
 539 * @param        IsEventMode is a boolean parameter that specifies continuous
 540 *               sampling (specify FALSE) or event driven sampling mode (specify
 541 *               TRUE) for the given channel.
 542 * @param        IsDifferentialMode is a boolean parameter which specifies
 543 *               unipolar(specify FALSE) or differential mode (specify TRUE) for
 544 *               the analog inputs. The  input mode is only valid for the
 545 *               external channels.
 546 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 547 *       block or PL Sysmon block register region.
 548 *
 549 * @return
 550 *               - XST_SUCCESS if the given values were written successfully to
 551 *               the Configuration Register 0.
 552 *               - XST_FAILURE if the channel sequencer is enabled or the input
 553 *               parameters are not valid for the selected channel.
 554 *
 555 * @note
 556 *               - The number of samples for the averaging for all the channels
 557 *               is set by using the function XSysMonPsu_SetAvg.
 558 *               - The calibration of the device is done by doing a ADC
 559 *               conversion on the calibration channel(channel 8). The input
 560 *               parameters IncreaseAcqCycles, IsDifferentialMode and
 561 *               IsEventMode are not valid for this channel.
 562 *
 563 *****************************************************************************/
 564 s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
 565                                 u32 IncreaseAcqCycles, u32 IsEventMode,
 566                                 u32 IsDifferentialMode, u32 SysmonBlk)
 567 {
 568         u32 RegValue;
 569         u32 EffectiveBaseAddress;
 570         s32 Status;
 571
 572         /* Assert the arguments. */
 573         Xil_AssertNonvoid(InstancePtr != NULL);
 574         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 575         Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
 576                           ((Channel >= XSM_CH_SUPPLY_CALIB) &&
 577                           (Channel <= XSM_CH_GAINERR_CALIB)) ||
 578                           ((Channel >= XSM_CH_SUPPLY4) &&
 579                           (Channel <= XSM_CH_TEMP_REMTE)));
 580         Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
 581                           (IncreaseAcqCycles == FALSE));
 582         Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
 583         Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
 584                           (IsDifferentialMode == FALSE));
 585         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 586
 587         /* Check if the device is in single channel mode else return failure */
 588         if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
 589                                 != XSM_SEQ_MODE_SINGCHAN)) {
 590                 Status = (s32)XST_FAILURE;
 591                 goto End;
 592         }
 593
 594         /* Calculate the effective baseaddress based on the Sysmon instance. */
 595         EffectiveBaseAddress =
 596                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 597                                         SysmonBlk);
 598
 599         /* Read the Configuration Register 0 and extract out Averaging value. */
 600         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 601                         XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
 602
 603         /*
 604          * Select the number of acquisition cycles. The acquisition cycles is
 605          * only valid for the external channels.
 606          */
 607         if (IncreaseAcqCycles == TRUE) {
 608                 if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
 609                     || (Channel == XSM_CH_VPVN)) {
 610                         RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
 611                 } else {
 612                         Status = (s32)XST_FAILURE;
 613                         goto End;
 614                 }
 615         }
 616
 617         /*
 618          * Select the input mode. The input mode is only valid for the
 619          * external channels.
 620          */
 621         if (IsDifferentialMode == TRUE) {
 622
 623                 if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
 624                     || (Channel == XSM_CH_VPVN)) {
 625                         RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
 626                 } else {
 627                         Status = (s32)XST_FAILURE;
 628                         goto End;
 629                 }
 630         }
 631
 632         /* Select the ADC mode. */
 633         if (IsEventMode == TRUE) {
 634                 RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
 635         }
 636
 637         /* Write the given values into the Configuration Register 0. */
 638         RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
 639         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
 640                          RegValue);
 641
 642         Status = (s32)XST_SUCCESS;
 643
 644 End:
 645         return Status;
 646 }
 647
 648 /****************************************************************************/
 649 /**
 650 *
 651 * This function enables the alarm outputs for the specified alarms in the
 652 * Configuration Registers 1:
 653 *
 654 *               - OT for Over Temperature (XSYSMONPSU_CFR_REG1_ALRM_OT_MASK)
 655 *               - ALM0 for On board Temperature (XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK)
 656 *               - ALM1 for SUPPLY1 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY1_MASK)
 657 *               - ALM2 for SUPPLY2 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY2_MASK)
 658 *               - ALM3 for SUPPLY3 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY3_MASK)
 659 *               - ALM4 for SUPPLY4 (XSYSMONPSU_CFR_REG1_ALRM__SUPPLY4_MASK)
 660 *               - ALM5 for SUPPLY5 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY5_MASK)
 661 *               - ALM6 for SUPPLY6 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY6_MASK)
 662 *
 663 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 664 * @param        AlmEnableMask is the bit-mask of the alarm outputs to be enabled
 665 *               in the Configuration Registers 1 and 3.
 666 *               Bit positions of 1 will be enabled. Bit positions of 0 will be
 667 *               disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
 668 *               masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
 669 *               XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
 670 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 671 *       block or PL Sysmon block register region.
 672 *
 673 * @return       None.
 674 *
 675 * @note         The implementation of the alarm enables in the Configuration
 676 *               register 1 is such that the alarms for bit positions of 0 will
 677 *               be enabled and alarms for bit positions of 1 will be disabled.
 678 *               The alarm outputs specified by the AlmEnableMask are negated
 679 *               before writing to the Configuration Register 1 because it
 680 *               was Disable register bits.
 681 *               Upper 16 bits of AlmEnableMask are applicable only for PS.
 682 *
 683 *****************************************************************************/
 684 void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
 685                 u32 SysmonBlk)
 686 {
 687         u32 RegValue;
 688         u32 EffectiveBaseAddress;
 689
 690         /* Assert the arguments. */
 691         Xil_AssertVoid(InstancePtr != NULL);
 692         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 693         Xil_AssertVoid(AlmEnableMask <=
 694                         (XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
 695                         (XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
 696         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 697
 698         /* Calculate the effective baseaddress based on the Sysmon instance. */
 699         EffectiveBaseAddress =
 700                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 701                                         SysmonBlk);
 702
 703         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 704                                         XSYSMONPSU_CFG_REG1_OFFSET);
 705         RegValue &= (u32)(~XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
 706         RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
 707
 708         /*
 709          * Enable/disables the alarm enables for the specified alarm bits in the
 710          * Configuration Register 1.
 711          */
 712         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
 713                          RegValue);
 714         /* Upper 16 bits of AlmEnableMask are valid only for PS */
 715         if (SysmonBlk == XSYSMON_PS) {
 716                 RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 717                                         XSYSMONPSU_CFG_REG3_OFFSET);
 718                 RegValue &= (u32)(~XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
 719                 RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
 720                                 (u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
 721                 XSysmonPsu_WriteReg(EffectiveBaseAddress +
 722                         XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
 723         }
 724 }
 725
 726 /****************************************************************************/
 727 /**
 728 *
 729 * This function gets the status of the alarm output enables in the
 730 * Configuration Register 1.
 731 *
 732 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 733 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 734 *       block or PL Sysmon block register region.
 735 *
 736 * @return       This is the bit-mask of the enabled alarm outputs in the
 737 *               Configuration Register 1. Use the masks XSYSMONPSU_CFG_REG1_ALRM_*_MASK
 738 *               masks defined in xsysmonpsu.h to interpret the returned value.
 739 *
 740 *               Bit positions of 1 indicate that the alarm output is enabled.
 741 *               Bit positions of 0 indicate that the alarm output is disabled.
 742 *
 743 *
 744 * @note         The implementation of the alarm enables in the Configuration
 745 *               register 1 is such that alarms for the bit positions of 1 will
 746 *               be disabled and alarms for bit positions of 0 will be enabled.
 747 *               The enabled alarm outputs returned by this function is the
 748 *               negated value of the the data read from the Configuration
 749 *               Register 1. Upper 16 bits of return value are valid only if the
 750 *               channel selected is PS.
 751 *
 752 *****************************************************************************/
 753 u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 754 {
 755         u32 RegValue;
 756         u32 EffectiveBaseAddress;
 757         u32 ReadReg;
 758
 759         /* Assert the arguments. */
 760         Xil_AssertNonvoid(InstancePtr != NULL);
 761         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 762         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 763
 764         /* Calculate the effective baseaddress based on the Sysmon instance. */
 765         EffectiveBaseAddress =
 766                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 767                                         SysmonBlk);
 768
 769         /*
 770          * Read the status of alarm output enables from the Configuration
 771          * Register 1.
 772          */
 773         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 774                         XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
 775         RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
 776
 777         if (SysmonBlk == XSYSMON_PS) {
 778                 ReadReg = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 779                         XSYSMONPSU_CFG_REG3_OFFSET) & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK;
 780                 ReadReg = (~ReadReg & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
 781                 RegValue |= ReadReg << XSM_CFG_ALARM_SHIFT;
 782         }
 783
 784         return RegValue;
 785 }
 786
 787 /****************************************************************************/
 788 /**
 789 *
 790 * This function sets the specified Channel Sequencer Mode in the Configuration
 791 * Register 1 :
 792 *               - Default safe mode (XSM_SEQ_MODE_SAFE)
 793 *               - One pass through sequence (XSM_SEQ_MODE_ONEPASS)
 794 *               - Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS)
 795 *               - Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN)
 796 *               - Olympus sampling mode (XSM_SEQ_MODE_OYLMPUS)
 797 *
 798 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 799 * @param        SequencerMode is the sequencer mode to be set.
 800 *               Use XSM_SEQ_MODE_* bits defined in xsysmonpsu.h.
 801 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 802 *       block or PL Sysmon block register region.
 803 *
 804 * @return       None.
 805 *
 806 * @note         Only one of the modes can be enabled at a time.
 807 *
 808 *****************************************************************************/
 809 void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
 810                 u32 SysmonBlk)
 811 {
 812         u32 RegValue;
 813         u32 EffectiveBaseAddress;
 814
 815         /* Assert the arguments. */
 816         Xil_AssertVoid(InstancePtr != NULL);
 817         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 818         Xil_AssertVoid((SequencerMode <= XSM_SEQ_MODE_SINGCHAN) ||
 819                         (SequencerMode == XSM_SEQ_MODE_OYLMPUS));
 820         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 821
 822         /* Calculate the effective baseaddress based on the Sysmon instance. */
 823         EffectiveBaseAddress =
 824                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 825                                         SysmonBlk);
 826
 827         /* Set the specified sequencer mode in the Configuration Register 1. */
 828         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 829                                         XSYSMONPSU_CFG_REG1_OFFSET);
 830         RegValue &= (u32)(~ XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
 831         RegValue |= (((u32)SequencerMode  << XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT) &
 832                                         XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
 833         XSysmonPsu_WriteReg(EffectiveBaseAddress +
 834                                         XSYSMONPSU_CFG_REG1_OFFSET, RegValue);
 835 }
 836
 837 /****************************************************************************/
 838 /**
 839 *
 840 * This function gets the channel sequencer mode from the Configuration
 841 * Register 1.
 842 *
 843 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 844 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 845 *       block or PL Sysmon block register region.
 846 *
 847 * @return       The channel sequencer mode :
 848 *               - XSM_SEQ_MODE_SAFE : Default safe mode
 849 *               - XSM_SEQ_MODE_ONEPASS : One pass through sequence
 850 *               - XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing
 851 *               - XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
 852 *               - XSM_SEQ_MODE_OLYMPUS : Olympus sampling mode
 853 *
 854 * @note         None.
 855 *
 856 *****************************************************************************/
 857 u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 858 {
 859         u8 SequencerMode;
 860         u32 EffectiveBaseAddress;
 861
 862         /* Assert the arguments. */
 863         Xil_AssertNonvoid(InstancePtr != NULL);
 864         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 865         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 866
 867         /* Calculate the effective baseaddress based on the Sysmon instance. */
 868         EffectiveBaseAddress =
 869                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 870                                         SysmonBlk);
 871
 872         /* Read the channel sequencer mode from the Configuration Register 1. */
 873         SequencerMode =  ((u8) ((XSysmonPsu_ReadReg(EffectiveBaseAddress +
 874                         XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK) >>
 875                         XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT));
 876
 877         return SequencerMode;
 878 }
 879
 880 /****************************************************************************/
 881 /**
 882 *
 883 * The function enables the Event mode or Continuous mode in the sequencer mode.
 884 *
 885 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 886 * @param        IsEventMode is a boolean parameter that specifies continuous
 887 *               sampling (specify FALSE) or event driven sampling mode (specify
 888 *               TRUE) for the channel.
 889 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 890 *       block or PL Sysmon block register region.
 891 *
 892 * @return       None.
 893 *
 894 * @note         None.
 895 *
 896 *****************************************************************************/
 897 void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
 898                 u32 SysmonBlk)
 899 {
 900         u32 RegValue;
 901         u32 EffectiveBaseAddress;
 902
 903         /* Assert the arguments. */
 904         Xil_AssertVoid(InstancePtr != NULL);
 905         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 906         Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
 907         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 908
 909         /* Calculate the effective baseaddress based on the Sysmon instance. */
 910         EffectiveBaseAddress =
 911                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 912                                         SysmonBlk);
 913
 914         /* Read the Configuration Register 0. */
 915         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 916                                         XSYSMONPSU_CFG_REG0_OFFSET);
 917
 918         /* Set the ADC mode. */
 919         if (IsEventMode == TRUE) {
 920                 RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
 921         } else {
 922                 RegValue &= (u32)(~XSYSMONPSU_CFG_REG0_EC_MASK);
 923         }
 924
 925         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
 926                          RegValue);
 927 }
 928
 929 /****************************************************************************/
 930 /**
 931 *
 932 * The function returns the mode of the sequencer.
 933 *
 934 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 935 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 936 *       block or PL Sysmon block register region.
 937 *
 938 * @return       Returns the Sequencer mode. XSYSMONPSU_EVENT_MODE for Event mode
 939 *               and XSYSMONPSU_CONTINUOUS_MODE for continuous mode.
 940 *
 941 * @note         None.
 942 *
 943 *****************************************************************************/
 944 s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 945 {
 946         s32 Mode;
 947         u32 RegValue;
 948         u32 EffectiveBaseAddress;
 949
 950         /* Assert the arguments. */
 951         Xil_AssertNonvoid(InstancePtr != NULL);
 952         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 953         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 954
 955         /* Calculate the effective baseaddress based on the Sysmon instance. */
 956         EffectiveBaseAddress =
 957                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
 958                                         SysmonBlk);
 959
 960         /* Read the Configuration Register 0. */
 961         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 962                                         XSYSMONPSU_CFG_REG0_OFFSET);
 963
 964         RegValue &= XSYSMONPSU_CFG_REG0_EC_MASK;
 965
 966         if (RegValue == XSYSMONPSU_CFG_REG0_EC_MASK) {
 967                 Mode = XSYSMONPSU_EVENT_MODE;
 968         } else {
 969                 Mode = XSYSMONPSU_CONTINUOUS_MODE;
 970         }
 971
 972         return Mode;
 973 }
 974
 975 /****************************************************************************/
 976 /**
 977 *
 978 * The function enables the external mux and connects a channel to the mux.
 979 *
 980 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
 981 * @param        Channel is the channel number used to connect to the external
 982 *               Mux. The valid channels are 0 to 5 and 16 to 31.
 983 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
 984 *       block or PL Sysmon block register region.
 985 *
 986 * @return
 987 *               - XST_SUCCESS if the given values were written successfully to
 988 *               the Configuration Register 0.
 989 *               - XST_FAILURE if the channel sequencer is enabled or the input
 990 *               parameters are not valid for the selected channel.
 991 *
 992 * @note         None.
 993 *
 994 *****************************************************************************/
 995 void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk)
 996 {
 997         u32 RegValue;
 998         u32 EffectiveBaseAddress;
 999
1000         /* Assert the arguments. */
1001         Xil_AssertVoid(InstancePtr != NULL);
1002         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1003         Xil_AssertVoid((Channel <= XSM_CH_VREFN) ||
1004                           ((Channel >= XSM_CH_AUX_MIN) &&
1005                           (Channel <= XSM_CH_AUX_MAX)));
1006         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1007
1008         /* Calculate the effective baseaddress based on the Sysmon instance. */
1009         EffectiveBaseAddress =
1010                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1011                                         SysmonBlk);
1012
1013         /*
1014          * Read the Configuration Register 0 and the clear the channel selection
1015          * bits.
1016          */
1017         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1018                                         XSYSMONPSU_CFG_REG0_OFFSET);
1019         RegValue &= ~(XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
1020
1021         /* Enable the External Mux and select the channel. */
1022         RegValue |= (XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK | (u32)Channel);
1023         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
1024                          RegValue);
1025 }
1026
1027 /****************************************************************************/
1028 /**
1029 *
1030 * The function returns the external mux channel.
1031 *
1032 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1033 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1034 *       block or PL Sysmon block register region.
1035 *
1036 * @return       Returns the channel number used to connect to the external
1037 *               Mux. The valid channels are 0 to 6, 8 to 16, and 31 to 36..
1038 *
1039 * @note         None.
1040 *
1041 *****************************************************************************/
1042 u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1043 {
1044         u32 RegValue;
1045         u32 EffectiveBaseAddress;
1046
1047         /* Assert the arguments. */
1048         Xil_AssertNonvoid(InstancePtr != NULL);
1049         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1050         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1051
1052         /* Calculate the effective baseaddress based on the Sysmon instance. */
1053         EffectiveBaseAddress =
1054                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1055                                         SysmonBlk);
1056
1057         /*
1058          * Read the Configuration Register 0 and derive the channel selection
1059          * bits.
1060          */
1061         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1062                                         XSYSMONPSU_CFG_REG0_OFFSET);
1063         RegValue &= XSYSMONPSU_CFG_REG0_MUX_CH_MASK;
1064
1065         return RegValue;
1066 }
1067
1068 /****************************************************************************/
1069 /**
1070 *
1071 * The function sets the frequency of the ADCCLK by configuring the DCLK to
1072 * ADCCLK ratio in the Configuration Register #2.
1073 *
1074 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1075 * @param        Divisor is clock divisor used to derive ADCCLK from DCLK.
1076 *               Valid values of the divisor are
1077 *               PS:
1078 *                - 0 means divide by 8.
1079 *                - 1,2 means divide by 2.
1080 *                - 3 to 255 means divide by that value.
1081 *       PL:
1082 *                - 0,1,2 means divide by 2.
1083 *                - 3 to 255 means divide by that value.
1084 *               Refer to the device specification for more details.
1085 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1086 *       block or PL Sysmon block register region.
1087 *
1088 * @return       None.
1089 *
1090 * @note         - The ADCCLK is an internal clock used by the ADC and is
1091 *               synchronized to the DCLK clock. The ADCCLK is equal to DCLK
1092 *               divided by the user selection in the Configuration Register 2.
1093 *               - There is no Assert on the minimum value of the Divisor.
1094 *
1095 *****************************************************************************/
1096 void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
1097             u32 SysmonBlk)
1098 {
1099         u32 RegValue;
1100         u32 EffectiveBaseAddress;
1101
1102         /* Assert the arguments. */
1103         Xil_AssertVoid(InstancePtr != NULL);
1104         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1105         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1106
1107         /* Calculate the effective baseaddress based on the Sysmon instance. */
1108         EffectiveBaseAddress =
1109                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1110                                         SysmonBlk);
1111
1112         /*
1113          * Read the Configuration Register 2 and the clear the clock divisor
1114          * bits.
1115          */
1116         RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1117                                         XSYSMONPSU_CFG_REG2_OFFSET);
1118         RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
1119
1120         /* Write the divisor value into the Configuration Register 2. */
1121         RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
1122                                         XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
1123         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
1124                          RegValue);
1125
1126 }
1127
1128 /****************************************************************************/
1129 /**
1130 *
1131 * The function gets the ADCCLK divisor from the Configuration Register 2.
1132 *
1133 * @param        InstancePtr is a pointer to the XSysMon instance.
1134 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1135 *       block or PL Sysmon block register region.
1136 *
1137 * @return       The divisor read from the Configuration Register 2.
1138 *
1139 * @note         The ADCCLK is an internal clock used by the ADC and is
1140 *               synchronized to the DCLK clock. The ADCCLK is equal to DCLK
1141 *               divided by the user selection in the Configuration Register 2.
1142 *
1143 *****************************************************************************/
1144 u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1145 {
1146         u16 Divisor;
1147         u32 EffectiveBaseAddress;
1148
1149         /* Assert the arguments. */
1150         Xil_AssertNonvoid(InstancePtr != NULL);
1151         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1152         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1153
1154         /* Calculate the effective baseaddress based on the Sysmon instance. */
1155         EffectiveBaseAddress =
1156                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1157                                         SysmonBlk);
1158
1159         /* Read the divisor value from the Configuration Register 2. */
1160         Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
1161                                                         XSYSMONPSU_CFG_REG2_OFFSET);
1162
1163         return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT);
1164 }
1165
1166 /****************************************************************************/
1167 /**
1168 *
1169 * This function enables the specified channels in the ADC Channel Selection
1170 * Sequencer Registers. The sequencer must be in the Safe Mode before writing
1171 * to these registers.
1172 *
1173 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1174 * @param        ChEnableMask is the bit mask of all the channels to be enabled.
1175 *               Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
1176 *               numbers. Bit masks of 1 will be enabled and bit mask of 0 will
1177 *               be disabled.
1178 *               The ChEnableMask is a 64 bit mask that is written to the three
1179 *               16 bit ADC Channel Selection Sequencer Registers.
1180 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1181 *       block or PL Sysmon block register region.
1182 *
1183 * @return
1184 *               - XST_SUCCESS if the given values were written successfully to
1185 *               the ADC Channel Selection Sequencer Registers.
1186 *               - XST_FAILURE if the channel sequencer is enabled.
1187 *
1188 * @note         None.
1189 *
1190 *****************************************************************************/
1191 s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
1192                 u32 SysmonBlk)
1193 {
1194         s32 Status;
1195         u32 EffectiveBaseAddress;
1196
1197         /* Assert the arguments. */
1198         Xil_AssertNonvoid(InstancePtr != NULL);
1199         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1200         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1201
1202         /*
1203          * The sequencer must be in the Default Safe Mode before writing
1204          * to these registers. Return XST_FAILURE if the channel sequencer
1205          * is enabled.
1206          */
1207         if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
1208                 Status = (s32)XST_FAILURE;
1209                 goto End;
1210         }
1211
1212         /* Calculate the effective baseaddress based on the Sysmon instance. */
1213         EffectiveBaseAddress =
1214                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1215                                         SysmonBlk);
1216
1217         /*
1218          * Enable the specified channels in the ADC Channel Selection Sequencer
1219          * Registers.
1220          */
1221         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
1222                          (ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));
1223
1224         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
1225                          (ChEnableMask >> XSM_SEQ_CH_SHIFT) &
1226                          XSYSMONPSU_SEQ_CH1_VALID_MASK);
1227
1228         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
1229                                  (ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
1230                          XSYSMONPSU_SEQ_CH2_VALID_MASK);
1231
1232         Status = (s32)XST_SUCCESS;
1233
1234 End:
1235         return Status;
1236 }
1237
1238 /****************************************************************************/
1239 /**
1240 *
1241 * This function gets the channel enable bits status from the ADC Channel
1242 * Selection Sequencer Registers.
1243 *
1244 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1245 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1246 *       block or PL Sysmon block register region.
1247 *
1248 * @return       Gets the channel enable bits. Use XSYSMONPSU_SEQ_CH* defined in
1249 *               xsysmonpsu_hw.h to interpret the Channel numbers. Bit masks of 1
1250 *               are the channels that are enabled and bit mask of 0 are
1251 *               the channels that are disabled.
1252 *
1253 * @return       None.
1254 *
1255 * @note         None.
1256 *
1257 *****************************************************************************/
1258 u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1259 {
1260         u64 RegVal;
1261         u32 EffectiveBaseAddress;
1262
1263         /* Assert the arguments. */
1264         Xil_AssertNonvoid(InstancePtr != NULL);
1265         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1266         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1267
1268         /* Calculate the effective baseaddress based on the Sysmon instance. */
1269         EffectiveBaseAddress =
1270                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1271                                         SysmonBlk);
1272
1273         /*
1274          * Read the channel enable bits for all the channels from the ADC
1275          * Channel Selection Register.
1276          */
1277         RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1278                         XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
1279         RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
1280                         XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
1281                                         XSM_SEQ_CH_SHIFT;
1282         RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
1283                         XSYSMONPSU_SEQ_CH2_OFFSET) &
1284                         XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
1285
1286         return RegVal;
1287 }
1288
1289 /****************************************************************************/
1290 /**
1291 *
1292 * This function enables the averaging for the specified channels in the ADC
1293 * Channel Averaging Enable Sequencer Registers. The sequencer must be in
1294 * the Safe Mode before writing to these registers.
1295 *
1296 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1297 * @param        AvgEnableChMask is the bit mask of all the channels for which
1298 *               averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
1299 *               xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
1300 *               enabled for bit masks of 1 and disabled for bit mask of 0.
1301 *               The AvgEnableChMask is a 64 bit mask that is written to the
1302 *               three 16 bit ADC Channel Averaging Enable Sequencer Registers.
1303 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1304 *       block or PL Sysmon block register region.
1305 *
1306 * @return
1307 *               - XST_SUCCESS if the given values were written successfully to
1308 *               the ADC Channel Averaging Enables Sequencer Registers.
1309 *               - XST_FAILURE if the channel sequencer is enabled.
1310 *
1311 * @note         None.
1312 *
1313 *****************************************************************************/
1314 s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
1315                 u32 SysmonBlk)
1316 {
1317         s32 Status;
1318         u32 EffectiveBaseAddress;
1319
1320         /* Assert the arguments. */
1321         Xil_AssertNonvoid(InstancePtr != NULL);
1322         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1323         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1324
1325         /*
1326          * The sequencer must be disabled for writing any of these registers.
1327          * Return XST_FAILURE if the channel sequencer is enabled.
1328          */
1329         if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
1330                                              != XSM_SEQ_MODE_SAFE)) {
1331                 Status = (s32)XST_FAILURE;
1332         } else {
1333                 /* Calculate the effective baseaddress based on the Sysmon instance. */
1334                 EffectiveBaseAddress =
1335                                 XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1336                                                 SysmonBlk);
1337                 /*
1338                  * Enable/disable the averaging for the specified channels in the
1339                  * ADC Channel Averaging Enables Sequencer Registers.
1340                  */
1341                 XSysmonPsu_WriteReg(EffectiveBaseAddress +
1342                                 XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
1343                                 (AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
1344
1345                 XSysmonPsu_WriteReg(EffectiveBaseAddress +
1346                                 XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
1347                                  (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
1348                                  XSYSMONPSU_SEQ_AVERAGE1_MASK);
1349
1350                 XSysmonPsu_WriteReg(EffectiveBaseAddress +
1351                                 XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
1352                                  (AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
1353                                  XSYSMONPSU_SEQ_AVERAGE2_MASK);
1354
1355                 Status = (s32)XST_SUCCESS;
1356         }
1357
1358         return Status;
1359 }
1360
1361 /****************************************************************************/
1362 /**
1363 *
1364 * This function returns the channels for which the averaging has been enabled
1365 * in the ADC Channel Averaging Enables Sequencer Registers.
1366 *
1367 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1368 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1369 *       block or PL Sysmon block register region.
1370 *
1371 * @returns      The status of averaging (enabled/disabled) for all the channels.
1372 *               Use XSYSMONPSU_SEQ_AVERAGE* defined in xsysmonpsu_hw.h to interpret the
1373 *               Channel numbers. Bit masks of 1 are the channels for which
1374 *               averaging is enabled and bit mask of 0 are the channels for
1375 *               averaging is disabled.
1376 *
1377 * @note         None.
1378 *
1379 *****************************************************************************/
1380 u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1381 {
1382         u64 RegVal;
1383         u32 EffectiveBaseAddress;
1384
1385         /* Assert the arguments. */
1386         Xil_AssertNonvoid(InstancePtr != NULL);
1387         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1388         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1389
1390         /* Calculate the effective baseaddress based on the Sysmon instance. */
1391         EffectiveBaseAddress =
1392                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1393                                         SysmonBlk);
1394
1395         /*
1396          * Read the averaging enable status for all the channels from the
1397          * ADC Channel Averaging Enables Sequencer Registers.
1398          */
1399         RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1400                         XSYSMONPSU_SEQ_AVERAGE0_OFFSET) & XSYSMONPSU_SEQ_AVERAGE0_MASK;
1401         RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
1402                         XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
1403                         XSM_SEQ_CH_SHIFT;
1404         RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
1405                         XSYSMONPSU_SEQ_AVERAGE2_OFFSET) &
1406                         XSYSMONPSU_SEQ_AVERAGE2_MASK) << XSM_SEQ_CH2_SHIFT;
1407
1408         return RegVal;
1409 }
1410
1411 /****************************************************************************/
1412 /**
1413 *
1414 * This function sets the Analog input mode for the specified channels in the
1415 * ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
1416 * the Safe Mode before writing to these registers.
1417 *
1418 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1419 * @param        InputModeChMask is the bit mask of all the channels for which
1420 *               the input mode is differential mode. Use XSYSMONPSU_SEQ_INPUT_MDE*
1421 *               defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
1422 *               or  Bipolar input mode will be set for bit masks of 1 and unipolar input
1423 *               mode for bit masks of 0.
1424 *               The InputModeChMask is a 64 bit mask that is written to the three
1425 *               16 bit ADC Channel Analog-Input Mode Sequencer Registers.
1426 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1427 *       block or PL Sysmon block register region.
1428 *
1429 * @return
1430 *               - XST_SUCCESS if the given values were written successfully to
1431 *               the ADC Channel Analog-Input Mode Sequencer Registers.
1432 *               - XST_FAILURE if the channel sequencer is enabled.
1433 *
1434 * @note         None.
1435 *
1436 *****************************************************************************/
1437 s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
1438                 u32 SysmonBlk)
1439 {
1440         s32 Status;
1441         u32 EffectiveBaseAddress;
1442
1443         /* Assert the arguments. */
1444         Xil_AssertNonvoid(InstancePtr != NULL);
1445         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1446         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1447
1448         /*
1449          * The sequencer must be in the Safe Mode before writing to
1450          * these registers. Return XST_FAILURE if the channel sequencer
1451          * is enabled.
1452          */
1453         if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
1454                                               != XSM_SEQ_MODE_SAFE)) {
1455                 Status = (s32)XST_FAILURE;
1456                 goto End;
1457         }
1458
1459         /* Calculate the effective baseaddress based on the Sysmon instance. */
1460         EffectiveBaseAddress =
1461                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1462                                         SysmonBlk);
1463
1464         /*
1465          * Set the input mode for the specified channels in the ADC Channel
1466          * Analog-Input Mode Sequencer Registers.
1467          */
1468         XSysmonPsu_WriteReg(EffectiveBaseAddress +
1469                         XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET,
1470                          (InputModeChMask & XSYSMONPSU_SEQ_INPUT_MDE0_MASK));
1471
1472         XSysmonPsu_WriteReg(EffectiveBaseAddress +
1473                         XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET,
1474                          (InputModeChMask >> XSM_SEQ_CH_SHIFT) &
1475                          XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
1476
1477         XSysmonPsu_WriteReg(EffectiveBaseAddress +
1478                 XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET,
1479                  (InputModeChMask >> XSM_SEQ_CH2_SHIFT) &
1480                  XSYSMONPSU_SEQ_INPUT_MDE2_MASK);
1481
1482         Status = (s32)XST_SUCCESS;
1483
1484 End:
1485         return Status;
1486 }
1487
1488 /****************************************************************************/
1489 /**
1490 *
1491 * This function gets the Analog input mode for all the channels from
1492 * the ADC Channel Analog-Input Mode Sequencer Registers.
1493 *
1494 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1495 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1496 *       block or PL Sysmon block register region.
1497 *
1498 * @returns      The input mode for all the channels.
1499 *               Use XSYSMONPSU_SEQ_INPUT_MDE* defined in xsysmonpsu_hw.h to interpret the
1500 *               Channel numbers. Bit masks of 1 are the channels for which
1501 *               input mode is differential/Bipolar and bit mask of 0 are the channels
1502 *               for which input mode is unipolar.
1503 *
1504 * @note         None.
1505 *
1506 *****************************************************************************/
1507 u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1508 {
1509         u64 InputMode;
1510         u32 EffectiveBaseAddress;
1511
1512         /* Assert the arguments. */
1513         Xil_AssertNonvoid(InstancePtr != NULL);
1514         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1515         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1516
1517         /* Calculate the effective baseaddress based on the Sysmon instance. */
1518         EffectiveBaseAddress =
1519                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1520                                         SysmonBlk);
1521
1522         /*
1523          *  Get the input mode for all the channels from the ADC Channel
1524          * Analog-Input Mode Sequencer Registers.
1525          */
1526         InputMode = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1527                         XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE0_MASK;
1528         InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
1529                         XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
1530                                 XSM_SEQ_CH_SHIFT;
1531         InputMode |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
1532                         XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET) &
1533                         XSYSMONPSU_SEQ_INPUT_MDE2_MASK) << XSM_SEQ_CH2_SHIFT;
1534
1535         return InputMode;
1536 }
1537
1538 /****************************************************************************/
1539 /**
1540 *
1541 * This function sets the number of Acquisition cycles in the ADC Channel
1542 * Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
1543 * before writing to these registers.
1544 *
1545 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1546 * @param        AcqCyclesChMask is the bit mask of all the channels for which
1547 *               the number of acquisition cycles is to be extended.
1548 *               Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to specify the Channel
1549 *               numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
1550 *               for bit masks of 1 and will be the default 4 ADCCLK cycles for
1551 *               bit masks of 0.
1552 *               The AcqCyclesChMask is a 64 bit mask that is written to the three
1553 *               16 bit ADC Channel Acquisition Time Sequencer Registers.
1554 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1555 *       block or PL Sysmon block register region.
1556 *
1557 * @return
1558 *               - XST_SUCCESS if the given values were written successfully to
1559 *               the Channel Sequencer Registers.
1560 *               - XST_FAILURE if the channel sequencer is enabled.
1561 *
1562 * @note         None.
1563 *
1564 *****************************************************************************/
1565 s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
1566                 u32 SysmonBlk)
1567 {
1568         s32 Status;
1569         u32 EffectiveBaseAddress;
1570
1571         /* Assert the arguments. */
1572         Xil_AssertNonvoid(InstancePtr != NULL);
1573         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1574         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1575
1576         /*
1577          * The sequencer must be in the Safe Mode before writing
1578          * to these registers. Return XST_FAILURE if the channel
1579          * sequencer is enabled.
1580          */
1581         if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
1582                                              != XSM_SEQ_MODE_SAFE)) {
1583                 Status = (s32)XST_FAILURE;
1584                 goto End;
1585         }
1586
1587         /* Calculate the effective baseaddress based on the Sysmon instance. */
1588         EffectiveBaseAddress =
1589                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1590                                         SysmonBlk);
1591
1592         /*
1593          * Set the Acquisition time for the specified channels in the
1594          * ADC Channel Acquisition Time Sequencer Registers.
1595          */
1596         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
1597                          (AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));
1598
1599         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
1600                          (AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
1601
1602         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
1603                         (AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
1604                                         XSYSMONPSU_SEQ_ACQ2_MASK);
1605
1606         Status = (s32)XST_SUCCESS;
1607
1608 End:
1609         return Status;
1610 }
1611
1612 /****************************************************************************/
1613 /**
1614 *
1615 * This function gets the status of acquisition time from the ADC Channel Acquisition
1616 * Time Sequencer Registers.
1617 *
1618 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1619 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1620 *       block or PL Sysmon block register region.
1621 *
1622 * @returns      The acquisition time for all the channels.
1623 *               Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to interpret the
1624 *               Channel numbers. Bit masks of 1 are the channels for which
1625 *               acquisition cycles are extended and bit mask of 0 are the
1626 *               channels for which acquisition cycles are not extended.
1627 *
1628 * @note         None.
1629 *
1630 *****************************************************************************/
1631 u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
1632 {
1633         u64 RegValAcq;
1634         u32 EffectiveBaseAddress;
1635
1636         /* Assert the arguments. */
1637         Xil_AssertNonvoid(InstancePtr != NULL);
1638         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1639         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1640
1641         /* Calculate the effective baseaddress based on the Sysmon instance. */
1642         EffectiveBaseAddress =
1643                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1644                                         SysmonBlk);
1645
1646         /*
1647          * Get the Acquisition cycles for the specified channels from the ADC
1648          * Channel Acquisition Time Sequencer Registers.
1649          */
1650         RegValAcq = XSysmonPsu_ReadReg(EffectiveBaseAddress +
1651                                         XSYSMONPSU_SEQ_ACQ0_OFFSET) & XSYSMONPSU_SEQ_ACQ0_MASK;
1652         RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
1653                                         XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
1654                                         XSM_SEQ_CH_SHIFT;
1655         RegValAcq |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
1656                         XSYSMONPSU_SEQ_ACQ2_OFFSET) &
1657                         XSYSMONPSU_SEQ_ACQ2_MASK) << XSM_SEQ_CH2_SHIFT;
1658
1659         return RegValAcq;
1660 }
1661
1662 /****************************************************************************/
1663 /**
1664 *
1665 * This functions sets the contents of the given Alarm Threshold Register.
1666 *
1667 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1668 * @param        AlarmThrReg is the index of an Alarm Threshold Register to
1669 *               be set. Use XSM_ATR_* constants defined in xsysmonpsu.h to
1670 *               specify the index.
1671 * @param        Value is the 16-bit threshold value to write into the register.
1672 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1673 *       block or PL Sysmon block register region.
1674 *
1675 * @return       None.
1676 *
1677 * @note         None.
1678 *
1679 *****************************************************************************/
1680 void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
1681                 u16 Value, u32 SysmonBlk)
1682 {
1683         u32 EffectiveBaseAddress;
1684
1685         /* Assert the arguments. */
1686         Xil_AssertVoid(InstancePtr != NULL);
1687         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1688         Xil_AssertVoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
1689                         ((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
1690                         (AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
1691         Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1692
1693         /* Calculate the effective baseaddress based on the Sysmon instance. */
1694         EffectiveBaseAddress =
1695                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1696                                         SysmonBlk);
1697
1698         /* Write the value into the specified Alarm Threshold Register. */
1699         XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_ALRM_TEMP_UPR_OFFSET +
1700                         ((u32)AlarmThrReg << 2U), Value);
1701 }
1702
1703 /****************************************************************************/
1704 /**
1705 *
1706 * This function returns the contents of the specified Alarm Threshold Register.
1707 *
1708 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1709 * @param        AlarmThrReg is the index of an Alarm Threshold Register
1710 *               to be read. Use XSM_ATR_* constants defined in xsysmonpsu.h
1711 *               to specify the index.
1712 * @param        SysmonBlk is the value that tells whether it is for PS Sysmon
1713 *       block or PL Sysmon block register region.
1714 *
1715 * @return       A 16-bit value representing the contents of the selected Alarm
1716 *               Threshold Register.
1717 *
1718 * @note         None.
1719 *
1720 *****************************************************************************/
1721 u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
1722                 u32 SysmonBlk)
1723 {
1724         u16 AlarmThreshold;
1725         u32 EffectiveBaseAddress;
1726
1727         /* Assert the arguments. */
1728         Xil_AssertNonvoid(InstancePtr != NULL);
1729         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1730         Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
1731                         ((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
1732                         (AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
1733         Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
1734
1735         /* Calculate the effective baseaddress based on the Sysmon instance. */
1736         EffectiveBaseAddress =
1737                         XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
1738                                         SysmonBlk);
1739
1740         /*
1741          * Read the specified Alarm Threshold Register and return
1742          * the value.
1743          */
1744         AlarmThreshold = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
1745                         XSYSMONPSU_ALRM_TEMP_UPR_OFFSET + ((u32)AlarmThrReg << 2));
1746
1747         return AlarmThreshold;
1748 }
1749
1750 /****************************************************************************/
1751 /**
1752 *
1753 * This function sets the conversion to be automatic for PS SysMon.
1754 *
1755 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1756 *
1757 * @return       None
1758 *
1759 * @note         In the auto-trigger mode, sample rate is of 1 Million samples.
1760 *
1761 *****************************************************************************/
1762 void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr)
1763 {
1764         u32 PSSysMonStatusReg;
1765
1766         /* Assert the arguments. */
1767         Xil_AssertVoid(InstancePtr != NULL);
1768         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1769
1770         /* Set the automatic conversion triggering in PS control register. */
1771         PSSysMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
1772                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
1773         PSSysMonStatusReg |= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK;
1774         XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
1775                         XSYSMONPSU_PS_SYSMON_CSTS_OFFSET, PSSysMonStatusReg);
1776 }
1777
1778 /****************************************************************************/
1779 /**
1780 *
1781 * This function gets the AMS monitor status.
1782 *
1783 * @param        InstancePtr is a pointer to the XSysMonPsu instance.
1784 *
1785 * @return       Returns the monitor status. See XSYSMONPSU_MON_STS_*_MASK
1786 *               definations present in xsysmonpsu_hw.h for knowing the status.
1787 *
1788 * @note         None
1789 * .
1790 *****************************************************************************/
1791 u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr)
1792 {
1793         u32 AMSMonStatusReg;
1794
1795         /* Assert the arguments. */
1796         Xil_AssertNonvoid(InstancePtr != NULL);
1797         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1798
1799         /*
1800          * Read the AMS monitor status. This gives tells about JTAG Locked / ADC
1801          * busy / ADC Current Channel number and its ADC output.
1802          */
1803         AMSMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
1804                         XSYSMONPSU_MON_STS_OFFSET);
1805
1806         return AMSMonStatusReg;
1807 }
1808
1809 /** @} */