1 /******************************************************************************
3 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
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6 * of this software and associated documentation files (the "Software"), to deal
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16 * (a) running on a Xilinx device, or
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24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup usbpsu_v1_3
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- ----- -------- -----------------------------------------------------
45 * 1.0 sg 06/16/16 First release
46 * 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed
47 * 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
49 * myk 12/01/18 Added hibernation support for device mode
52 *****************************************************************************/
54 /***************************** Include Files ********************************/
56 #include "xusb_wrapper.h"
58 /************************** Constant Definitions *****************************/
61 /**************************** Type Definitions *******************************/
64 /***************** Macros (Inline Functions) Definitions *********************/
67 /************************** Function Prototypes ******************************/
70 /************************** Variable Definitions *****************************/
72 /*****************************************************************************/
74 * Waits until a bit in a register is cleared or timeout occurs
76 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
77 * @param Offset is register offset.
78 * @param BitMask is bit mask of required bit to be checked.
79 * @param Timeout is the time to wait specified in micro seconds.
82 * - XST_SUCCESS when bit is cleared.
83 * - XST_FAILURE when timed out.
85 ******************************************************************************/
86 s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
87 u32 BitMask, u32 Timeout)
90 u32 LocalTimeout = Timeout;
93 RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
94 if ((RegVal & BitMask) == 0U) {
98 if (LocalTimeout == 0U) {
107 /*****************************************************************************/
109 * Waits until a bit in a register is set or timeout occurs
111 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
112 * @param Offset is register offset.
113 * @param BitMask is bit mask of required bit to be checked.
114 * @param Timeout is the time to wait specified in micro seconds.
117 * - XST_SUCCESS when bit is set.
118 * - XST_FAILURE when timed out.
120 ******************************************************************************/
121 s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
122 u32 BitMask, u32 Timeout)
125 u32 LocalTimeout = Timeout;
128 RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
129 if ((RegVal & BitMask) != 0U) {
133 if (LocalTimeout == 0U) {
142 /*****************************************************************************/
144 * Sets mode of Core to USB Device/Host/OTG.
147 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
148 * @param Mode is mode to set
149 * - XUSBPSU_GCTL_PRTCAP_OTG
150 * - XUSBPSU_GCTL_PRTCAP_HOST
151 * - XUSBPSU_GCTL_PRTCAP_DEVICE
155 ******************************************************************************/
156 void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
160 Xil_AssertVoid(InstancePtr != NULL);
161 Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
162 (Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
164 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
165 RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
166 RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
167 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
170 /*****************************************************************************/
172 * Issues core PHY reset.
174 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
178 ******************************************************************************/
179 void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
183 Xil_AssertVoid(InstancePtr != NULL);
185 /* Before Resetting PHY, put Core in Reset */
186 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
187 RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
188 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
190 /* Assert USB3 PHY reset */
191 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
192 RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
193 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
195 /* Assert USB2 PHY reset */
196 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
197 RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
198 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
200 XUsbSleep(XUSBPSU_PHY_TIMEOUT);
202 /* Clear USB3 PHY reset */
203 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
204 RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
205 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
207 /* Clear USB2 PHY reset */
208 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
209 RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
210 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
212 XUsbSleep(XUSBPSU_PHY_TIMEOUT);
214 /* Take Core out of reset state after PHYS are stable*/
215 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
216 RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
217 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
220 /*****************************************************************************/
222 * Sets up Event buffers so that events are written by Core.
224 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
228 ******************************************************************************/
229 void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
231 struct XUsbPsu_EvtBuffer *Evt;
233 Xil_AssertVoid(InstancePtr != NULL);
235 Evt = &InstancePtr->Evt;
236 Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
239 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
240 (UINTPTR)InstancePtr->EventBuffer);
241 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
242 ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
243 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
244 XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
245 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
248 /*****************************************************************************/
250 * Resets Event buffer Registers to zero so that events are not written by Core.
252 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
256 ******************************************************************************/
257 void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
260 Xil_AssertVoid(InstancePtr != NULL);
262 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
263 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
264 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
265 (u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
266 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
269 /*****************************************************************************/
271 * Reads data from Hardware Params Registers of Core.
273 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
274 * @param RegIndex is Register number to read
275 * - XUSBPSU_GHWPARAMS0
276 * - XUSBPSU_GHWPARAMS1
277 * - XUSBPSU_GHWPARAMS2
278 * - XUSBPSU_GHWPARAMS3
279 * - XUSBPSU_GHWPARAMS4
280 * - XUSBPSU_GHWPARAMS5
281 * - XUSBPSU_GHWPARAMS6
282 * - XUSBPSU_GHWPARAMS7
284 * @return One of the GHWPARAMS RegValister contents.
286 ******************************************************************************/
287 u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
291 Xil_AssertNonvoid(InstancePtr != NULL);
292 Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
294 RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
295 ((u32)RegIndex * (u32)4)));
299 /*****************************************************************************/
303 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
306 * - XST_SUCCESS if initialization was successful
307 * - XST_FAILURE if initialization was not successful
309 ******************************************************************************/
310 s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
315 /* issue device SoftReset too */
316 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
318 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
319 XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
320 /* timed out return failure */
324 XUsbPsu_PhyReset(InstancePtr);
326 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
327 RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
328 RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
329 RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
331 Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
333 switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
334 case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
335 RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
338 case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
339 /* enable hibernation here */
340 #ifdef XUSBPSU_HIBERNATION_ENABLE
341 RegVal |= XUSBPSU_GCTL_GBLHIBERNATIONEN;
342 InstancePtr->HasHibernation = 1;
347 /* Made for Misra-C Compliance. */
351 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
353 #ifdef XUSBPSU_HIBERNATION_ENABLE
354 if (InstancePtr->HasHibernation)
355 XUsbPsu_InitHibernation(InstancePtr);
361 /*****************************************************************************/
363 * Enables an interrupt in Event Enable RegValister.
365 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
366 * @param Mask is the OR of any Interrupt Enable Masks:
367 * - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
368 * - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
369 * - XUSBPSU_DEVTEN_CMDCMPLTEN
370 * - XUSBPSU_DEVTEN_ERRTICERREN
371 * - XUSBPSU_DEVTEN_SOFEN
372 * - XUSBPSU_DEVTEN_EOPFEN
373 * - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
374 * - XUSBPSU_DEVTEN_WKUPEVTEN
375 * - XUSBPSU_DEVTEN_ULSTCNGEN
376 * - XUSBPSU_DEVTEN_CONNECTDONEEN
377 * - XUSBPSU_DEVTEN_USBRSTEN
378 * - XUSBPSU_DEVTEN_DISCONNEVTEN
382 ******************************************************************************/
383 void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
387 Xil_AssertVoid(InstancePtr != NULL);
389 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
392 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
395 /*****************************************************************************/
397 * Disables an interrupt in Event Enable RegValister.
399 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
400 * @param Mask is the OR of Interrupt Enable Masks
401 * - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
402 * - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
403 * - XUSBPSU_DEVTEN_CMDCMPLTEN
404 * - XUSBPSU_DEVTEN_ERRTICERREN
405 * - XUSBPSU_DEVTEN_SOFEN
406 * - XUSBPSU_DEVTEN_EOPFEN
407 * - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
408 * - XUSBPSU_DEVTEN_WKUPEVTEN
409 * - XUSBPSU_DEVTEN_ULSTCNGEN
410 * - XUSBPSU_DEVTEN_CONNECTDONEEN
411 * - XUSBPSU_DEVTEN_USBRSTEN
412 * - XUSBPSU_DEVTEN_DISCONNEVTEN
416 ******************************************************************************/
417 void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
421 Xil_AssertVoid(InstancePtr != NULL);
423 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
425 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
428 /****************************************************************************/
431 * This function does the following:
432 * - initializes a specific XUsbPsu instance.
433 * - sets up Event Buffer for Core to write events.
434 * - Core Reset and PHY Reset.
435 * - Sets core in Device Mode.
436 * - Sets default speed as HIGH_SPEED.
437 * - Sets Device Address to 0.
438 * - Enables interrupts.
440 * @param InstancePtr is a pointer to the XUsbPsu instance.
441 * @param ConfigPtr points to the XUsbPsu device configuration structure.
442 * @param BaseAddress is the device base address in the virtual memory
443 * address space. If the address translation is not used then the
444 * physical address is passed.
445 * Unexpected errors may occur if the address mapping is changed
446 * after this function is invoked.
448 * @return XST_SUCCESS else XST_FAILURE
452 *****************************************************************************/
453 s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
454 XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
460 Xil_AssertNonvoid(InstancePtr != NULL);
461 Xil_AssertNonvoid(ConfigPtr != NULL);
462 Xil_AssertNonvoid(BaseAddress != 0U)
464 InstancePtr->ConfigPtr = ConfigPtr;
466 Status = XUsbPsu_CoreInit(InstancePtr);
467 if (Status != XST_SUCCESS) {
469 xil_printf("Core initialization failed\r\n");
474 RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
475 InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
476 InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
477 InstancePtr->NumInEps);
479 /* Map USB and Physical Endpoints */
480 XUsbPsu_InitializeEps(InstancePtr);
482 XUsbPsu_EventBuffersSetup(InstancePtr);
484 XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
487 * Setting to max speed to support SS and HS
489 XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
491 (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
496 /****************************************************************************/
499 * Starts the controller so that Host can detect this device.
501 * @param InstancePtr is a pointer to the XUsbPsu instance.
503 * @return XST_SUCCESS else XST_FAILURE
507 *****************************************************************************/
508 s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
512 Xil_AssertNonvoid(InstancePtr != NULL);
514 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
516 RegVal |= XUSBPSU_DCTL_RUN_STOP;
518 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
520 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
521 XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
528 /****************************************************************************/
531 * Stops the controller so that Device disconnects from Host.
533 * @param InstancePtr is a pointer to the XUsbPsu instance.
535 * @return XST_SUCCESS else XST_FAILURE
539 *****************************************************************************/
540 s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
544 Xil_AssertNonvoid(InstancePtr != NULL);
546 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
547 RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
549 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
551 if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
552 XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
559 /****************************************************************************/
561 * Enables USB2 Test Modes
563 * @param InstancePtr is a pointer to the XUsbPsu instance.
564 * @param Mode is Test mode to set.
566 * @return XST_SUCCESS else XST_FAILURE
570 ****************************************************************************/
571 s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
574 s32 Status = XST_SUCCESS;
576 Xil_AssertNonvoid(InstancePtr != NULL);
577 Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
578 && (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
580 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
581 RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
586 case XUSBPSU_TEST_SE0_NAK:
587 case XUSBPSU_TEST_PACKET:
588 case XUSBPSU_TEST_FORCE_ENABLE:
589 RegVal |= (u32)Mode << 1;
593 Status = (s32)XST_FAILURE;
597 if (Status != (s32)XST_FAILURE) {
598 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
599 Status = XST_SUCCESS;
605 /****************************************************************************/
607 * Gets current State of USB Link
609 * @param InstancePtr is a pointer to the XUsbPsu instance.
615 ****************************************************************************/
616 XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
620 Xil_AssertNonvoid(InstancePtr != NULL);
622 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
624 return XUSBPSU_DSTS_USBLNKST(RegVal);
627 /****************************************************************************/
629 * Sets USB Link to a particular State
631 * @param InstancePtr is a pointer to the XUsbPsu instance.
632 * @param State is State of Link to set.
634 * @return XST_SUCCESS else XST_FAILURE
638 ****************************************************************************/
639 s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
640 XusbPsuLinkStateChange State)
644 Xil_AssertNonvoid(InstancePtr != NULL);
646 /* Wait until device controller is ready. */
647 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
648 XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
652 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
653 RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
655 RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
656 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
661 /****************************************************************************/
663 * Sets speed of the Core for connecting to Host
665 * @param InstancePtr is a pointer to the XUsbPsu instance.
666 * @param Speed is required speed
667 * - XUSBPSU_DCFG_HIGHSPEED
668 * - XUSBPSU_DCFG_FULLSPEED2
669 * - XUSBPSU_DCFG_LOWSPEED
670 * - XUSBPSU_DCFG_FULLSPEED1
676 *****************************************************************************/
677 void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
681 Xil_AssertVoid(InstancePtr != NULL);
682 Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
684 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
685 RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
687 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
690 /****************************************************************************/
692 * Sets Device Address of the Core
694 * @param InstancePtr is a pointer to the XUsbPsu instance.
695 * @param Addr is address to set.
697 * @return XST_SUCCESS else XST_FAILURE
701 *****************************************************************************/
702 s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
706 Xil_AssertNonvoid(InstancePtr != NULL);
707 Xil_AssertNonvoid(Addr <= 127U);
709 if (InstancePtr->AppData->State == XUSBPSU_STATE_CONFIGURED) {
713 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
714 RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
715 RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
716 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
719 InstancePtr->AppData->State = XUSBPSU_STATE_ADDRESS;
722 InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT;
728 /****************************************************************************/
730 * Set U1 sleep timeout
732 * @param InstancePtr is a pointer to the XUsbPsu instance.
733 * @param Sleep is time in microseconds
735 * @return XST_SUCCESS else XST_FAILURE
739 *****************************************************************************/
740 s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
744 Xil_AssertNonvoid(InstancePtr != NULL);
746 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
747 RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
748 RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
749 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
754 /****************************************************************************/
756 * Set U2 sleep timeout
758 * @param InstancePtr is a pointer to the XUsbPsu instance.
759 * @param Sleep is time in microseconds
761 * @return XST_SUCCESS else XST_FAILURE
765 *****************************************************************************/
766 s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
770 Xil_AssertNonvoid(InstancePtr != NULL);
772 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
773 RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
774 RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
775 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
779 /****************************************************************************/
781 * Enable Accept U1 and U2 sleep enable
783 * @param InstancePtr is a pointer to the XUsbPsu instance.
785 * @return XST_SUCCESS else XST_FAILURE
789 *****************************************************************************/
790 s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
794 Xil_AssertNonvoid(InstancePtr != NULL);
796 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
797 RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
798 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
803 /****************************************************************************/
805 * Enable U1 enable sleep
807 * @param InstancePtr is a pointer to the XUsbPsu instance.
809 * @return XST_SUCCESS else XST_FAILURE
813 *****************************************************************************/
814 s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
818 Xil_AssertNonvoid(InstancePtr != NULL);
820 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
821 RegVal |= XUSBPSU_DCTL_INITU1ENA;
822 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
827 /****************************************************************************/
829 * Enable U2 enable sleep
831 * @param InstancePtr is a pointer to the XUsbPsu instance.
833 * @return XST_SUCCESS else XST_FAILURE
837 *****************************************************************************/
838 s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
842 Xil_AssertNonvoid(InstancePtr != NULL);
844 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
845 RegVal |= XUSBPSU_DCTL_INITU2ENA;
846 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
851 /****************************************************************************/
853 * Enable U1 disable sleep
855 * @param InstancePtr is a pointer to the XUsbPsu instance.
857 * @return XST_SUCCESS else XST_FAILURE
861 *****************************************************************************/
862 s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
866 Xil_AssertNonvoid(InstancePtr != NULL);
868 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
869 RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
870 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
875 /****************************************************************************/
877 * Enable U2 disable sleep
879 * @param InstancePtr is a pointer to the XUsbPsu instance.
881 * @return XST_SUCCESS else XST_FAILURE
885 *****************************************************************************/
886 s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
890 Xil_AssertNonvoid(InstancePtr != NULL);
892 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
893 RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
894 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);