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32 /*****************************************************************************/
35 * @file xusbps_endpoint.h
36 * @addtogroup usbpsu_v1_3
39 * This is an internal file containing the definitions for endpoints. It is
40 * included by the xusbps_endpoint.c which is implementing the endpoint
41 * functions and by xusbps_intr.c.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- --------------------------------------------------------
48 * 1.0 sg 06/06/16 First release
49 * 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code
54 ******************************************************************************/
55 #ifndef XUSBPSU_ENDPOINT_H
56 #define XUSBPSU_ENDPOINT_H
62 /***************************** Include Files *********************************/
64 #include "xil_cache.h"
65 #include "xusb_wrapper.h"
66 #include "xil_types.h"
68 /**************************** Type Definitions *******************************/
70 /************************** Constant Definitions *****************************/
72 /* Device Generic Command Register */
73 #define XUSBPSU_DGCMD_SET_LMP 0x00000001U
74 #define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x00000002U
75 #define XUSBPSU_DGCMD_XMIT_FUNCTION 0x00000003U
77 /* These apply for core versions 1.94a and later */
78 #define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x00000004U
79 #define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x00000005U
81 #define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x00000009U
82 #define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0000000aU
83 #define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0000000cU
84 #define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x00000010U
86 #define XUSBPSU_DGCMD_STATUS(n) (((u32)(n) >> 15) & 1)
87 #define XUSBPSU_DGCMD_CMDACT (0x00000001U << 10)
88 #define XUSBPSU_DGCMD_CMDIOC (0x00000001U << 8)
90 /* Device Generic Command Parameter Register */
91 #define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (0x00000001U << 0)
92 #define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((u32)(n) << 0)
93 #define XUSBPSU_DGCMDPAR_RX_FIFO (0x00000000U << 5)
94 #define XUSBPSU_DGCMDPAR_TX_FIFO (0x00000001U << 5)
95 #define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0x00000000U << 0)
96 #define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (0x00000001U << 0)
98 /* Device Endpoint Command Register */
99 #define XUSBPSU_DEPCMD_PARAM_SHIFT 16U
100 #define XUSBPSU_DEPCMD_PARAM(x) ((u32)(x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
101 #define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((u32)(x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
103 #define XUSBPSU_DEPCMD_STATUS(x) (((u32)(x) >> 12) & (u32)0xF)
104 #define XUSBPSU_DEPCMD_HIPRI_FORCERM (0x00000001U << 11)
105 #define XUSBPSU_DEPCMD_CMDACT (0x00000001U << 10)
106 #define XUSBPSU_DEPCMD_CMDIOC (0x00000001U << 8)
108 #define XUSBPSU_DEPCMD_DEPSTARTCFG 0x00000009U
109 #define XUSBPSU_DEPCMD_ENDTRANSFER 0x00000008U
110 #define XUSBPSU_DEPCMD_UPDATETRANSFER 0x00000007U
111 #define XUSBPSU_DEPCMD_STARTTRANSFER 0x00000006U
112 #define XUSBPSU_DEPCMD_CLEARSTALL 0x00000005U
113 #define XUSBPSU_DEPCMD_SETSTALL 0x00000004U
114 #define XUSBPSU_DEPCMD_GETEPSTATE 0x00000003U
115 #define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x00000002U
116 #define XUSBPSU_DEPCMD_SETEPCONFIG 0x00000001U
118 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
119 #define XUSBPSU_DALEPENA_EP(n) (0x00000001U << (n))
121 #define XUSBPSU_DEPCFG_INT_NUM(n) ((u32)(n) << 0)
122 #define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (0x00000001U << 8)
123 #define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (0x00000001U << 9)
124 #define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (0x00000001U << 10)
125 #define XUSBPSU_DEPCFG_FIFO_ERROR_EN (0x00000001U << 11)
126 #define XUSBPSU_DEPCFG_STREAM_EVENT_EN (0x00000001U << 13)
127 #define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((u32)(n) << 16)
128 #define XUSBPSU_DEPCFG_STREAM_CAPABLE (0x00000001U << 24)
129 #define XUSBPSU_DEPCFG_EP_NUMBER(n) ((u32)(n) << 25)
130 #define XUSBPSU_DEPCFG_BULK_BASED (0x00000001U << 30)
131 #define XUSBPSU_DEPCFG_FIFO_BASED (0x00000001U << 31)
133 /* DEPCFG parameter 0 */
134 #define XUSBPSU_DEPCFG_EP_TYPE(n) ((u32)(n) << 1)
135 #define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((u32)(n) << 3)
136 #define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((u32)(n) << 17)
137 #define XUSBPSU_DEPCFG_BURST_SIZE(n) ((u32)(n) << 22)
138 #define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((u32)(n) << 26)
139 /* This applies for core versions earlier than 1.94a */
140 #define XUSBPSU_DEPCFG_IGN_SEQ_NUM (0x00000001U << 31)
141 /* These apply for core versions 1.94a and later */
142 #define XUSBPSU_DEPCFG_ACTION_INIT (0x00000000U << 30)
143 #define XUSBPSU_DEPCFG_ACTION_RESTORE (0x00000001U << 30)
144 #define XUSBPSU_DEPCFG_ACTION_MODIFY (0x00000002U << 30)
146 /* DEPXFERCFG parameter 0 */
147 #define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((u32)(n) & (u32)0xffff)
149 #define XUSBPSU_DEPCMD_TYPE_BULK 2U
150 #define XUSBPSU_DEPCMD_TYPE_INTR 3U
152 /* TRB Length, PCM and Status */
153 #define XUSBPSU_TRB_SIZE_MASK (0x00ffffffU)
154 #define XUSBPSU_TRB_SIZE_LENGTH(n) ((u32)(n) & XUSBPSU_TRB_SIZE_MASK)
155 #define XUSBPSU_TRB_SIZE_PCM1(n) (((u32)(n) & (u32)0x03) << 24)
156 #define XUSBPSU_TRB_SIZE_TRBSTS(n) (((u32)(n) & ((u32)0x0f << 28)) >> 28)
158 #define XUSBPSU_TRBSTS_OK 0U
159 #define XUSBPSU_TRBSTS_MISSED_ISOC 1U
160 #define XUSBPSU_TRBSTS_SETUP_PENDING 2U
161 #define XUSBPSU_TRB_STS_XFER_IN_PROG 4U
164 #define XUSBPSU_TRB_CTRL_HWO ((u32)0x00000001U << 0)
165 #define XUSBPSU_TRB_CTRL_LST ((u32)0x00000001U << 1)
166 #define XUSBPSU_TRB_CTRL_CHN ((u32)0x00000001U << 2)
167 #define XUSBPSU_TRB_CTRL_CSP ((u32)0x00000001U << 3)
168 #define XUSBPSU_TRB_CTRL_TRBCTL(n) (((u32)(n) & (u32)0x3f) << 4)
169 #define XUSBPSU_TRB_CTRL_ISP_IMI (0x00000001U << 10)
170 #define XUSBPSU_TRB_CTRL_IOC (0x00000001U << 11)
171 #define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((u32)(n) & (u32)0xffff) << 14)
173 #define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1)
174 #define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2)
175 #define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3)
176 #define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4)
177 #define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5)
178 #define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6)
179 #define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7)
180 #define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8)
186 #endif /* XUSBPSU_ENDPOINT_H */