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32 /****************************************************************************/
36 * @addtogroup wdtps_v3_0
39 * This file contains the hardware interface to the System Watch Dog Timer (WDT).
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ------ -------- ---------------------------------------------
46 * 1.00a ecm/jz 01/15/10 First release
47 * 1.02a sg 07/15/12 Removed defines related to External Signal
48 * Length functionality for CR 658287
49 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
52 ******************************************************************************/
53 #ifndef XWDTPS_HW_H /* prevent circular inclusions */
54 #define XWDTPS_HW_H /* by using protection macros */
60 /***************************** Include Files *********************************/
62 #include "xil_types.h"
63 #include "xil_assert.h"
66 /************************** Constant Definitions *****************************/
68 /** @name Register Map
69 * Offsets of registers from the start of the device
73 #define XWDTPS_ZMR_OFFSET 0x00000000U /**< Zero Mode Register */
74 #define XWDTPS_CCR_OFFSET 0x00000004U /**< Counter Control Register */
75 #define XWDTPS_RESTART_OFFSET 0x00000008U /**< Restart Register */
76 #define XWDTPS_SR_OFFSET 0x0000000CU /**< Status Register */
80 /** @name Zero Mode Register
81 * This register controls how the time out is indicated and also contains
82 * the access code (0xABC) to allow writes to the register
85 #define XWDTPS_ZMR_WDEN_MASK 0x00000001U /**< enable the WDT */
86 #define XWDTPS_ZMR_RSTEN_MASK 0x00000002U /**< enable the reset output */
87 #define XWDTPS_ZMR_IRQEN_MASK 0x00000004U /**< enable the IRQ output */
89 #define XWDTPS_ZMR_RSTLN_MASK 0x00000070U /**< set length of reset pulse */
90 #define XWDTPS_ZMR_RSTLN_SHIFT 4U /**< shift for reset pulse */
92 #define XWDTPS_ZMR_IRQLN_MASK 0x00000180U /**< set length of interrupt pulse */
93 #define XWDTPS_ZMR_IRQLN_SHIFT 7U /**< shift for interrupt pulse */
95 #define XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U /**< mask for writing access key */
96 #define XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U /**< access key, 0xABC << 12 */
100 /** @name Counter Control register
101 * This register controls how fast the timer runs and the reset value
102 * and also contains the access code (0x248) to allow writes to the
107 #define XWDTPS_CCR_CLKSEL_MASK 0x00000003U /**< counter clock prescale */
109 #define XWDTPS_CCR_CRV_MASK 0x00003FFCU /**< counter reset value */
110 #define XWDTPS_CCR_CRV_SHIFT 2U /**< shift for writing value */
112 #define XWDTPS_CCR_CKEY_MASK 0x03FFC000U /**< mask for writing access key */
113 #define XWDTPS_CCR_CKEY_VAL 0x00920000U /**< access key, 0x248 << 14 */
115 /* Bit patterns for Clock prescale divider values */
117 #define XWDTPS_CCR_PSCALE_0008 0x00000000U /**< divide clock by 8 */
118 #define XWDTPS_CCR_PSCALE_0064 0x00000001U /**< divide clock by 64 */
119 #define XWDTPS_CCR_PSCALE_0512 0x00000002U /**< divide clock by 512 */
120 #define XWDTPS_CCR_PSCALE_4096 0x00000003U /**< divide clock by 4096 */
124 /** @name Restart register
125 * This register resets the timer preventing a timeout. Value is specific
130 #define XWDTPS_RESTART_KEY_VAL 0x00001999U /**< valid key */
134 /** @name Status register
135 * This register indicates timer reached zero count.
138 #define XWDTPS_SR_WDZ_MASK 0x00000001U /**< time out occurred */
142 /**************************** Type Definitions *******************************/
145 /***************** Macros (Inline Functions) Definitions *********************/
147 /****************************************************************************/
150 * Read the given register.
152 * @param BaseAddress is the base address of the device
153 * @param RegOffset is the register offset to be read
155 * @return The 32-bit value of the register
157 * @note C-style signature:
158 * u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset)
160 *****************************************************************************/
161 #define XWdtPs_ReadReg(BaseAddress, RegOffset) \
162 Xil_In32((BaseAddress) + (u32)(RegOffset))
164 /****************************************************************************/
167 * Write the given register.
169 * @param BaseAddress is the base address of the device
170 * @param RegOffset is the register offset to be written
171 * @param Data is the 32-bit value to write to the register
175 * @note C-style signature:
176 * void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
178 *****************************************************************************/
179 #define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \
180 Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
183 /************************** Function Prototypes ******************************/
186 /************************** Variable Definitions *****************************/