git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c

   1 \r
   2 /*******************************************************************\r
   3 *\r
   4 * CAUTION: This file is automatically generated by HSI.\r
   5 * Version: \r
   6 * DO NOT EDIT.\r
   7 *\r
   8 * Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*\r
   9 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
  10 *of this software and associated documentation files (the Software), to deal\r
  11 *in the Software without restriction, including without limitation the rights\r
  12 *to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
  13 *copies of the Software, and to permit persons to whom the Software is\r
  14 *furnished to do so, subject to the following conditions:\r
  15 *\r
  16 *The above copyright notice and this permission notice shall be included in\r
  17 *all copies or substantial portions of the Software.\r
  18 * \r
  19 * Use of the Software is limited solely to applications:\r
  20 *(a) running on a Xilinx device, or\r
  21 *(b) that interact with a Xilinx device through a bus or interconnect.\r
  22 *\r
  23 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  24 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
  25 *FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
  26 *XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
  27 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
  28 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  29 *\r
  30 *Except as contained in this notice, the name of the Xilinx shall not be used\r
  31 *in advertising or otherwise to promote the sale, use or other dealings in\r
  32 *this Software without prior written authorization from Xilinx.\r
  33 *\r
  34 \r
  35 * \r
  36 * Description: Driver configuration\r
  37 *\r
  38 *******************************************************************/\r
  39 \r
  40 #include "xparameters.h"\r
  41 #include "xzdma.h"\r
  42 \r
  43 /*\r
  44 * The configuration table for devices\r
  45 */\r
  46 \r
  47 XZDma_Config XZDma_ConfigTable[] =\r
  48 {\r
  49         {\r
  50                 XPAR_PSU_ADMA_0_DEVICE_ID,\r
  51                 XPAR_PSU_ADMA_0_BASEADDR,\r
  52                 XPAR_PSU_ADMA_0_DMA_MODE\r
  53         },\r
  54         {\r
  55                 XPAR_PSU_ADMA_1_DEVICE_ID,\r
  56                 XPAR_PSU_ADMA_1_BASEADDR,\r
  57                 XPAR_PSU_ADMA_1_DMA_MODE\r
  58         },\r
  59         {\r
  60                 XPAR_PSU_ADMA_2_DEVICE_ID,\r
  61                 XPAR_PSU_ADMA_2_BASEADDR,\r
  62                 XPAR_PSU_ADMA_2_DMA_MODE\r
  63         },\r
  64         {\r
  65                 XPAR_PSU_ADMA_3_DEVICE_ID,\r
  66                 XPAR_PSU_ADMA_3_BASEADDR,\r
  67                 XPAR_PSU_ADMA_3_DMA_MODE\r
  68         },\r
  69         {\r
  70                 XPAR_PSU_ADMA_4_DEVICE_ID,\r
  71                 XPAR_PSU_ADMA_4_BASEADDR,\r
  72                 XPAR_PSU_ADMA_4_DMA_MODE\r
  73         },\r
  74         {\r
  75                 XPAR_PSU_ADMA_5_DEVICE_ID,\r
  76                 XPAR_PSU_ADMA_5_BASEADDR,\r
  77                 XPAR_PSU_ADMA_5_DMA_MODE\r
  78         },\r
  79         {\r
  80                 XPAR_PSU_ADMA_6_DEVICE_ID,\r
  81                 XPAR_PSU_ADMA_6_BASEADDR,\r
  82                 XPAR_PSU_ADMA_6_DMA_MODE\r
  83         },\r
  84         {\r
  85                 XPAR_PSU_ADMA_7_DEVICE_ID,\r
  86                 XPAR_PSU_ADMA_7_BASEADDR,\r
  87                 XPAR_PSU_ADMA_7_DMA_MODE\r
  88         },\r
  89         {\r
  90                 XPAR_PSU_GDMA_0_DEVICE_ID,\r
  91                 XPAR_PSU_GDMA_0_BASEADDR,\r
  92                 XPAR_PSU_GDMA_0_DMA_MODE\r
  93         },\r
  94         {\r
  95                 XPAR_PSU_GDMA_1_DEVICE_ID,\r
  96                 XPAR_PSU_GDMA_1_BASEADDR,\r
  97                 XPAR_PSU_GDMA_1_DMA_MODE\r
  98         },\r
  99         {\r
 100                 XPAR_PSU_GDMA_2_DEVICE_ID,\r
 101                 XPAR_PSU_GDMA_2_BASEADDR,\r
 102                 XPAR_PSU_GDMA_2_DMA_MODE\r
 103         },\r
 104         {\r
 105                 XPAR_PSU_GDMA_3_DEVICE_ID,\r
 106                 XPAR_PSU_GDMA_3_BASEADDR,\r
 107                 XPAR_PSU_GDMA_3_DMA_MODE\r
 108         },\r
 109         {\r
 110                 XPAR_PSU_GDMA_4_DEVICE_ID,\r
 111                 XPAR_PSU_GDMA_4_BASEADDR,\r
 112                 XPAR_PSU_GDMA_4_DMA_MODE\r
 113         },\r
 114         {\r
 115                 XPAR_PSU_GDMA_5_DEVICE_ID,\r
 116                 XPAR_PSU_GDMA_5_BASEADDR,\r
 117                 XPAR_PSU_GDMA_5_DMA_MODE\r
 118         },\r
 119         {\r
 120                 XPAR_PSU_GDMA_6_DEVICE_ID,\r
 121                 XPAR_PSU_GDMA_6_BASEADDR,\r
 122                 XPAR_PSU_GDMA_6_DMA_MODE\r
 123         },\r
 124         {\r
 125                 XPAR_PSU_GDMA_7_DEVICE_ID,\r
 126                 XPAR_PSU_GDMA_7_BASEADDR,\r
 127                 XPAR_PSU_GDMA_7_DMA_MODE\r
 128         }\r
 129 };\r
 130 \r
 131 \r