git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  22 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /****************************************************************************/
  33 /**
  34 *
  35 * @file psu_init.h
  36 *
  37 * This file is automatically generated
  38 *
  39 *****************************************************************************/
  40
  41
  42 #undef CRL_APB_RPLL_CFG_OFFSET
  43 #define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
  44 #undef CRL_APB_RPLL_CTRL_OFFSET
  45 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  46 #undef CRL_APB_RPLL_CTRL_OFFSET
  47 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  48 #undef CRL_APB_RPLL_CTRL_OFFSET
  49 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  50 #undef CRL_APB_RPLL_CTRL_OFFSET
  51 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  52 #undef CRL_APB_RPLL_CTRL_OFFSET
  53 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
  54 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
  55 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
  56 #undef CRL_APB_RPLL_FRAC_CFG_OFFSET
  57 #define CRL_APB_RPLL_FRAC_CFG_OFFSET                                               0XFF5E0038
  58 #undef CRL_APB_IOPLL_CFG_OFFSET
  59 #define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
  60 #undef CRL_APB_IOPLL_CTRL_OFFSET
  61 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  62 #undef CRL_APB_IOPLL_CTRL_OFFSET
  63 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  64 #undef CRL_APB_IOPLL_CTRL_OFFSET
  65 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  66 #undef CRL_APB_IOPLL_CTRL_OFFSET
  67 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  68 #undef CRL_APB_IOPLL_CTRL_OFFSET
  69 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
  70 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
  71 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
  72 #undef CRL_APB_IOPLL_FRAC_CFG_OFFSET
  73 #define CRL_APB_IOPLL_FRAC_CFG_OFFSET                                              0XFF5E0028
  74 #undef CRF_APB_APLL_CFG_OFFSET
  75 #define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
  76 #undef CRF_APB_APLL_CTRL_OFFSET
  77 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  78 #undef CRF_APB_APLL_CTRL_OFFSET
  79 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  80 #undef CRF_APB_APLL_CTRL_OFFSET
  81 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  82 #undef CRF_APB_APLL_CTRL_OFFSET
  83 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  84 #undef CRF_APB_APLL_CTRL_OFFSET
  85 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
  86 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
  87 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
  88 #undef CRF_APB_APLL_FRAC_CFG_OFFSET
  89 #define CRF_APB_APLL_FRAC_CFG_OFFSET                                               0XFD1A0028
  90 #undef CRF_APB_DPLL_CFG_OFFSET
  91 #define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
  92 #undef CRF_APB_DPLL_CTRL_OFFSET
  93 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  94 #undef CRF_APB_DPLL_CTRL_OFFSET
  95 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  96 #undef CRF_APB_DPLL_CTRL_OFFSET
  97 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
  98 #undef CRF_APB_DPLL_CTRL_OFFSET
  99 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
 100 #undef CRF_APB_DPLL_CTRL_OFFSET
 101 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
 102 #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
 103 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
 104 #undef CRF_APB_DPLL_FRAC_CFG_OFFSET
 105 #define CRF_APB_DPLL_FRAC_CFG_OFFSET                                               0XFD1A0034
 106 #undef CRF_APB_VPLL_CFG_OFFSET
 107 #define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
 108 #undef CRF_APB_VPLL_CTRL_OFFSET
 109 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 110 #undef CRF_APB_VPLL_CTRL_OFFSET
 111 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 112 #undef CRF_APB_VPLL_CTRL_OFFSET
 113 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 114 #undef CRF_APB_VPLL_CTRL_OFFSET
 115 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 116 #undef CRF_APB_VPLL_CTRL_OFFSET
 117 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
 118 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
 119 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
 120 #undef CRF_APB_VPLL_FRAC_CFG_OFFSET
 121 #define CRF_APB_VPLL_FRAC_CFG_OFFSET                                               0XFD1A0040
 122
 123 /*PLL loop filter resistor control*/
 124 #undef CRL_APB_RPLL_CFG_RES_DEFVAL
 125 #undef CRL_APB_RPLL_CFG_RES_SHIFT
 126 #undef CRL_APB_RPLL_CFG_RES_MASK
 127 #define CRL_APB_RPLL_CFG_RES_DEFVAL                                                0x00000000
 128 #define CRL_APB_RPLL_CFG_RES_SHIFT                                                 0
 129 #define CRL_APB_RPLL_CFG_RES_MASK                                                  0x0000000FU
 130
 131 /*PLL charge pump control*/
 132 #undef CRL_APB_RPLL_CFG_CP_DEFVAL
 133 #undef CRL_APB_RPLL_CFG_CP_SHIFT
 134 #undef CRL_APB_RPLL_CFG_CP_MASK
 135 #define CRL_APB_RPLL_CFG_CP_DEFVAL                                                 0x00000000
 136 #define CRL_APB_RPLL_CFG_CP_SHIFT                                                  5
 137 #define CRL_APB_RPLL_CFG_CP_MASK                                                   0x000001E0U
 138
 139 /*PLL loop filter high frequency capacitor control*/
 140 #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
 141 #undef CRL_APB_RPLL_CFG_LFHF_SHIFT
 142 #undef CRL_APB_RPLL_CFG_LFHF_MASK
 143 #define CRL_APB_RPLL_CFG_LFHF_DEFVAL                                               0x00000000
 144 #define CRL_APB_RPLL_CFG_LFHF_SHIFT                                                10
 145 #define CRL_APB_RPLL_CFG_LFHF_MASK                                                 0x00000C00U
 146
 147 /*Lock circuit counter setting*/
 148 #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
 149 #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
 150 #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
 151 #define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 152 #define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                                            13
 153 #define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 154
 155 /*Lock circuit configuration settings for lock windowsize*/
 156 #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
 157 #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
 158 #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
 159 #define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 160 #define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                                            25
 161 #define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 162
 163 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 164                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 165 #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
 166 #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
 167 #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
 168 #define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
 169 #define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                                            20
 170 #define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 171
 172 /*The integer portion of the feedback divider to the PLL*/
 173 #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
 174 #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
 175 #undef CRL_APB_RPLL_CTRL_FBDIV_MASK
 176 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
 177 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
 178 #define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 179
 180 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 181 #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
 182 #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
 183 #undef CRL_APB_RPLL_CTRL_DIV2_MASK
 184 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
 185 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
 186 #define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
 187
 188 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 189                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 190 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
 191 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 192 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 193 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 194 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
 195 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
 196
 197 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 198 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
 199 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
 200 #undef CRL_APB_RPLL_CTRL_RESET_MASK
 201 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
 202 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
 203 #define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
 204
 205 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 206 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
 207 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
 208 #undef CRL_APB_RPLL_CTRL_RESET_MASK
 209 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
 210 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
 211 #define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
 212
 213 /*RPLL is locked*/
 214 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
 215 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
 216 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
 217 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
 218 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
 219 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
 220 #define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
 221
 222 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 223                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 224 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
 225 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 226 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 227 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 228 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
 229 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
 230
 231 /*Divisor value for this clock.*/
 232 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
 233 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 234 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
 235 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 236 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
 237 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 238
 239 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 240                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 241 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL
 242 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
 243 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK
 244 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 245 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 246 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 247
 248 /*Fractional value for the Feedback value.*/
 249 #undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL
 250 #undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
 251 #undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK
 252 #define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 253 #define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT                                           0
 254 #define CRL_APB_RPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 255
 256 /*PLL loop filter resistor control*/
 257 #undef CRL_APB_IOPLL_CFG_RES_DEFVAL
 258 #undef CRL_APB_IOPLL_CFG_RES_SHIFT
 259 #undef CRL_APB_IOPLL_CFG_RES_MASK
 260 #define CRL_APB_IOPLL_CFG_RES_DEFVAL                                               0x00000000
 261 #define CRL_APB_IOPLL_CFG_RES_SHIFT                                                0
 262 #define CRL_APB_IOPLL_CFG_RES_MASK                                                 0x0000000FU
 263
 264 /*PLL charge pump control*/
 265 #undef CRL_APB_IOPLL_CFG_CP_DEFVAL
 266 #undef CRL_APB_IOPLL_CFG_CP_SHIFT
 267 #undef CRL_APB_IOPLL_CFG_CP_MASK
 268 #define CRL_APB_IOPLL_CFG_CP_DEFVAL                                                0x00000000
 269 #define CRL_APB_IOPLL_CFG_CP_SHIFT                                                 5
 270 #define CRL_APB_IOPLL_CFG_CP_MASK                                                  0x000001E0U
 271
 272 /*PLL loop filter high frequency capacitor control*/
 273 #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
 274 #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
 275 #undef CRL_APB_IOPLL_CFG_LFHF_MASK
 276 #define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                                              0x00000000
 277 #define CRL_APB_IOPLL_CFG_LFHF_SHIFT                                               10
 278 #define CRL_APB_IOPLL_CFG_LFHF_MASK                                                0x00000C00U
 279
 280 /*Lock circuit counter setting*/
 281 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
 282 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
 283 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
 284 #define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                                          0x00000000
 285 #define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                                           13
 286 #define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                                            0x007FE000U
 287
 288 /*Lock circuit configuration settings for lock windowsize*/
 289 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
 290 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
 291 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
 292 #define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                                          0x00000000
 293 #define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                                           25
 294 #define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                                            0xFE000000U
 295
 296 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 297                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 298 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
 299 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
 300 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
 301 #define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                                          0x00012C09
 302 #define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                                           20
 303 #define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                                            0x00700000U
 304
 305 /*The integer portion of the feedback divider to the PLL*/
 306 #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
 307 #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
 308 #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
 309 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
 310 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
 311 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
 312
 313 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 314 #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
 315 #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
 316 #undef CRL_APB_IOPLL_CTRL_DIV2_MASK
 317 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
 318 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
 319 #define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
 320
 321 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 322                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 323 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
 324 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 325 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 326 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
 327 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
 328 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
 329
 330 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 331 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
 332 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
 333 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
 334 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
 335 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
 336 #define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
 337
 338 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 339 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
 340 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
 341 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
 342 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
 343 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
 344 #define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
 345
 346 /*IOPLL is locked*/
 347 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
 348 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
 349 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
 350 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
 351 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
 352 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
 353 #define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
 354
 355 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 356                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 357 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
 358 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 359 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 360 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
 361 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
 362 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
 363
 364 /*Divisor value for this clock.*/
 365 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
 366 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 367 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
 368 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
 369 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
 370 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
 371
 372 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 373                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 374 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL
 375 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
 376 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK
 377 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL                                      0x00000000
 378 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT                                       31
 379 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK                                        0x80000000U
 380
 381 /*Fractional value for the Feedback value.*/
 382 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL
 383 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
 384 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK
 385 #define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL                                         0x00000000
 386 #define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT                                          0
 387 #define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK                                           0x0000FFFFU
 388
 389 /*PLL loop filter resistor control*/
 390 #undef CRF_APB_APLL_CFG_RES_DEFVAL
 391 #undef CRF_APB_APLL_CFG_RES_SHIFT
 392 #undef CRF_APB_APLL_CFG_RES_MASK
 393 #define CRF_APB_APLL_CFG_RES_DEFVAL                                                0x00000000
 394 #define CRF_APB_APLL_CFG_RES_SHIFT                                                 0
 395 #define CRF_APB_APLL_CFG_RES_MASK                                                  0x0000000FU
 396
 397 /*PLL charge pump control*/
 398 #undef CRF_APB_APLL_CFG_CP_DEFVAL
 399 #undef CRF_APB_APLL_CFG_CP_SHIFT
 400 #undef CRF_APB_APLL_CFG_CP_MASK
 401 #define CRF_APB_APLL_CFG_CP_DEFVAL                                                 0x00000000
 402 #define CRF_APB_APLL_CFG_CP_SHIFT                                                  5
 403 #define CRF_APB_APLL_CFG_CP_MASK                                                   0x000001E0U
 404
 405 /*PLL loop filter high frequency capacitor control*/
 406 #undef CRF_APB_APLL_CFG_LFHF_DEFVAL
 407 #undef CRF_APB_APLL_CFG_LFHF_SHIFT
 408 #undef CRF_APB_APLL_CFG_LFHF_MASK
 409 #define CRF_APB_APLL_CFG_LFHF_DEFVAL                                               0x00000000
 410 #define CRF_APB_APLL_CFG_LFHF_SHIFT                                                10
 411 #define CRF_APB_APLL_CFG_LFHF_MASK                                                 0x00000C00U
 412
 413 /*Lock circuit counter setting*/
 414 #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
 415 #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
 416 #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
 417 #define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 418 #define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                                            13
 419 #define CRF_APB_APLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 420
 421 /*Lock circuit configuration settings for lock windowsize*/
 422 #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
 423 #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
 424 #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
 425 #define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 426 #define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                                            25
 427 #define CRF_APB_APLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 428
 429 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 430                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 431 #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
 432 #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
 433 #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
 434 #define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
 435 #define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                                            20
 436 #define CRF_APB_APLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 437
 438 /*The integer portion of the feedback divider to the PLL*/
 439 #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
 440 #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
 441 #undef CRF_APB_APLL_CTRL_FBDIV_MASK
 442 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
 443 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
 444 #define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
 445
 446 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 447 #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
 448 #undef CRF_APB_APLL_CTRL_DIV2_SHIFT
 449 #undef CRF_APB_APLL_CTRL_DIV2_MASK
 450 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
 451 #define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
 452 #define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
 453
 454 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 455                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 456 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
 457 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
 458 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
 459 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 460 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
 461 #define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
 462
 463 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 464 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
 465 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
 466 #undef CRF_APB_APLL_CTRL_RESET_MASK
 467 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
 468 #define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
 469 #define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
 470
 471 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 472 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
 473 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
 474 #undef CRF_APB_APLL_CTRL_RESET_MASK
 475 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
 476 #define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
 477 #define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
 478
 479 /*APLL is locked*/
 480 #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
 481 #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
 482 #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
 483 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
 484 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
 485 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
 486 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 487
 488 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 489                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 490 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
 491 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
 492 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
 493 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
 494 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
 495 #define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
 496
 497 /*Divisor value for this clock.*/
 498 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 499 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 500 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
 501 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 502 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 503 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 504
 505 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 506                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 507 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL
 508 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
 509 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK
 510 #define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 511 #define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT                                        31
 512 #define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 513
 514 /*Fractional value for the Feedback value.*/
 515 #undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL
 516 #undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
 517 #undef CRF_APB_APLL_FRAC_CFG_DATA_MASK
 518 #define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 519 #define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT                                           0
 520 #define CRF_APB_APLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 521
 522 /*PLL loop filter resistor control*/
 523 #undef CRF_APB_DPLL_CFG_RES_DEFVAL
 524 #undef CRF_APB_DPLL_CFG_RES_SHIFT
 525 #undef CRF_APB_DPLL_CFG_RES_MASK
 526 #define CRF_APB_DPLL_CFG_RES_DEFVAL                                                0x00000000
 527 #define CRF_APB_DPLL_CFG_RES_SHIFT                                                 0
 528 #define CRF_APB_DPLL_CFG_RES_MASK                                                  0x0000000FU
 529
 530 /*PLL charge pump control*/
 531 #undef CRF_APB_DPLL_CFG_CP_DEFVAL
 532 #undef CRF_APB_DPLL_CFG_CP_SHIFT
 533 #undef CRF_APB_DPLL_CFG_CP_MASK
 534 #define CRF_APB_DPLL_CFG_CP_DEFVAL                                                 0x00000000
 535 #define CRF_APB_DPLL_CFG_CP_SHIFT                                                  5
 536 #define CRF_APB_DPLL_CFG_CP_MASK                                                   0x000001E0U
 537
 538 /*PLL loop filter high frequency capacitor control*/
 539 #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
 540 #undef CRF_APB_DPLL_CFG_LFHF_SHIFT
 541 #undef CRF_APB_DPLL_CFG_LFHF_MASK
 542 #define CRF_APB_DPLL_CFG_LFHF_DEFVAL                                               0x00000000
 543 #define CRF_APB_DPLL_CFG_LFHF_SHIFT                                                10
 544 #define CRF_APB_DPLL_CFG_LFHF_MASK                                                 0x00000C00U
 545
 546 /*Lock circuit counter setting*/
 547 #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
 548 #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
 549 #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
 550 #define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 551 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                                            13
 552 #define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 553
 554 /*Lock circuit configuration settings for lock windowsize*/
 555 #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
 556 #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
 557 #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
 558 #define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 559 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                                            25
 560 #define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 561
 562 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 563                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 564 #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
 565 #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
 566 #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
 567 #define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                                           0x00002C09
 568 #define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                                            20
 569 #define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 570
 571 /*The integer portion of the feedback divider to the PLL*/
 572 #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
 573 #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
 574 #undef CRF_APB_DPLL_CTRL_FBDIV_MASK
 575 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
 576 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
 577 #define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 578
 579 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 580 #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
 581 #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
 582 #undef CRF_APB_DPLL_CTRL_DIV2_MASK
 583 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
 584 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
 585 #define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
 586
 587 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 588                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 589 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
 590 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 591 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 592 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
 593 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
 594 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
 595
 596 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 597 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
 598 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
 599 #undef CRF_APB_DPLL_CTRL_RESET_MASK
 600 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
 601 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
 602 #define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
 603
 604 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 605 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
 606 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
 607 #undef CRF_APB_DPLL_CTRL_RESET_MASK
 608 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
 609 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
 610 #define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
 611
 612 /*DPLL is locked*/
 613 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
 614 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
 615 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
 616 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
 617 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
 618 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
 619 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 620
 621 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 622                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 623 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
 624 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 625 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 626 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
 627 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
 628 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
 629
 630 /*Divisor value for this clock.*/
 631 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 632 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 633 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
 634 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 635 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 636 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 637
 638 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 639                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 640 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL
 641 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
 642 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK
 643 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 644 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 645 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 646
 647 /*Fractional value for the Feedback value.*/
 648 #undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL
 649 #undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
 650 #undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK
 651 #define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 652 #define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT                                           0
 653 #define CRF_APB_DPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 654
 655 /*PLL loop filter resistor control*/
 656 #undef CRF_APB_VPLL_CFG_RES_DEFVAL
 657 #undef CRF_APB_VPLL_CFG_RES_SHIFT
 658 #undef CRF_APB_VPLL_CFG_RES_MASK
 659 #define CRF_APB_VPLL_CFG_RES_DEFVAL                                                0x00000000
 660 #define CRF_APB_VPLL_CFG_RES_SHIFT                                                 0
 661 #define CRF_APB_VPLL_CFG_RES_MASK                                                  0x0000000FU
 662
 663 /*PLL charge pump control*/
 664 #undef CRF_APB_VPLL_CFG_CP_DEFVAL
 665 #undef CRF_APB_VPLL_CFG_CP_SHIFT
 666 #undef CRF_APB_VPLL_CFG_CP_MASK
 667 #define CRF_APB_VPLL_CFG_CP_DEFVAL                                                 0x00000000
 668 #define CRF_APB_VPLL_CFG_CP_SHIFT                                                  5
 669 #define CRF_APB_VPLL_CFG_CP_MASK                                                   0x000001E0U
 670
 671 /*PLL loop filter high frequency capacitor control*/
 672 #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
 673 #undef CRF_APB_VPLL_CFG_LFHF_SHIFT
 674 #undef CRF_APB_VPLL_CFG_LFHF_MASK
 675 #define CRF_APB_VPLL_CFG_LFHF_DEFVAL                                               0x00000000
 676 #define CRF_APB_VPLL_CFG_LFHF_SHIFT                                                10
 677 #define CRF_APB_VPLL_CFG_LFHF_MASK                                                 0x00000C00U
 678
 679 /*Lock circuit counter setting*/
 680 #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
 681 #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
 682 #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
 683 #define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
 684 #define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                                            13
 685 #define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
 686
 687 /*Lock circuit configuration settings for lock windowsize*/
 688 #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
 689 #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
 690 #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
 691 #define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
 692 #define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                                            25
 693 #define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
 694
 695 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 696                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
 697 #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
 698 #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
 699 #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
 700 #define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012809
 701 #define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                                            20
 702 #define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
 703
 704 /*The integer portion of the feedback divider to the PLL*/
 705 #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
 706 #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
 707 #undef CRF_APB_VPLL_CTRL_FBDIV_MASK
 708 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
 709 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
 710 #define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
 711
 712 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
 713 #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
 714 #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
 715 #undef CRF_APB_VPLL_CTRL_DIV2_MASK
 716 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
 717 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
 718 #define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
 719
 720 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 721                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 722 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
 723 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 724 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 725 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
 726 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
 727 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
 728
 729 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 730 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
 731 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
 732 #undef CRF_APB_VPLL_CTRL_RESET_MASK
 733 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
 734 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
 735 #define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
 736
 737 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
 738 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
 739 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
 740 #undef CRF_APB_VPLL_CTRL_RESET_MASK
 741 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
 742 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
 743 #define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
 744
 745 /*VPLL is locked*/
 746 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
 747 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
 748 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
 749 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
 750 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
 751 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
 752 #define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
 753
 754 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 755                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
 756 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
 757 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 758 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 759 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
 760 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
 761 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
 762
 763 /*Divisor value for this clock.*/
 764 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
 765 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 766 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
 767 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
 768 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
 769 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
 770
 771 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 772                  mode and uses DATA of this register for the fractional portion of the feedback divider.*/
 773 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL
 774 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
 775 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK
 776 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
 777 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT                                        31
 778 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
 779
 780 /*Fractional value for the Feedback value.*/
 781 #undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL
 782 #undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
 783 #undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK
 784 #define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
 785 #define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT                                           0
 786 #define CRF_APB_VPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
 787 #undef CRL_APB_GEM0_REF_CTRL_OFFSET
 788 #define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
 789 #undef CRL_APB_GEM1_REF_CTRL_OFFSET
 790 #define CRL_APB_GEM1_REF_CTRL_OFFSET                                               0XFF5E0054
 791 #undef CRL_APB_GEM2_REF_CTRL_OFFSET
 792 #define CRL_APB_GEM2_REF_CTRL_OFFSET                                               0XFF5E0058
 793 #undef CRL_APB_GEM3_REF_CTRL_OFFSET
 794 #define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
 795 #undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
 796 #define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
 797 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
 798 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
 799 #undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET
 800 #define CRL_APB_USB1_BUS_REF_CTRL_OFFSET                                           0XFF5E0064
 801 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
 802 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
 803 #undef CRL_APB_QSPI_REF_CTRL_OFFSET
 804 #define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
 805 #undef CRL_APB_SDIO0_REF_CTRL_OFFSET
 806 #define CRL_APB_SDIO0_REF_CTRL_OFFSET                                              0XFF5E006C
 807 #undef CRL_APB_SDIO1_REF_CTRL_OFFSET
 808 #define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
 809 #undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
 810 #define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
 811 #undef CRL_APB_UART0_REF_CTRL_OFFSET
 812 #define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
 813 #undef CRL_APB_UART1_REF_CTRL_OFFSET
 814 #define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
 815 #undef CRL_APB_I2C0_REF_CTRL_OFFSET
 816 #define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
 817 #undef CRL_APB_I2C1_REF_CTRL_OFFSET
 818 #define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
 819 #undef CRL_APB_SPI0_REF_CTRL_OFFSET
 820 #define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
 821 #undef CRL_APB_SPI1_REF_CTRL_OFFSET
 822 #define CRL_APB_SPI1_REF_CTRL_OFFSET                                               0XFF5E0080
 823 #undef CRL_APB_CAN0_REF_CTRL_OFFSET
 824 #define CRL_APB_CAN0_REF_CTRL_OFFSET                                               0XFF5E0084
 825 #undef CRL_APB_CAN1_REF_CTRL_OFFSET
 826 #define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
 827 #undef CRL_APB_CPU_R5_CTRL_OFFSET
 828 #define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
 829 #undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
 830 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
 831 #undef CRL_APB_CSU_PLL_CTRL_OFFSET
 832 #define CRL_APB_CSU_PLL_CTRL_OFFSET                                                0XFF5E00A0
 833 #undef CRL_APB_PCAP_CTRL_OFFSET
 834 #define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
 835 #undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
 836 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
 837 #undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
 838 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
 839 #undef CRL_APB_DBG_LPD_CTRL_OFFSET
 840 #define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
 841 #undef CRL_APB_NAND_REF_CTRL_OFFSET
 842 #define CRL_APB_NAND_REF_CTRL_OFFSET                                               0XFF5E00B4
 843 #undef CRL_APB_ADMA_REF_CTRL_OFFSET
 844 #define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
 845 #undef CRL_APB_PL0_REF_CTRL_OFFSET
 846 #define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
 847 #undef CRL_APB_PL1_REF_CTRL_OFFSET
 848 #define CRL_APB_PL1_REF_CTRL_OFFSET                                                0XFF5E00C4
 849 #undef CRL_APB_PL2_REF_CTRL_OFFSET
 850 #define CRL_APB_PL2_REF_CTRL_OFFSET                                                0XFF5E00C8
 851 #undef CRL_APB_PL3_REF_CTRL_OFFSET
 852 #define CRL_APB_PL3_REF_CTRL_OFFSET                                                0XFF5E00CC
 853 #undef CRL_APB_AMS_REF_CTRL_OFFSET
 854 #define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
 855 #undef CRL_APB_DLL_REF_CTRL_OFFSET
 856 #define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
 857 #undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
 858 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
 859 #undef CRF_APB_SATA_REF_CTRL_OFFSET
 860 #define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
 861 #undef CRF_APB_PCIE_REF_CTRL_OFFSET
 862 #define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
 863 #undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
 864 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
 865 #undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
 866 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
 867 #undef CRF_APB_DP_STC_REF_CTRL_OFFSET
 868 #define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
 869 #undef CRF_APB_ACPU_CTRL_OFFSET
 870 #define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
 871 #undef CRF_APB_DBG_TRACE_CTRL_OFFSET
 872 #define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
 873 #undef CRF_APB_DBG_FPD_CTRL_OFFSET
 874 #define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
 875 #undef CRF_APB_DDR_CTRL_OFFSET
 876 #define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
 877 #undef CRF_APB_GPU_REF_CTRL_OFFSET
 878 #define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
 879 #undef CRF_APB_GDMA_REF_CTRL_OFFSET
 880 #define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
 881 #undef CRF_APB_DPDMA_REF_CTRL_OFFSET
 882 #define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
 883 #undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
 884 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
 885 #undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
 886 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
 887 #undef CRF_APB_GTGREF0_REF_CTRL_OFFSET
 888 #define CRF_APB_GTGREF0_REF_CTRL_OFFSET                                            0XFD1A00C8
 889 #undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
 890 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
 891 #undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
 892 #define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
 893 #undef FPD_SLCR_WDT_CLK_SEL_OFFSET
 894 #define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
 895 #undef IOU_SLCR_WDT_CLK_SEL_OFFSET
 896 #define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
 897 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
 898 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
 899
 900 /*Clock active for the RX channel*/
 901 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL
 902 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
 903 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK
 904 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
 905 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                                      26
 906 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
 907
 908 /*Clock active signal. Switch to 0 to disable the clock*/
 909 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL
 910 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
 911 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK
 912 #define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
 913 #define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                                         25
 914 #define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                                          0x02000000U
 915
 916 /*6 bit divider*/
 917 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL
 918 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
 919 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK
 920 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
 921 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                                       16
 922 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
 923
 924 /*6 bit divider*/
 925 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL
 926 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
 927 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK
 928 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
 929 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                                       8
 930 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
 931
 932 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 933                 clock. This is not usually an issue, but designers must be aware.)*/
 934 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL
 935 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
 936 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK
 937 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
 938 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                                         0
 939 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
 940
 941 /*Clock active for the RX channel*/
 942 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL
 943 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
 944 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK
 945 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
 946 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT                                      26
 947 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
 948
 949 /*Clock active signal. Switch to 0 to disable the clock*/
 950 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL
 951 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
 952 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK
 953 #define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
 954 #define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT                                         25
 955 #define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK                                          0x02000000U
 956
 957 /*6 bit divider*/
 958 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL
 959 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
 960 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK
 961 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
 962 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT                                       16
 963 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
 964
 965 /*6 bit divider*/
 966 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL
 967 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
 968 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK
 969 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
 970 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT                                       8
 971 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
 972
 973 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 974                 clock. This is not usually an issue, but designers must be aware.)*/
 975 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL
 976 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
 977 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK
 978 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
 979 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT                                         0
 980 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
 981
 982 /*Clock active for the RX channel*/
 983 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL
 984 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
 985 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK
 986 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
 987 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT                                      26
 988 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
 989
 990 /*Clock active signal. Switch to 0 to disable the clock*/
 991 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL
 992 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
 993 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK
 994 #define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
 995 #define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT                                         25
 996 #define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK                                          0x02000000U
 997
 998 /*6 bit divider*/
 999 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL
1000 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
1001 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK
1002 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
1003 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT                                       16
1004 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1005
1006 /*6 bit divider*/
1007 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL
1008 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
1009 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK
1010 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
1011 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT                                       8
1012 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1013
1014 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1015                 clock. This is not usually an issue, but designers must be aware.)*/
1016 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL
1017 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
1018 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK
1019 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
1020 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT                                         0
1021 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1022
1023 /*Clock active for the RX channel*/
1024 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
1025 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
1026 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
1027 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
1028 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
1029 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
1030
1031 /*Clock active signal. Switch to 0 to disable the clock*/
1032 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
1033 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
1034 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
1035 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
1036 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
1037 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
1038
1039 /*6 bit divider*/
1040 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
1041 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
1042 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
1043 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
1044 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
1045 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1046
1047 /*6 bit divider*/
1048 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
1049 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
1050 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
1051 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
1052 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
1053 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1054
1055 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1056                 clock. This is not usually an issue, but designers must be aware.)*/
1057 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
1058 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
1059 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
1060 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
1061 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
1062 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1063
1064 /*6 bit divider*/
1065 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
1066 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
1067 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
1068 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL                                   0x00051000
1069 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                                    8
1070 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
1071
1072 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1073                 clock. This is not usually an issue, but designers must be aware.)*/
1074 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
1075 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
1076 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
1077 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                                     0x00051000
1078 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                                      0
1079 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                                       0x00000007U
1080
1081 /*6 bit divider*/
1082 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
1083 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
1084 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
1085 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL                                   0x00051000
1086 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                                    16
1087 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                                     0x003F0000U
1088
1089 /*Clock active signal. Switch to 0 to disable the clock*/
1090 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
1091 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
1092 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
1093 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                                     0x00051000
1094 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                                      24
1095 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                                       0x01000000U
1096
1097 /*Clock active signal. Switch to 0 to disable the clock*/
1098 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
1099 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
1100 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
1101 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
1102 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
1103 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
1104
1105 /*6 bit divider*/
1106 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
1107 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
1108 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
1109 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
1110 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
1111 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
1112
1113 /*6 bit divider*/
1114 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
1115 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
1116 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
1117 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
1118 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
1119 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
1120
1121 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1122                 clock. This is not usually an issue, but designers must be aware.)*/
1123 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
1124 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
1125 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
1126 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
1127 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
1128 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
1129
1130 /*Clock active signal. Switch to 0 to disable the clock*/
1131 #undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL
1132 #undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
1133 #undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK
1134 #define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
1135 #define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT                                     25
1136 #define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
1137
1138 /*6 bit divider*/
1139 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL
1140 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
1141 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK
1142 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
1143 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
1144 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
1145
1146 /*6 bit divider*/
1147 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL
1148 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
1149 #undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK
1150 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
1151 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
1152 #define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
1153
1154 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1155                 clock. This is not usually an issue, but designers must be aware.)*/
1156 #undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL
1157 #undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
1158 #undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK
1159 #define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
1160 #define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
1161 #define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
1162
1163 /*Clock active signal. Switch to 0 to disable the clock*/
1164 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
1165 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
1166 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
1167 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
1168 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
1169 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
1170
1171 /*6 bit divider*/
1172 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
1173 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
1174 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
1175 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
1176 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
1177 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
1178
1179 /*6 bit divider*/
1180 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
1181 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
1182 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
1183 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
1184 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
1185 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
1186
1187 /*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1188                 clock. This is not usually an issue, but designers must be aware.)*/
1189 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
1190 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
1191 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
1192 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
1193 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
1194 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
1195
1196 /*Clock active signal. Switch to 0 to disable the clock*/
1197 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
1198 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
1199 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
1200 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
1201 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
1202 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
1203
1204 /*6 bit divider*/
1205 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
1206 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
1207 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
1208 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
1209 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
1210 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1211
1212 /*6 bit divider*/
1213 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
1214 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
1215 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
1216 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
1217 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
1218 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1219
1220 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1221                 clock. This is not usually an issue, but designers must be aware.)*/
1222 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
1223 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
1224 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
1225 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
1226 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
1227 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1228
1229 /*Clock active signal. Switch to 0 to disable the clock*/
1230 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL
1231 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
1232 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK
1233 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
1234 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT                                        24
1235 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK                                         0x01000000U
1236
1237 /*6 bit divider*/
1238 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL
1239 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
1240 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK
1241 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
1242 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT                                      16
1243 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1244
1245 /*6 bit divider*/
1246 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL
1247 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
1248 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK
1249 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
1250 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT                                      8
1251 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1252
1253 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1254                 clock. This is not usually an issue, but designers must be aware.)*/
1255 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL
1256 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
1257 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK
1258 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
1259 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT                                        0
1260 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1261
1262 /*Clock active signal. Switch to 0 to disable the clock*/
1263 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
1264 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
1265 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
1266 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
1267 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
1268 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
1269
1270 /*6 bit divider*/
1271 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
1272 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
1273 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
1274 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
1275 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
1276 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1277
1278 /*6 bit divider*/
1279 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
1280 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
1281 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
1282 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
1283 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
1284 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1285
1286 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1287                 clock. This is not usually an issue, but designers must be aware.)*/
1288 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
1289 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
1290 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
1291 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
1292 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
1293 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1294
1295 /*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/
1296 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
1297 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1298 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
1299 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL                             0x00000000
1300 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT                              17
1301 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK                               0x00020000U
1302
1303 /*Clock active signal. Switch to 0 to disable the clock*/
1304 #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
1305 #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1306 #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
1307 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
1308 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
1309 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
1310
1311 /*6 bit divider*/
1312 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
1313 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1314 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
1315 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
1316 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
1317 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1318
1319 /*6 bit divider*/
1320 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
1321 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1322 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
1323 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1324 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
1325 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1326
1327 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1328                 clock. This is not usually an issue, but designers must be aware.)*/
1329 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
1330 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1331 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
1332 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
1333 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
1334 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1335
1336 /*Clock active signal. Switch to 0 to disable the clock*/
1337 #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
1338 #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1339 #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
1340 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
1341 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
1342 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
1343
1344 /*6 bit divider*/
1345 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
1346 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1347 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
1348 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
1349 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
1350 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
1351
1352 /*6 bit divider*/
1353 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
1354 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1355 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
1356 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1357 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
1358 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
1359
1360 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1361                 clock. This is not usually an issue, but designers must be aware.)*/
1362 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
1363 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1364 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
1365 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
1366 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
1367 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
1368
1369 /*Clock active signal. Switch to 0 to disable the clock*/
1370 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
1371 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1372 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
1373 #define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
1374 #define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
1375 #define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
1376
1377 /*6 bit divider*/
1378 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
1379 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1380 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
1381 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
1382 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
1383 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1384
1385 /*6 bit divider*/
1386 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
1387 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1388 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
1389 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
1390 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
1391 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1392
1393 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1394                 clock. This is not usually an issue, but designers must be aware.)*/
1395 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
1396 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1397 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
1398 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
1399 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
1400 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1401
1402 /*Clock active signal. Switch to 0 to disable the clock*/
1403 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
1404 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1405 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
1406 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
1407 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
1408 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
1409
1410 /*6 bit divider*/
1411 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
1412 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1413 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
1414 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
1415 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
1416 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1417
1418 /*6 bit divider*/
1419 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
1420 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1421 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
1422 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
1423 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
1424 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1425
1426 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1427                 clock. This is not usually an issue, but designers must be aware.)*/
1428 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
1429 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1430 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
1431 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
1432 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
1433 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1434
1435 /*Clock active signal. Switch to 0 to disable the clock*/
1436 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL
1437 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
1438 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK
1439 #define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
1440 #define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                                         24
1441 #define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                                          0x01000000U
1442
1443 /*6 bit divider*/
1444 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL
1445 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
1446 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK
1447 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
1448 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                                       16
1449 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1450
1451 /*6 bit divider*/
1452 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL
1453 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
1454 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK
1455 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
1456 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                                       8
1457 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1458
1459 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1460                 clock. This is not usually an issue, but designers must be aware.)*/
1461 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL
1462 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
1463 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK
1464 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
1465 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                                         0
1466 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1467
1468 /*Clock active signal. Switch to 0 to disable the clock*/
1469 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL
1470 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
1471 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK
1472 #define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
1473 #define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT                                         24
1474 #define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK                                          0x01000000U
1475
1476 /*6 bit divider*/
1477 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL
1478 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
1479 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK
1480 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
1481 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT                                       16
1482 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1483
1484 /*6 bit divider*/
1485 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL
1486 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
1487 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK
1488 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
1489 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT                                       8
1490 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1491
1492 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1493                 clock. This is not usually an issue, but designers must be aware.)*/
1494 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL
1495 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
1496 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK
1497 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
1498 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT                                         0
1499 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1500
1501 /*Clock active signal. Switch to 0 to disable the clock*/
1502 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL
1503 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
1504 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK
1505 #define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
1506 #define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT                                         24
1507 #define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK                                          0x01000000U
1508
1509 /*6 bit divider*/
1510 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL
1511 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
1512 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK
1513 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
1514 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT                                       16
1515 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1516
1517 /*6 bit divider*/
1518 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL
1519 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
1520 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK
1521 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
1522 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT                                       8
1523 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1524
1525 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1526                 clock. This is not usually an issue, but designers must be aware.)*/
1527 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL
1528 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
1529 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK
1530 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
1531 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT                                         0
1532 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1533
1534 /*Clock active signal. Switch to 0 to disable the clock*/
1535 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
1536 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1537 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
1538 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
1539 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
1540 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
1541
1542 /*6 bit divider*/
1543 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
1544 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1545 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
1546 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
1547 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
1548 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1549
1550 /*6 bit divider*/
1551 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
1552 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1553 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
1554 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
1555 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
1556 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1557
1558 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1559                 clock. This is not usually an issue, but designers must be aware.)*/
1560 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
1561 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1562 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
1563 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
1564 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
1565 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1566
1567 /*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1568                 d lead to system hang*/
1569 #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
1570 #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1571 #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
1572 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
1573 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
1574 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
1575
1576 /*6 bit divider*/
1577 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
1578 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1579 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
1580 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
1581 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
1582 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
1583
1584 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1585                 clock. This is not usually an issue, but designers must be aware.)*/
1586 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
1587 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1588 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
1589 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
1590 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
1591 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
1592
1593 /*Clock active signal. Switch to 0 to disable the clock*/
1594 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
1595 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1596 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
1597 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
1598 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
1599 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
1600
1601 /*6 bit divider*/
1602 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
1603 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1604 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
1605 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
1606 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
1607 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
1608
1609 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1610                 clock. This is not usually an issue, but designers must be aware.)*/
1611 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
1612 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1613 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
1614 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
1615 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
1616 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
1617
1618 /*Clock active signal. Switch to 0 to disable the clock*/
1619 #undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL
1620 #undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
1621 #undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK
1622 #define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL                                         0x01001500
1623 #define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT                                          24
1624 #define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK                                           0x01000000U
1625
1626 /*6 bit divider*/
1627 #undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL
1628 #undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
1629 #undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK
1630 #define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL                                       0x01001500
1631 #define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT                                        8
1632 #define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK                                         0x00003F00U
1633
1634 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1635                 clock. This is not usually an issue, but designers must be aware.)*/
1636 #undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL
1637 #undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
1638 #undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK
1639 #define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL                                         0x01001500
1640 #define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT                                          0
1641 #define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK                                           0x00000007U
1642
1643 /*Clock active signal. Switch to 0 to disable the clock*/
1644 #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
1645 #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1646 #undef CRL_APB_PCAP_CTRL_CLKACT_MASK
1647 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
1648 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
1649 #define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
1650
1651 /*6 bit divider*/
1652 #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
1653 #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1654 #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
1655 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
1656 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
1657 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
1658
1659 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1660                 clock. This is not usually an issue, but designers must be aware.)*/
1661 #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
1662 #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1663 #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
1664 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
1665 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
1666 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
1667
1668 /*Clock active signal. Switch to 0 to disable the clock*/
1669 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
1670 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1671 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
1672 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
1673 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
1674 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
1675
1676 /*6 bit divider*/
1677 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
1678 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1679 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
1680 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
1681 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
1682 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
1683
1684 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1685                 clock. This is not usually an issue, but designers must be aware.)*/
1686 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
1687 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1688 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
1689 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
1690 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
1691 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
1692
1693 /*Clock active signal. Switch to 0 to disable the clock*/
1694 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
1695 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1696 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
1697 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
1698 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
1699 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
1700
1701 /*6 bit divider*/
1702 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
1703 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1704 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
1705 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
1706 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
1707 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
1708
1709 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1710                 clock. This is not usually an issue, but designers must be aware.)*/
1711 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
1712 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1713 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
1714 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
1715 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
1716 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
1717
1718 /*Clock active signal. Switch to 0 to disable the clock*/
1719 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
1720 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1721 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
1722 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
1723 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
1724 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
1725
1726 /*6 bit divider*/
1727 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
1728 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1729 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
1730 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
1731 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
1732 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
1733
1734 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1735                 clock. This is not usually an issue, but designers must be aware.)*/
1736 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
1737 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1738 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
1739 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
1740 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
1741 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
1742
1743 /*Clock active signal. Switch to 0 to disable the clock*/
1744 #undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL
1745 #undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
1746 #undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK
1747 #define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL                                        0x00052000
1748 #define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT                                         24
1749 #define CRL_APB_NAND_REF_CTRL_CLKACT_MASK                                          0x01000000U
1750
1751 /*6 bit divider*/
1752 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL
1753 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
1754 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK
1755 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL                                      0x00052000
1756 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT                                       16
1757 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
1758
1759 /*6 bit divider*/
1760 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL
1761 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
1762 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK
1763 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL                                      0x00052000
1764 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT                                       8
1765 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1766
1767 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1768                 clock. This is not usually an issue, but designers must be aware.)*/
1769 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL
1770 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
1771 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK
1772 #define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL                                        0x00052000
1773 #define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT                                         0
1774 #define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1775
1776 /*Clock active signal. Switch to 0 to disable the clock*/
1777 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
1778 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1779 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
1780 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
1781 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
1782 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
1783
1784 /*6 bit divider*/
1785 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
1786 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1787 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
1788 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
1789 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
1790 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
1791
1792 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1793                 clock. This is not usually an issue, but designers must be aware.)*/
1794 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
1795 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1796 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
1797 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
1798 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
1799 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
1800
1801 /*Clock active signal. Switch to 0 to disable the clock*/
1802 #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
1803 #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1804 #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
1805 #define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1806 #define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                                          24
1807 #define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                                           0x01000000U
1808
1809 /*6 bit divider*/
1810 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
1811 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1812 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
1813 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1814 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                                        16
1815 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1816
1817 /*6 bit divider*/
1818 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
1819 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1820 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
1821 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1822 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                                        8
1823 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1824
1825 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1826                 clock. This is not usually an issue, but designers must be aware.)*/
1827 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
1828 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1829 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
1830 #define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1831 #define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                                          0
1832 #define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1833
1834 /*Clock active signal. Switch to 0 to disable the clock*/
1835 #undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL
1836 #undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1837 #undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK
1838 #define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1839 #define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT                                          24
1840 #define CRL_APB_PL1_REF_CTRL_CLKACT_MASK                                           0x01000000U
1841
1842 /*6 bit divider*/
1843 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL
1844 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1845 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK
1846 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1847 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT                                        16
1848 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1849
1850 /*6 bit divider*/
1851 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL
1852 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1853 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK
1854 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1855 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT                                        8
1856 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1857
1858 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1859                 clock. This is not usually an issue, but designers must be aware.)*/
1860 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL
1861 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1862 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK
1863 #define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1864 #define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT                                          0
1865 #define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1866
1867 /*Clock active signal. Switch to 0 to disable the clock*/
1868 #undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL
1869 #undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1870 #undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK
1871 #define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1872 #define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT                                          24
1873 #define CRL_APB_PL2_REF_CTRL_CLKACT_MASK                                           0x01000000U
1874
1875 /*6 bit divider*/
1876 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL
1877 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1878 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK
1879 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1880 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT                                        16
1881 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1882
1883 /*6 bit divider*/
1884 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL
1885 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1886 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK
1887 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1888 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT                                        8
1889 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1890
1891 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1892                 clock. This is not usually an issue, but designers must be aware.)*/
1893 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL
1894 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1895 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK
1896 #define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1897 #define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT                                          0
1898 #define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1899
1900 /*Clock active signal. Switch to 0 to disable the clock*/
1901 #undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL
1902 #undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1903 #undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK
1904 #define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
1905 #define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT                                          24
1906 #define CRL_APB_PL3_REF_CTRL_CLKACT_MASK                                           0x01000000U
1907
1908 /*6 bit divider*/
1909 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL
1910 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1911 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK
1912 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
1913 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT                                        16
1914 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1915
1916 /*6 bit divider*/
1917 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL
1918 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1919 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK
1920 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
1921 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT                                        8
1922 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1923
1924 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1925                 clock. This is not usually an issue, but designers must be aware.)*/
1926 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL
1927 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1928 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK
1929 #define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
1930 #define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT                                          0
1931 #define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1932
1933 /*6 bit divider*/
1934 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
1935 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1936 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
1937 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
1938 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
1939 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
1940
1941 /*6 bit divider*/
1942 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
1943 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1944 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
1945 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
1946 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
1947 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
1948
1949 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1950                 clock. This is not usually an issue, but designers must be aware.)*/
1951 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
1952 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1953 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
1954 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
1955 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
1956 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1957
1958 /*Clock active signal. Switch to 0 to disable the clock*/
1959 #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
1960 #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1961 #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
1962 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
1963 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
1964 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
1965
1966 /*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1967                 is not usually an issue, but designers must be aware.)*/
1968 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
1969 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1970 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
1971 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
1972 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
1973 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
1974
1975 /*6 bit divider*/
1976 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
1977 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1978 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
1979 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
1980 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
1981 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
1982
1983 /*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1984                  cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1985 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
1986 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1987 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
1988 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
1989 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
1990 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
1991
1992 /*Clock active signal. Switch to 0 to disable the clock*/
1993 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
1994 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1995 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
1996 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
1997 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
1998 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
1999
2000 /*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2001                 he new clock. This is not usually an issue, but designers must be aware.)*/
2002 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
2003 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
2004 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
2005 #define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                                        0x01001600
2006 #define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                                         0
2007 #define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
2008
2009 /*Clock active signal. Switch to 0 to disable the clock*/
2010 #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
2011 #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
2012 #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
2013 #define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                                        0x01001600
2014 #define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                                         24
2015 #define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                                          0x01000000U
2016
2017 /*6 bit divider*/
2018 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
2019 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
2020 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
2021 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001600
2022 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                                       8
2023 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
2024
2025 /*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
2026                 es of the new clock. This is not usually an issue, but designers must be aware.)*/
2027 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
2028 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
2029 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
2030 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                                        0x00001500
2031 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                                         0
2032 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                                          0x00000007U
2033
2034 /*Clock active signal. Switch to 0 to disable the clock*/
2035 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
2036 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
2037 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
2038 #define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                                        0x00001500
2039 #define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                                         24
2040 #define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                                          0x01000000U
2041
2042 /*6 bit divider*/
2043 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
2044 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
2045 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
2046 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                                      0x00001500
2047 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                                       8
2048 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
2049
2050 /*6 bit divider*/
2051 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
2052 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
2053 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
2054 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
2055 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
2056 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
2057
2058 /*6 bit divider*/
2059 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
2060 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
2061 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
2062 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
2063 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
2064 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
2065
2066 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
2067                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
2068 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
2069 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
2070 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
2071 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
2072 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
2073 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
2074
2075 /*Clock active signal. Switch to 0 to disable the clock*/
2076 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
2077 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
2078 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
2079 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
2080 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
2081 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
2082
2083 /*6 bit divider*/
2084 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
2085 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
2086 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
2087 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
2088 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
2089 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
2090
2091 /*6 bit divider*/
2092 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
2093 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
2094 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
2095 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
2096 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
2097 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
2098
2099 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
2100                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
2101 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
2102 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
2103 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
2104 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
2105 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
2106 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
2107
2108 /*Clock active signal. Switch to 0 to disable the clock*/
2109 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
2110 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
2111 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
2112 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
2113 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
2114 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
2115
2116 /*6 bit divider*/
2117 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
2118 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
2119 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
2120 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
2121 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
2122 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
2123
2124 /*6 bit divider*/
2125 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
2126 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
2127 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
2128 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
2129 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
2130 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
2131
2132 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
2133                 e new clock. This is not usually an issue, but designers must be aware.)*/
2134 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
2135 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
2136 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
2137 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
2138 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
2139 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
2140
2141 /*Clock active signal. Switch to 0 to disable the clock*/
2142 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
2143 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
2144 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
2145 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
2146 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
2147 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
2148
2149 /*6 bit divider*/
2150 #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
2151 #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
2152 #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
2153 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
2154 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
2155 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
2156
2157 /*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2158                 lock. This is not usually an issue, but designers must be aware.)*/
2159 #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
2160 #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
2161 #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
2162 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
2163 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
2164 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
2165
2166 /*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
2167 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
2168 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
2169 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
2170 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
2171 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
2172 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
2173
2174 /*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
2175                  to the entire APU*/
2176 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
2177 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
2178 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
2179 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
2180 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
2181 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
2182
2183 /*6 bit divider*/
2184 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL
2185 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
2186 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK
2187 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
2188 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
2189 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
2190
2191 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2192                 he new clock. This is not usually an issue, but designers must be aware.)*/
2193 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL
2194 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
2195 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK
2196 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
2197 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
2198 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
2199
2200 /*Clock active signal. Switch to 0 to disable the clock*/
2201 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL
2202 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
2203 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK
2204 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
2205 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
2206 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
2207
2208 /*6 bit divider*/
2209 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
2210 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
2211 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
2212 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
2213 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
2214 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
2215
2216 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2217                 he new clock. This is not usually an issue, but designers must be aware.)*/
2218 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
2219 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
2220 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
2221 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
2222 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
2223 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
2224
2225 /*Clock active signal. Switch to 0 to disable the clock*/
2226 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
2227 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
2228 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
2229 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
2230 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
2231 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
2232
2233 /*6 bit divider*/
2234 #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
2235 #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
2236 #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
2237 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
2238 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
2239 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
2240
2241 /*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
2242                 s not usually an issue, but designers must be aware.)*/
2243 #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
2244 #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
2245 #undef CRF_APB_DDR_CTRL_SRCSEL_MASK
2246 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
2247 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
2248 #define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
2249
2250 /*6 bit divider*/
2251 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
2252 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
2253 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
2254 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
2255 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
2256 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
2257
2258 /*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2259                 he new clock. This is not usually an issue, but designers must be aware.)*/
2260 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
2261 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
2262 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
2263 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
2264 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
2265 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
2266
2267 /*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/
2268 #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
2269 #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
2270 #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
2271 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
2272 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
2273 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
2274
2275 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
2276 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
2277 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
2278 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
2279 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
2280 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
2281 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
2282
2283 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
2284 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
2285 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
2286 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
2287 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
2288 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
2289 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
2290
2291 /*6 bit divider*/
2292 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
2293 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
2294 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
2295 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
2296 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
2297 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
2298
2299 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2300                 lock. This is not usually an issue, but designers must be aware.)*/
2301 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
2302 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
2303 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
2304 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
2305 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
2306 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
2307
2308 /*Clock active signal. Switch to 0 to disable the clock*/
2309 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
2310 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
2311 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
2312 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
2313 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
2314 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
2315
2316 /*6 bit divider*/
2317 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
2318 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
2319 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
2320 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
2321 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
2322 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
2323
2324 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2325                 lock. This is not usually an issue, but designers must be aware.)*/
2326 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
2327 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
2328 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
2329 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
2330 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
2331 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
2332
2333 /*Clock active signal. Switch to 0 to disable the clock*/
2334 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
2335 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
2336 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
2337 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
2338 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
2339 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
2340
2341 /*6 bit divider*/
2342 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
2343 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
2344 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
2345 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
2346 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
2347 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
2348
2349 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2350                 lock. This is not usually an issue, but designers must be aware.)*/
2351 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
2352 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
2353 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
2354 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
2355 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
2356 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
2357
2358 /*Clock active signal. Switch to 0 to disable the clock*/
2359 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
2360 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
2361 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
2362 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
2363 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
2364 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
2365
2366 /*6 bit divider*/
2367 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
2368 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
2369 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
2370 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
2371 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
2372 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
2373
2374 /*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2375                 he new clock. This is not usually an issue, but designers must be aware.)*/
2376 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
2377 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
2378 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
2379 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
2380 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
2381 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
2382
2383 /*Clock active signal. Switch to 0 to disable the clock*/
2384 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
2385 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
2386 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
2387 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
2388 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
2389 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
2390
2391 /*6 bit divider*/
2392 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL
2393 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
2394 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK
2395 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL                                   0x00000800
2396 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT                                    8
2397 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
2398
2399 /*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2400                 he new clock. This is not usually an issue, but designers must be aware.)*/
2401 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL
2402 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
2403 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK
2404 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL                                     0x00000800
2405 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT                                      0
2406 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK                                       0x00000007U
2407
2408 /*Clock active signal. Switch to 0 to disable the clock*/
2409 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL
2410 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
2411 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK
2412 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL                                     0x00000800
2413 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT                                      24
2414 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK                                       0x01000000U
2415
2416 /*6 bit divider*/
2417 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
2418 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
2419 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
2420 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
2421 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
2422 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
2423
2424 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2425                 he new clock. This is not usually an issue, but designers must be aware.)*/
2426 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
2427 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
2428 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
2429 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
2430 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
2431 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
2432
2433 /*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
2434                 0" = Select the R5 clock for the APB interface of TTC0*/
2435 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
2436 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
2437 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
2438 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL                                   0x00000000
2439 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                                    0
2440 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                                     0x00000003U
2441
2442 /*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
2443                 0" = Select the R5 clock for the APB interface of TTC1*/
2444 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
2445 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
2446 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
2447 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL                                   0x00000000
2448 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                                    2
2449 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                                     0x0000000CU
2450
2451 /*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
2452                 0" = Select the R5 clock for the APB interface of TTC2*/
2453 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
2454 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
2455 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
2456 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL                                   0x00000000
2457 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                                    4
2458 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                                     0x00000030U
2459
2460 /*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
2461                 0" = Select the R5 clock for the APB interface of TTC3*/
2462 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
2463 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
2464 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
2465 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL                                   0x00000000
2466 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                                    6
2467 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                                     0x000000C0U
2468
2469 /*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/
2470 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2471 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2472 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
2473 #define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
2474 #define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
2475 #define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
2476
2477 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
2478                 ia MIO*/
2479 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2480 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2481 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
2482 #define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
2483 #define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
2484 #define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
2485
2486 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/
2487 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
2488 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
2489 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
2490 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL                                  0x00000000
2491 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT                                   0
2492 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                                    0x00000001U
2493 #undef CRF_APB_RST_DDR_SS_OFFSET
2494 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
2495 #undef DDRC_MSTR_OFFSET
2496 #define DDRC_MSTR_OFFSET                                                           0XFD070000
2497 #undef DDRC_MRCTRL0_OFFSET
2498 #define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
2499 #undef DDRC_DERATEEN_OFFSET
2500 #define DDRC_DERATEEN_OFFSET                                                       0XFD070020
2501 #undef DDRC_DERATEINT_OFFSET
2502 #define DDRC_DERATEINT_OFFSET                                                      0XFD070024
2503 #undef DDRC_PWRCTL_OFFSET
2504 #define DDRC_PWRCTL_OFFSET                                                         0XFD070030
2505 #undef DDRC_PWRTMG_OFFSET
2506 #define DDRC_PWRTMG_OFFSET                                                         0XFD070034
2507 #undef DDRC_RFSHCTL0_OFFSET
2508 #define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
2509 #undef DDRC_RFSHCTL3_OFFSET
2510 #define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
2511 #undef DDRC_RFSHTMG_OFFSET
2512 #define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
2513 #undef DDRC_ECCCFG0_OFFSET
2514 #define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
2515 #undef DDRC_ECCCFG1_OFFSET
2516 #define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
2517 #undef DDRC_CRCPARCTL1_OFFSET
2518 #define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
2519 #undef DDRC_CRCPARCTL2_OFFSET
2520 #define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
2521 #undef DDRC_INIT0_OFFSET
2522 #define DDRC_INIT0_OFFSET                                                          0XFD0700D0
2523 #undef DDRC_INIT1_OFFSET
2524 #define DDRC_INIT1_OFFSET                                                          0XFD0700D4
2525 #undef DDRC_INIT2_OFFSET
2526 #define DDRC_INIT2_OFFSET                                                          0XFD0700D8
2527 #undef DDRC_INIT3_OFFSET
2528 #define DDRC_INIT3_OFFSET                                                          0XFD0700DC
2529 #undef DDRC_INIT4_OFFSET
2530 #define DDRC_INIT4_OFFSET                                                          0XFD0700E0
2531 #undef DDRC_INIT5_OFFSET
2532 #define DDRC_INIT5_OFFSET                                                          0XFD0700E4
2533 #undef DDRC_INIT6_OFFSET
2534 #define DDRC_INIT6_OFFSET                                                          0XFD0700E8
2535 #undef DDRC_INIT7_OFFSET
2536 #define DDRC_INIT7_OFFSET                                                          0XFD0700EC
2537 #undef DDRC_DIMMCTL_OFFSET
2538 #define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
2539 #undef DDRC_RANKCTL_OFFSET
2540 #define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
2541 #undef DDRC_DRAMTMG0_OFFSET
2542 #define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
2543 #undef DDRC_DRAMTMG1_OFFSET
2544 #define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
2545 #undef DDRC_DRAMTMG2_OFFSET
2546 #define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
2547 #undef DDRC_DRAMTMG3_OFFSET
2548 #define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
2549 #undef DDRC_DRAMTMG4_OFFSET
2550 #define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
2551 #undef DDRC_DRAMTMG5_OFFSET
2552 #define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
2553 #undef DDRC_DRAMTMG6_OFFSET
2554 #define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
2555 #undef DDRC_DRAMTMG7_OFFSET
2556 #define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
2557 #undef DDRC_DRAMTMG8_OFFSET
2558 #define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
2559 #undef DDRC_DRAMTMG9_OFFSET
2560 #define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
2561 #undef DDRC_DRAMTMG11_OFFSET
2562 #define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
2563 #undef DDRC_DRAMTMG12_OFFSET
2564 #define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
2565 #undef DDRC_ZQCTL0_OFFSET
2566 #define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
2567 #undef DDRC_ZQCTL1_OFFSET
2568 #define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
2569 #undef DDRC_DFITMG0_OFFSET
2570 #define DDRC_DFITMG0_OFFSET                                                        0XFD070190
2571 #undef DDRC_DFITMG1_OFFSET
2572 #define DDRC_DFITMG1_OFFSET                                                        0XFD070194
2573 #undef DDRC_DFILPCFG0_OFFSET
2574 #define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
2575 #undef DDRC_DFILPCFG1_OFFSET
2576 #define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
2577 #undef DDRC_DFIUPD1_OFFSET
2578 #define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
2579 #undef DDRC_DFIMISC_OFFSET
2580 #define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
2581 #undef DDRC_DFITMG2_OFFSET
2582 #define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
2583 #undef DDRC_DBICTL_OFFSET
2584 #define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
2585 #undef DDRC_ADDRMAP0_OFFSET
2586 #define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
2587 #undef DDRC_ADDRMAP1_OFFSET
2588 #define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
2589 #undef DDRC_ADDRMAP2_OFFSET
2590 #define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
2591 #undef DDRC_ADDRMAP3_OFFSET
2592 #define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
2593 #undef DDRC_ADDRMAP4_OFFSET
2594 #define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
2595 #undef DDRC_ADDRMAP5_OFFSET
2596 #define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
2597 #undef DDRC_ADDRMAP6_OFFSET
2598 #define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
2599 #undef DDRC_ADDRMAP7_OFFSET
2600 #define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
2601 #undef DDRC_ADDRMAP8_OFFSET
2602 #define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
2603 #undef DDRC_ADDRMAP9_OFFSET
2604 #define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
2605 #undef DDRC_ADDRMAP10_OFFSET
2606 #define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
2607 #undef DDRC_ADDRMAP11_OFFSET
2608 #define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
2609 #undef DDRC_ODTCFG_OFFSET
2610 #define DDRC_ODTCFG_OFFSET                                                         0XFD070240
2611 #undef DDRC_ODTMAP_OFFSET
2612 #define DDRC_ODTMAP_OFFSET                                                         0XFD070244
2613 #undef DDRC_SCHED_OFFSET
2614 #define DDRC_SCHED_OFFSET                                                          0XFD070250
2615 #undef DDRC_PERFLPR1_OFFSET
2616 #define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
2617 #undef DDRC_PERFWR1_OFFSET
2618 #define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
2619 #undef DDRC_DQMAP5_OFFSET
2620 #define DDRC_DQMAP5_OFFSET                                                         0XFD070294
2621 #undef DDRC_DBG0_OFFSET
2622 #define DDRC_DBG0_OFFSET                                                           0XFD070300
2623 #undef DDRC_DBGCMD_OFFSET
2624 #define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
2625 #undef DDRC_SWCTL_OFFSET
2626 #define DDRC_SWCTL_OFFSET                                                          0XFD070320
2627 #undef DDRC_PCCFG_OFFSET
2628 #define DDRC_PCCFG_OFFSET                                                          0XFD070400
2629 #undef DDRC_PCFGR_0_OFFSET
2630 #define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
2631 #undef DDRC_PCFGW_0_OFFSET
2632 #define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
2633 #undef DDRC_PCTRL_0_OFFSET
2634 #define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
2635 #undef DDRC_PCFGQOS0_0_OFFSET
2636 #define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
2637 #undef DDRC_PCFGQOS1_0_OFFSET
2638 #define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
2639 #undef DDRC_PCFGR_1_OFFSET
2640 #define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
2641 #undef DDRC_PCFGW_1_OFFSET
2642 #define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
2643 #undef DDRC_PCTRL_1_OFFSET
2644 #define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
2645 #undef DDRC_PCFGQOS0_1_OFFSET
2646 #define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
2647 #undef DDRC_PCFGQOS1_1_OFFSET
2648 #define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
2649 #undef DDRC_PCFGR_2_OFFSET
2650 #define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
2651 #undef DDRC_PCFGW_2_OFFSET
2652 #define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
2653 #undef DDRC_PCTRL_2_OFFSET
2654 #define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
2655 #undef DDRC_PCFGQOS0_2_OFFSET
2656 #define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
2657 #undef DDRC_PCFGQOS1_2_OFFSET
2658 #define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
2659 #undef DDRC_PCFGR_3_OFFSET
2660 #define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
2661 #undef DDRC_PCFGW_3_OFFSET
2662 #define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
2663 #undef DDRC_PCTRL_3_OFFSET
2664 #define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
2665 #undef DDRC_PCFGQOS0_3_OFFSET
2666 #define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
2667 #undef DDRC_PCFGQOS1_3_OFFSET
2668 #define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
2669 #undef DDRC_PCFGWQOS0_3_OFFSET
2670 #define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
2671 #undef DDRC_PCFGWQOS1_3_OFFSET
2672 #define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
2673 #undef DDRC_PCFGR_4_OFFSET
2674 #define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
2675 #undef DDRC_PCFGW_4_OFFSET
2676 #define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
2677 #undef DDRC_PCTRL_4_OFFSET
2678 #define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
2679 #undef DDRC_PCFGQOS0_4_OFFSET
2680 #define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
2681 #undef DDRC_PCFGQOS1_4_OFFSET
2682 #define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
2683 #undef DDRC_PCFGWQOS0_4_OFFSET
2684 #define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
2685 #undef DDRC_PCFGWQOS1_4_OFFSET
2686 #define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
2687 #undef DDRC_PCFGR_5_OFFSET
2688 #define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
2689 #undef DDRC_PCFGW_5_OFFSET
2690 #define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
2691 #undef DDRC_PCTRL_5_OFFSET
2692 #define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
2693 #undef DDRC_PCFGQOS0_5_OFFSET
2694 #define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
2695 #undef DDRC_PCFGQOS1_5_OFFSET
2696 #define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
2697 #undef DDRC_PCFGWQOS0_5_OFFSET
2698 #define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
2699 #undef DDRC_PCFGWQOS1_5_OFFSET
2700 #define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
2701 #undef DDRC_SARBASE0_OFFSET
2702 #define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
2703 #undef DDRC_SARSIZE0_OFFSET
2704 #define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
2705 #undef DDRC_SARBASE1_OFFSET
2706 #define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
2707 #undef DDRC_SARSIZE1_OFFSET
2708 #define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
2709 #undef DDRC_DFITMG0_SHADOW_OFFSET
2710 #define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
2711 #undef CRF_APB_RST_DDR_SS_OFFSET
2712 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
2713 #undef DDR_PHY_PGCR0_OFFSET
2714 #define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
2715 #undef DDR_PHY_PGCR2_OFFSET
2716 #define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
2717 #undef DDR_PHY_PGCR5_OFFSET
2718 #define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
2719 #undef DDR_PHY_PTR0_OFFSET
2720 #define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
2721 #undef DDR_PHY_PTR1_OFFSET
2722 #define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
2723 #undef DDR_PHY_DSGCR_OFFSET
2724 #define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
2725 #undef DDR_PHY_DCR_OFFSET
2726 #define DDR_PHY_DCR_OFFSET                                                         0XFD080100
2727 #undef DDR_PHY_DTPR0_OFFSET
2728 #define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
2729 #undef DDR_PHY_DTPR1_OFFSET
2730 #define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
2731 #undef DDR_PHY_DTPR2_OFFSET
2732 #define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
2733 #undef DDR_PHY_DTPR3_OFFSET
2734 #define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
2735 #undef DDR_PHY_DTPR4_OFFSET
2736 #define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
2737 #undef DDR_PHY_DTPR5_OFFSET
2738 #define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
2739 #undef DDR_PHY_DTPR6_OFFSET
2740 #define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
2741 #undef DDR_PHY_RDIMMGCR0_OFFSET
2742 #define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
2743 #undef DDR_PHY_RDIMMGCR1_OFFSET
2744 #define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
2745 #undef DDR_PHY_RDIMMCR1_OFFSET
2746 #define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
2747 #undef DDR_PHY_MR0_OFFSET
2748 #define DDR_PHY_MR0_OFFSET                                                         0XFD080180
2749 #undef DDR_PHY_MR1_OFFSET
2750 #define DDR_PHY_MR1_OFFSET                                                         0XFD080184
2751 #undef DDR_PHY_MR2_OFFSET
2752 #define DDR_PHY_MR2_OFFSET                                                         0XFD080188
2753 #undef DDR_PHY_MR3_OFFSET
2754 #define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
2755 #undef DDR_PHY_MR4_OFFSET
2756 #define DDR_PHY_MR4_OFFSET                                                         0XFD080190
2757 #undef DDR_PHY_MR5_OFFSET
2758 #define DDR_PHY_MR5_OFFSET                                                         0XFD080194
2759 #undef DDR_PHY_MR6_OFFSET
2760 #define DDR_PHY_MR6_OFFSET                                                         0XFD080198
2761 #undef DDR_PHY_MR11_OFFSET
2762 #define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
2763 #undef DDR_PHY_MR12_OFFSET
2764 #define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
2765 #undef DDR_PHY_MR13_OFFSET
2766 #define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
2767 #undef DDR_PHY_MR14_OFFSET
2768 #define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
2769 #undef DDR_PHY_MR22_OFFSET
2770 #define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
2771 #undef DDR_PHY_DTCR0_OFFSET
2772 #define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
2773 #undef DDR_PHY_DTCR1_OFFSET
2774 #define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
2775 #undef DDR_PHY_CATR0_OFFSET
2776 #define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
2777 #undef DDR_PHY_RIOCR5_OFFSET
2778 #define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
2779 #undef DDR_PHY_ACIOCR0_OFFSET
2780 #define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
2781 #undef DDR_PHY_ACIOCR2_OFFSET
2782 #define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
2783 #undef DDR_PHY_ACIOCR3_OFFSET
2784 #define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
2785 #undef DDR_PHY_ACIOCR4_OFFSET
2786 #define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
2787 #undef DDR_PHY_IOVCR0_OFFSET
2788 #define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
2789 #undef DDR_PHY_VTCR0_OFFSET
2790 #define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
2791 #undef DDR_PHY_VTCR1_OFFSET
2792 #define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
2793 #undef DDR_PHY_ACBDLR6_OFFSET
2794 #define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
2795 #undef DDR_PHY_ACBDLR7_OFFSET
2796 #define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
2797 #undef DDR_PHY_ACBDLR8_OFFSET
2798 #define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
2799 #undef DDR_PHY_ZQCR_OFFSET
2800 #define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
2801 #undef DDR_PHY_ZQ0PR0_OFFSET
2802 #define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
2803 #undef DDR_PHY_ZQ0OR0_OFFSET
2804 #define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
2805 #undef DDR_PHY_ZQ0OR1_OFFSET
2806 #define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
2807 #undef DDR_PHY_ZQ1PR0_OFFSET
2808 #define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
2809 #undef DDR_PHY_DX0GCR0_OFFSET
2810 #define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
2811 #undef DDR_PHY_DX0GCR4_OFFSET
2812 #define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
2813 #undef DDR_PHY_DX0GCR5_OFFSET
2814 #define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
2815 #undef DDR_PHY_DX0GCR6_OFFSET
2816 #define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
2817 #undef DDR_PHY_DX0LCDLR2_OFFSET
2818 #define DDR_PHY_DX0LCDLR2_OFFSET                                                   0XFD080788
2819 #undef DDR_PHY_DX0GTR0_OFFSET
2820 #define DDR_PHY_DX0GTR0_OFFSET                                                     0XFD0807C0
2821 #undef DDR_PHY_DX1GCR0_OFFSET
2822 #define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
2823 #undef DDR_PHY_DX1GCR4_OFFSET
2824 #define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
2825 #undef DDR_PHY_DX1GCR5_OFFSET
2826 #define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
2827 #undef DDR_PHY_DX1GCR6_OFFSET
2828 #define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
2829 #undef DDR_PHY_DX1LCDLR2_OFFSET
2830 #define DDR_PHY_DX1LCDLR2_OFFSET                                                   0XFD080888
2831 #undef DDR_PHY_DX1GTR0_OFFSET
2832 #define DDR_PHY_DX1GTR0_OFFSET                                                     0XFD0808C0
2833 #undef DDR_PHY_DX2GCR0_OFFSET
2834 #define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
2835 #undef DDR_PHY_DX2GCR1_OFFSET
2836 #define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
2837 #undef DDR_PHY_DX2GCR4_OFFSET
2838 #define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
2839 #undef DDR_PHY_DX2GCR5_OFFSET
2840 #define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
2841 #undef DDR_PHY_DX2GCR6_OFFSET
2842 #define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
2843 #undef DDR_PHY_DX2LCDLR2_OFFSET
2844 #define DDR_PHY_DX2LCDLR2_OFFSET                                                   0XFD080988
2845 #undef DDR_PHY_DX2GTR0_OFFSET
2846 #define DDR_PHY_DX2GTR0_OFFSET                                                     0XFD0809C0
2847 #undef DDR_PHY_DX3GCR0_OFFSET
2848 #define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
2849 #undef DDR_PHY_DX3GCR1_OFFSET
2850 #define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
2851 #undef DDR_PHY_DX3GCR4_OFFSET
2852 #define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
2853 #undef DDR_PHY_DX3GCR5_OFFSET
2854 #define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
2855 #undef DDR_PHY_DX3GCR6_OFFSET
2856 #define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
2857 #undef DDR_PHY_DX3LCDLR2_OFFSET
2858 #define DDR_PHY_DX3LCDLR2_OFFSET                                                   0XFD080A88
2859 #undef DDR_PHY_DX3GTR0_OFFSET
2860 #define DDR_PHY_DX3GTR0_OFFSET                                                     0XFD080AC0
2861 #undef DDR_PHY_DX4GCR0_OFFSET
2862 #define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
2863 #undef DDR_PHY_DX4GCR1_OFFSET
2864 #define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
2865 #undef DDR_PHY_DX4GCR4_OFFSET
2866 #define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
2867 #undef DDR_PHY_DX4GCR5_OFFSET
2868 #define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
2869 #undef DDR_PHY_DX4GCR6_OFFSET
2870 #define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
2871 #undef DDR_PHY_DX4LCDLR2_OFFSET
2872 #define DDR_PHY_DX4LCDLR2_OFFSET                                                   0XFD080B88
2873 #undef DDR_PHY_DX4GTR0_OFFSET
2874 #define DDR_PHY_DX4GTR0_OFFSET                                                     0XFD080BC0
2875 #undef DDR_PHY_DX5GCR0_OFFSET
2876 #define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
2877 #undef DDR_PHY_DX5GCR1_OFFSET
2878 #define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
2879 #undef DDR_PHY_DX5GCR4_OFFSET
2880 #define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
2881 #undef DDR_PHY_DX5GCR5_OFFSET
2882 #define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
2883 #undef DDR_PHY_DX5GCR6_OFFSET
2884 #define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
2885 #undef DDR_PHY_DX5LCDLR2_OFFSET
2886 #define DDR_PHY_DX5LCDLR2_OFFSET                                                   0XFD080C88
2887 #undef DDR_PHY_DX5GTR0_OFFSET
2888 #define DDR_PHY_DX5GTR0_OFFSET                                                     0XFD080CC0
2889 #undef DDR_PHY_DX6GCR0_OFFSET
2890 #define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
2891 #undef DDR_PHY_DX6GCR1_OFFSET
2892 #define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
2893 #undef DDR_PHY_DX6GCR4_OFFSET
2894 #define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
2895 #undef DDR_PHY_DX6GCR5_OFFSET
2896 #define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
2897 #undef DDR_PHY_DX6GCR6_OFFSET
2898 #define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
2899 #undef DDR_PHY_DX6LCDLR2_OFFSET
2900 #define DDR_PHY_DX6LCDLR2_OFFSET                                                   0XFD080D88
2901 #undef DDR_PHY_DX6GTR0_OFFSET
2902 #define DDR_PHY_DX6GTR0_OFFSET                                                     0XFD080DC0
2903 #undef DDR_PHY_DX7GCR0_OFFSET
2904 #define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
2905 #undef DDR_PHY_DX7GCR1_OFFSET
2906 #define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
2907 #undef DDR_PHY_DX7GCR4_OFFSET
2908 #define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
2909 #undef DDR_PHY_DX7GCR5_OFFSET
2910 #define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
2911 #undef DDR_PHY_DX7GCR6_OFFSET
2912 #define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
2913 #undef DDR_PHY_DX7LCDLR2_OFFSET
2914 #define DDR_PHY_DX7LCDLR2_OFFSET                                                   0XFD080E88
2915 #undef DDR_PHY_DX7GTR0_OFFSET
2916 #define DDR_PHY_DX7GTR0_OFFSET                                                     0XFD080EC0
2917 #undef DDR_PHY_DX8GCR0_OFFSET
2918 #define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
2919 #undef DDR_PHY_DX8GCR1_OFFSET
2920 #define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
2921 #undef DDR_PHY_DX8GCR4_OFFSET
2922 #define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
2923 #undef DDR_PHY_DX8GCR5_OFFSET
2924 #define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
2925 #undef DDR_PHY_DX8GCR6_OFFSET
2926 #define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
2927 #undef DDR_PHY_DX8LCDLR2_OFFSET
2928 #define DDR_PHY_DX8LCDLR2_OFFSET                                                   0XFD080F88
2929 #undef DDR_PHY_DX8GTR0_OFFSET
2930 #define DDR_PHY_DX8GTR0_OFFSET                                                     0XFD080FC0
2931 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET
2932 #define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
2933 #undef DDR_PHY_DX8SL0DXCTL2_OFFSET
2934 #define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
2935 #undef DDR_PHY_DX8SL0IOCR_OFFSET
2936 #define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
2937 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET
2938 #define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
2939 #undef DDR_PHY_DX8SL1DXCTL2_OFFSET
2940 #define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
2941 #undef DDR_PHY_DX8SL1IOCR_OFFSET
2942 #define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
2943 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET
2944 #define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
2945 #undef DDR_PHY_DX8SL2DXCTL2_OFFSET
2946 #define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
2947 #undef DDR_PHY_DX8SL2IOCR_OFFSET
2948 #define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
2949 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET
2950 #define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
2951 #undef DDR_PHY_DX8SL3DXCTL2_OFFSET
2952 #define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
2953 #undef DDR_PHY_DX8SL3IOCR_OFFSET
2954 #define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
2955 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET
2956 #define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
2957 #undef DDR_PHY_DX8SL4DXCTL2_OFFSET
2958 #define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
2959 #undef DDR_PHY_DX8SL4IOCR_OFFSET
2960 #define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
2961 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET
2962 #define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
2963 #undef DDR_PHY_PIR_OFFSET
2964 #define DDR_PHY_PIR_OFFSET                                                         0XFD080004
2965
2966 /*DDR block level reset inside of the DDR Sub System*/
2967 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
2968 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
2969 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
2970 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
2971 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
2972 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
2973
2974 /*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
2975                 evice*/
2976 #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
2977 #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
2978 #undef DDRC_MSTR_DEVICE_CONFIG_MASK
2979 #define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                                             0x03040001
2980 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT                                              30
2981 #define DDRC_MSTR_DEVICE_CONFIG_MASK                                               0xC0000000U
2982
2983 /*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/
2984 #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
2985 #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
2986 #undef DDRC_MSTR_FREQUENCY_MODE_MASK
2987 #define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                                            0x03040001
2988 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT                                             29
2989 #define DDRC_MSTR_FREQUENCY_MODE_MASK                                              0x20000000U
2990
2991 /*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
2992                 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
2993                 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
2994                 ks - 1111 - Four ranks*/
2995 #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
2996 #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
2997 #undef DDRC_MSTR_ACTIVE_RANKS_MASK
2998 #define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                                              0x03040001
2999 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT                                               24
3000 #define DDRC_MSTR_ACTIVE_RANKS_MASK                                                0x03000000U
3001
3002 /*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
3003                  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
3004                 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
3005                 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
3006                  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/
3007 #undef DDRC_MSTR_BURST_RDWR_DEFVAL
3008 #undef DDRC_MSTR_BURST_RDWR_SHIFT
3009 #undef DDRC_MSTR_BURST_RDWR_MASK
3010 #define DDRC_MSTR_BURST_RDWR_DEFVAL                                                0x03040001
3011 #define DDRC_MSTR_BURST_RDWR_SHIFT                                                 16
3012 #define DDRC_MSTR_BURST_RDWR_MASK                                                  0x000F0000U
3013
3014 /*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
3015                 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
3016                 l_off_mode is not supported, and this bit must be set to '0'.*/
3017 #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
3018 #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
3019 #undef DDRC_MSTR_DLL_OFF_MODE_MASK
3020 #define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                                              0x03040001
3021 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT                                               15
3022 #define DDRC_MSTR_DLL_OFF_MODE_MASK                                                0x00008000U
3023
3024 /*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
3025                 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
3026                 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
3027                 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/
3028 #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
3029 #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
3030 #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
3031 #define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                                            0x03040001
3032 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                                             12
3033 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK                                              0x00003000U
3034
3035 /*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
3036                  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
3037                 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/
3038 #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
3039 #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
3040 #undef DDRC_MSTR_GEARDOWN_MODE_MASK
3041 #define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                                             0x03040001
3042 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT                                              11
3043 #define DDRC_MSTR_GEARDOWN_MODE_MASK                                               0x00000800U
3044
3045 /*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
3046                 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
3047                 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
3048                 ing is not supported in DDR4 geardown mode.*/
3049 #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
3050 #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
3051 #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
3052 #define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                                         0x03040001
3053 #define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                                          10
3054 #define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                                           0x00000400U
3055
3056 /*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
3057                 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
3058                  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
3059                 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/
3060 #undef DDRC_MSTR_BURSTCHOP_DEFVAL
3061 #undef DDRC_MSTR_BURSTCHOP_SHIFT
3062 #undef DDRC_MSTR_BURSTCHOP_MASK
3063 #define DDRC_MSTR_BURSTCHOP_DEFVAL                                                 0x03040001
3064 #define DDRC_MSTR_BURSTCHOP_SHIFT                                                  9
3065 #define DDRC_MSTR_BURSTCHOP_MASK                                                   0x00000200U
3066
3067 /*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
3068                 port LPDDR4.*/
3069 #undef DDRC_MSTR_LPDDR4_DEFVAL
3070 #undef DDRC_MSTR_LPDDR4_SHIFT
3071 #undef DDRC_MSTR_LPDDR4_MASK
3072 #define DDRC_MSTR_LPDDR4_DEFVAL                                                    0x03040001
3073 #define DDRC_MSTR_LPDDR4_SHIFT                                                     5
3074 #define DDRC_MSTR_LPDDR4_MASK                                                      0x00000020U
3075
3076 /*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
3077                 DR4.*/
3078 #undef DDRC_MSTR_DDR4_DEFVAL
3079 #undef DDRC_MSTR_DDR4_SHIFT
3080 #undef DDRC_MSTR_DDR4_MASK
3081 #define DDRC_MSTR_DDR4_DEFVAL                                                      0x03040001
3082 #define DDRC_MSTR_DDR4_SHIFT                                                       4
3083 #define DDRC_MSTR_DDR4_MASK                                                        0x00000010U
3084
3085 /*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
3086                 port LPDDR3.*/
3087 #undef DDRC_MSTR_LPDDR3_DEFVAL
3088 #undef DDRC_MSTR_LPDDR3_SHIFT
3089 #undef DDRC_MSTR_LPDDR3_MASK
3090 #define DDRC_MSTR_LPDDR3_DEFVAL                                                    0x03040001
3091 #define DDRC_MSTR_LPDDR3_SHIFT                                                     3
3092 #define DDRC_MSTR_LPDDR3_MASK                                                      0x00000008U
3093
3094 /*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
3095                 port LPDDR2.*/
3096 #undef DDRC_MSTR_LPDDR2_DEFVAL
3097 #undef DDRC_MSTR_LPDDR2_SHIFT
3098 #undef DDRC_MSTR_LPDDR2_MASK
3099 #define DDRC_MSTR_LPDDR2_DEFVAL                                                    0x03040001
3100 #define DDRC_MSTR_LPDDR2_SHIFT                                                     2
3101 #define DDRC_MSTR_LPDDR2_MASK                                                      0x00000004U
3102
3103 /*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
3104                 */
3105 #undef DDRC_MSTR_DDR3_DEFVAL
3106 #undef DDRC_MSTR_DDR3_SHIFT
3107 #undef DDRC_MSTR_DDR3_MASK
3108 #define DDRC_MSTR_DDR3_DEFVAL                                                      0x03040001
3109 #define DDRC_MSTR_DDR3_SHIFT                                                       0
3110 #define DDRC_MSTR_DDR3_MASK                                                        0x00000001U
3111
3112 /*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
3113                  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
3114                 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/
3115 #undef DDRC_MRCTRL0_MR_WR_DEFVAL
3116 #undef DDRC_MRCTRL0_MR_WR_SHIFT
3117 #undef DDRC_MRCTRL0_MR_WR_MASK
3118 #define DDRC_MRCTRL0_MR_WR_DEFVAL                                                  0x00000030
3119 #define DDRC_MRCTRL0_MR_WR_SHIFT                                                   31
3120 #define DDRC_MRCTRL0_MR_WR_MASK                                                    0x80000000U
3121
3122 /*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
3123                  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
3124                 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
3125                 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
3126                 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
3127                 put Inversion of RDIMMs.*/
3128 #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
3129 #undef DDRC_MRCTRL0_MR_ADDR_SHIFT
3130 #undef DDRC_MRCTRL0_MR_ADDR_MASK
3131 #define DDRC_MRCTRL0_MR_ADDR_DEFVAL                                                0x00000030
3132 #define DDRC_MRCTRL0_MR_ADDR_SHIFT                                                 12
3133 #define DDRC_MRCTRL0_MR_ADDR_MASK                                                  0x0000F000U
3134
3135 /*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
3136                  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
3137                 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
3138                  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/
3139 #undef DDRC_MRCTRL0_MR_RANK_DEFVAL
3140 #undef DDRC_MRCTRL0_MR_RANK_SHIFT
3141 #undef DDRC_MRCTRL0_MR_RANK_MASK
3142 #define DDRC_MRCTRL0_MR_RANK_DEFVAL                                                0x00000030
3143 #define DDRC_MRCTRL0_MR_RANK_SHIFT                                                 4
3144 #define DDRC_MRCTRL0_MR_RANK_MASK                                                  0x00000030U
3145
3146 /*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
3147                 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
3148                  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
3149                 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
3150                 n is not allowed - 1 - Software intervention is allowed*/
3151 #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
3152 #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
3153 #undef DDRC_MRCTRL0_SW_INIT_INT_MASK
3154 #define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                                            0x00000030
3155 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                                             3
3156 #define DDRC_MRCTRL0_SW_INIT_INT_MASK                                              0x00000008U
3157
3158 /*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/
3159 #undef DDRC_MRCTRL0_PDA_EN_DEFVAL
3160 #undef DDRC_MRCTRL0_PDA_EN_SHIFT
3161 #undef DDRC_MRCTRL0_PDA_EN_MASK
3162 #define DDRC_MRCTRL0_PDA_EN_DEFVAL                                                 0x00000030
3163 #define DDRC_MRCTRL0_PDA_EN_SHIFT                                                  2
3164 #define DDRC_MRCTRL0_PDA_EN_MASK                                                   0x00000004U
3165
3166 /*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/
3167 #undef DDRC_MRCTRL0_MPR_EN_DEFVAL
3168 #undef DDRC_MRCTRL0_MPR_EN_SHIFT
3169 #undef DDRC_MRCTRL0_MPR_EN_MASK
3170 #define DDRC_MRCTRL0_MPR_EN_DEFVAL                                                 0x00000030
3171 #define DDRC_MRCTRL0_MPR_EN_SHIFT                                                  1
3172 #define DDRC_MRCTRL0_MPR_EN_MASK                                                   0x00000002U
3173
3174 /*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
3175                 d*/
3176 #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
3177 #undef DDRC_MRCTRL0_MR_TYPE_SHIFT
3178 #undef DDRC_MRCTRL0_MR_TYPE_MASK
3179 #define DDRC_MRCTRL0_MR_TYPE_DEFVAL                                                0x00000030
3180 #define DDRC_MRCTRL0_MR_TYPE_SHIFT                                                 0
3181 #define DDRC_MRCTRL0_MR_TYPE_MASK                                                  0x00000001U
3182
3183 /*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
3184                  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
3185                 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/
3186 #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
3187 #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
3188 #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
3189 #define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                                       0x00000000
3190 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                                        8
3191 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                                         0x00000300U
3192
3193 /*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
3194                 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/
3195 #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
3196 #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
3197 #undef DDRC_DERATEEN_DERATE_BYTE_MASK
3198 #define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                                           0x00000000
3199 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT                                            4
3200 #define DDRC_DERATEEN_DERATE_BYTE_MASK                                             0x000000F0U
3201
3202 /*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
3203                 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
3204                 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/
3205 #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
3206 #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
3207 #undef DDRC_DERATEEN_DERATE_VALUE_MASK
3208 #define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                                          0x00000000
3209 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT                                           1
3210 #define DDRC_DERATEEN_DERATE_VALUE_MASK                                            0x00000002U
3211
3212 /*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
3213                 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
3214                 mode.*/
3215 #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
3216 #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
3217 #undef DDRC_DERATEEN_DERATE_ENABLE_MASK
3218 #define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                                         0x00000000
3219 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                                          0
3220 #define DDRC_DERATEEN_DERATE_ENABLE_MASK                                           0x00000001U
3221
3222 /*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
3223                 DR3/LPDDR4. This register must not be set to zero*/
3224 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
3225 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
3226 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
3227 #define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
3228 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                                     0
3229 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                                      0xFFFFFFFFU
3230
3231 /*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
3232                 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
3233                  - Allow transition from Self refresh state*/
3234 #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
3235 #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
3236 #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
3237 #define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                                         0x00000000
3238 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                                          6
3239 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                                           0x00000040U
3240
3241 /*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
3242                 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
3243                 are Exit from Self Refresh*/
3244 #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
3245 #undef DDRC_PWRCTL_SELFREF_SW_SHIFT
3246 #undef DDRC_PWRCTL_SELFREF_SW_MASK
3247 #define DDRC_PWRCTL_SELFREF_SW_DEFVAL                                              0x00000000
3248 #define DDRC_PWRCTL_SELFREF_SW_SHIFT                                               5
3249 #define DDRC_PWRCTL_SELFREF_SW_MASK                                                0x00000020U
3250
3251 /*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
3252                 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
3253                 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
3254                 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/
3255 #undef DDRC_PWRCTL_MPSM_EN_DEFVAL
3256 #undef DDRC_PWRCTL_MPSM_EN_SHIFT
3257 #undef DDRC_PWRCTL_MPSM_EN_MASK
3258 #define DDRC_PWRCTL_MPSM_EN_DEFVAL                                                 0x00000000
3259 #define DDRC_PWRCTL_MPSM_EN_SHIFT                                                  4
3260 #define DDRC_PWRCTL_MPSM_EN_MASK                                                   0x00000010U
3261
3262 /*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
3263                 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
3264                 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
3265                 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
3266                 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/
3267 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
3268 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
3269 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
3270 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL                                 0x00000000
3271 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT                                  3
3272 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK                                   0x00000008U
3273
3274 /*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
3275                 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
3276                 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
3277                  should not be set to 1. FOR PERFORMANCE ONLY.*/
3278 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
3279 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
3280 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
3281 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                                        0x00000000
3282 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                                         2
3283 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                                          0x00000004U
3284
3285 /*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
3286                 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/
3287 #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
3288 #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
3289 #undef DDRC_PWRCTL_POWERDOWN_EN_MASK
3290 #define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                                            0x00000000
3291 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                                             1
3292 #define DDRC_PWRCTL_POWERDOWN_EN_MASK                                              0x00000002U
3293
3294 /*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
3295                 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/
3296 #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
3297 #undef DDRC_PWRCTL_SELFREF_EN_SHIFT
3298 #undef DDRC_PWRCTL_SELFREF_EN_MASK
3299 #define DDRC_PWRCTL_SELFREF_EN_DEFVAL                                              0x00000000
3300 #define DDRC_PWRCTL_SELFREF_EN_SHIFT                                               0
3301 #define DDRC_PWRCTL_SELFREF_EN_MASK                                                0x00000001U
3302
3303 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
3304                 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/
3305 #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
3306 #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
3307 #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
3308 #define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                                          0x00402010
3309 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                                           16
3310 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK                                            0x00FF0000U
3311
3312 /*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
3313                 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
3314                 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/
3315 #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
3316 #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
3317 #undef DDRC_PWRTMG_T_DPD_X4096_MASK
3318 #define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                                             0x00402010
3319 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT                                              8
3320 #define DDRC_PWRTMG_T_DPD_X4096_MASK                                               0x0000FF00U
3321
3322 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
3323                  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/
3324 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
3325 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
3326 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
3327 #define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                                        0x00402010
3328 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                                         0
3329 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                                          0x0000001FU
3330
3331 /*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
3332                 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
3333                  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
3334                 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
3335                 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/
3336 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
3337 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
3338 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
3339 #define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                                        0x00210000
3340 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                                         20
3341 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                                          0x00F00000U
3342
3343 /*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
3344                 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
3345                  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
3346                 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
3347                 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
3348                 ued to the uMCTL2. FOR PERFORMANCE ONLY.*/
3349 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
3350 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
3351 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
3352 #define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                                        0x00210000
3353 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                                         12
3354 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                                          0x0001F000U
3355
3356 /*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
3357                 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
3358                 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
3359                 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
3360                 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
3361                 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
3362                 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
3363                 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
3364                 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
3365                 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
3366                 initiated update is complete.*/
3367 #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
3368 #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
3369 #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
3370 #define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                                         0x00210000
3371 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                                          4
3372 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK                                           0x000001F0U
3373
3374 /*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
3375                 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
3376                 support LPDDR2/LPDDR3/LPDDR4*/
3377 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
3378 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
3379 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
3380 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                                      0x00210000
3381 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                                       2
3382 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                                        0x00000004U
3383
3384 /*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
3385                 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
3386                 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
3387                 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
3388                 uture version of the uMCTL2.*/
3389 #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
3390 #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
3391 #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
3392 #define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                                          0x00000000
3393 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                                           4
3394 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK                                            0x00000070U
3395
3396 /*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
3397                 s automatically updated when exiting reset, so it does not need to be toggled initially.*/
3398 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
3399 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
3400 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
3401 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL                                  0x00000000
3402 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT                                   1
3403 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                                    0x00000002U
3404
3405 /*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
3406                 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
3407                 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
3408                 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
3409                 his register field is changeable on the fly.*/
3410 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
3411 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
3412 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
3413 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                                      0x00000000
3414 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                                       0
3415 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                                        0x00000001U
3416
3417 /*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
3418                  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
3419                 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
3420                 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
3421                 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
3422                 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
3423                 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/
3424 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
3425 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
3426 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
3427 #define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                                          0x0062008C
3428 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                                           16
3429 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                                            0x0FFF0000U
3430
3431 /*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
3432                 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
3433                  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/
3434 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
3435 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
3436 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
3437 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                                       0x0062008C
3438 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                                        15
3439 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                                         0x00008000U
3440
3441 /*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
3442                  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
3443                 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
3444                  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
3445                 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
3446                 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/
3447 #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
3448 #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
3449 #undef DDRC_RFSHTMG_T_RFC_MIN_MASK
3450 #define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                                              0x0062008C
3451 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                                               0
3452 #define DDRC_RFSHTMG_T_RFC_MIN_MASK                                                0x000003FFU
3453
3454 /*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/
3455 #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
3456 #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
3457 #undef DDRC_ECCCFG0_DIS_SCRUB_MASK
3458 #define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                                              0x00000000
3459 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                                               4
3460 #define DDRC_ECCCFG0_DIS_SCRUB_MASK                                                0x00000010U
3461
3462 /*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
3463                  use*/
3464 #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
3465 #undef DDRC_ECCCFG0_ECC_MODE_SHIFT
3466 #undef DDRC_ECCCFG0_ECC_MODE_MASK
3467 #define DDRC_ECCCFG0_ECC_MODE_DEFVAL                                               0x00000000
3468 #define DDRC_ECCCFG0_ECC_MODE_SHIFT                                                0
3469 #define DDRC_ECCCFG0_ECC_MODE_MASK                                                 0x00000007U
3470
3471 /*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
3472                 ng, if ECCCFG1.data_poison_en=1*/
3473 #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
3474 #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
3475 #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
3476 #define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                                        0x00000000
3477 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                                         1
3478 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                                          0x00000002U
3479
3480 /*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/
3481 #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
3482 #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
3483 #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
3484 #define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                                         0x00000000
3485 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                                          0
3486 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK                                           0x00000001U
3487
3488 /*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
3489                 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
3490                 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
3491                 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
3492                 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
3493                 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/
3494 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
3495 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
3496 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
3497 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                                     0x10000200
3498 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                                      24
3499 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                                       0x3F000000U
3500
3501 /*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
3502                 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
3503                 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
3504                 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
3505                 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
3506                  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
3507                 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
3508                 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
3509                 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
3510                 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
3511                 PR Page 1 should be treated as 'Don't care'.*/
3512 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
3513 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
3514 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
3515 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL                                   0x10000200
3516 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                                    9
3517 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                                     0x00000200U
3518
3519 /*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
3520                  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
3521                  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/
3522 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL
3523 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
3524 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK
3525 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL                             0x10000200
3526 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT                              8
3527 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK                               0x00000100U
3528
3529 /*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
3530                 d to support DDR4.*/
3531 #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL
3532 #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
3533 #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK
3534 #define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                                          0x10000200
3535 #define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                                           7
3536 #define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                                            0x00000080U
3537
3538 /*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
3539                  CRC mode register setting in the DRAM.*/
3540 #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL
3541 #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
3542 #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK
3543 #define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                                          0x10000200
3544 #define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                                           4
3545 #define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                                            0x00000010U
3546
3547 /*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
3548                 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
3549                 is register should be 1.*/
3550 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL
3551 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
3552 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK
3553 #define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                                       0x10000200
3554 #define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                                        0
3555 #define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                                         0x00000001U
3556
3557 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
3558                  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
3559                 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/
3560 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL
3561 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
3562 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK
3563 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL                                  0x0030050C
3564 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT                                   16
3565 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                                    0x01FF0000U
3566
3567 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
3568                 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
3569                 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/
3570 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL
3571 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
3572 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK
3573 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL                                  0x0030050C
3574 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT                                   8
3575 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                                    0x00001F00U
3576
3577 /*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
3578                 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
3579                 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
3580                 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
3581                 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
3582                 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
3583                 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
3584                 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
3585                 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
3586                 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
3587                 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
3588                 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
3589                  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
3590                 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
3591                 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
3592                 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
3593                 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
3594                  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
3595                 H-6 Values of 0, 1 and 2 are illegal.*/
3596 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL
3597 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
3598 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK
3599 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL                        0x0030050C
3600 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT                         0
3601 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK                          0x0000003FU
3602
3603 /*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
3604                  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
3605                 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
3606                 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
3607                 or LPDDR4 in this version of the uMCTL2.*/
3608 #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL
3609 #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
3610 #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK
3611 #define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                                           0x0002004E
3612 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                                            30
3613 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK                                             0xC0000000U
3614
3615 /*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
3616                  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
3617                 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
3618                 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/
3619 #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL
3620 #undef DDRC_INIT0_POST_CKE_X1024_SHIFT
3621 #undef DDRC_INIT0_POST_CKE_X1024_MASK
3622 #define DDRC_INIT0_POST_CKE_X1024_DEFVAL                                           0x0002004E
3623 #define DDRC_INIT0_POST_CKE_X1024_SHIFT                                            16
3624 #define DDRC_INIT0_POST_CKE_X1024_MASK                                             0x03FF0000U
3625
3626 /*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
3627                 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
3628                 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
3629                  to next integer value.*/
3630 #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL
3631 #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT
3632 #undef DDRC_INIT0_PRE_CKE_X1024_MASK
3633 #define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                                            0x0002004E
3634 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT                                             0
3635 #define DDRC_INIT0_PRE_CKE_X1024_MASK                                              0x00000FFFU
3636
3637 /*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
3638                 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/
3639 #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL
3640 #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
3641 #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK
3642 #define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                                          0x00000000
3643 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                                           16
3644 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK                                            0x01FF0000U
3645
3646 /*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
3647                 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/
3648 #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL
3649 #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT
3650 #undef DDRC_INIT1_FINAL_WAIT_X32_MASK
3651 #define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                                           0x00000000
3652 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                                            8
3653 #define DDRC_INIT1_FINAL_WAIT_X32_MASK                                             0x00007F00U
3654
3655 /*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
3656                 . There is no known specific requirement for this; it may be set to zero.*/
3657 #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL
3658 #undef DDRC_INIT1_PRE_OCD_X32_SHIFT
3659 #undef DDRC_INIT1_PRE_OCD_X32_MASK
3660 #define DDRC_INIT1_PRE_OCD_X32_DEFVAL                                              0x00000000
3661 #define DDRC_INIT1_PRE_OCD_X32_SHIFT                                               0
3662 #define DDRC_INIT1_PRE_OCD_X32_MASK                                                0x0000000FU
3663
3664 /*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/
3665 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL
3666 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
3667 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK
3668 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                                     0x00000D05
3669 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                                      8
3670 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                                       0x0000FF00U
3671
3672 /*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
3673                 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/
3674 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL
3675 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
3676 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK
3677 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                                      0x00000D05
3678 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                                       0
3679 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                                        0x0000000FU
3680
3681 /*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
3682                  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
3683                 register*/
3684 #undef DDRC_INIT3_MR_DEFVAL
3685 #undef DDRC_INIT3_MR_SHIFT
3686 #undef DDRC_INIT3_MR_MASK
3687 #define DDRC_INIT3_MR_DEFVAL                                                       0x00000510
3688 #define DDRC_INIT3_MR_SHIFT                                                        16
3689 #define DDRC_INIT3_MR_MASK                                                         0xFFFF0000U
3690
3691 /*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
3692                 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
3693                  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
3694                 lue to write to MR2 register*/
3695 #undef DDRC_INIT3_EMR_DEFVAL
3696 #undef DDRC_INIT3_EMR_SHIFT
3697 #undef DDRC_INIT3_EMR_MASK
3698 #define DDRC_INIT3_EMR_DEFVAL                                                      0x00000510
3699 #define DDRC_INIT3_EMR_SHIFT                                                       0
3700 #define DDRC_INIT3_EMR_MASK                                                        0x0000FFFFU
3701
3702 /*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
3703                 egister mDDR: Unused*/
3704 #undef DDRC_INIT4_EMR2_DEFVAL
3705 #undef DDRC_INIT4_EMR2_SHIFT
3706 #undef DDRC_INIT4_EMR2_MASK
3707 #define DDRC_INIT4_EMR2_DEFVAL                                                     0x00000000
3708 #define DDRC_INIT4_EMR2_SHIFT                                                      16
3709 #define DDRC_INIT4_EMR2_MASK                                                       0xFFFF0000U
3710
3711 /*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
3712                 rite to MR13 register*/
3713 #undef DDRC_INIT4_EMR3_DEFVAL
3714 #undef DDRC_INIT4_EMR3_SHIFT
3715 #undef DDRC_INIT4_EMR3_MASK
3716 #define DDRC_INIT4_EMR3_DEFVAL                                                     0x00000000
3717 #define DDRC_INIT4_EMR3_SHIFT                                                      0
3718 #define DDRC_INIT4_EMR3_MASK                                                       0x0000FFFFU
3719
3720 /*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
3721                 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/
3722 #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL
3723 #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
3724 #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK
3725 #define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                                           0x00100004
3726 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                                            16
3727 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK                                             0x00FF0000U
3728
3729 /*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
3730                 3 typically requires 10 us.*/
3731 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL
3732 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
3733 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK
3734 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                                      0x00100004
3735 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                                       0
3736 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                                        0x000003FFU
3737
3738 /*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/
3739 #undef DDRC_INIT6_MR4_DEFVAL
3740 #undef DDRC_INIT6_MR4_SHIFT
3741 #undef DDRC_INIT6_MR4_MASK
3742 #define DDRC_INIT6_MR4_DEFVAL                                                      0x00000000
3743 #define DDRC_INIT6_MR4_SHIFT                                                       16
3744 #define DDRC_INIT6_MR4_MASK                                                        0xFFFF0000U
3745
3746 /*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/
3747 #undef DDRC_INIT6_MR5_DEFVAL
3748 #undef DDRC_INIT6_MR5_SHIFT
3749 #undef DDRC_INIT6_MR5_MASK
3750 #define DDRC_INIT6_MR5_DEFVAL                                                      0x00000000
3751 #define DDRC_INIT6_MR5_SHIFT                                                       0
3752 #define DDRC_INIT6_MR5_MASK                                                        0x0000FFFFU
3753
3754 /*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/
3755 #undef DDRC_INIT7_MR6_DEFVAL
3756 #undef DDRC_INIT7_MR6_SHIFT
3757 #undef DDRC_INIT7_MR6_MASK
3758 #define DDRC_INIT7_MR6_DEFVAL
3759 #define DDRC_INIT7_MR6_SHIFT                                                       16
3760 #define DDRC_INIT7_MR6_MASK                                                        0xFFFF0000U
3761
3762 /*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
3763                 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
3764                  address mirroring is enabled.*/
3765 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL
3766 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
3767 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK
3768 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL                                  0x00000000
3769 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT                                   5
3770 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                                    0x00000020U
3771
3772 /*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3773                  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
3774                 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
3775                 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
3776                 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/
3777 #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL
3778 #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
3779 #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK
3780 #define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                                             0x00000000
3781 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                                              4
3782 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK                                               0x00000010U
3783
3784 /*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3785                  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
3786                 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
3787                 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/
3788 #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL
3789 #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT
3790 #undef DDRC_DIMMCTL_MRS_A17_EN_MASK
3791 #define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                                             0x00000000
3792 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                                              3
3793 #define DDRC_DIMMCTL_MRS_A17_EN_MASK                                               0x00000008U
3794
3795 /*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
3796                 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
3797                 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
3798                 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
3799                 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
3800                  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
3801                 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/
3802 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL
3803 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
3804 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK
3805 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                                     0x00000000
3806 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                                      2
3807 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                                       0x00000004U
3808
3809 /*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
3810                 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
3811                 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
3812                 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
3813                 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
3814                  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
3815                 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
3816                 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
3817                 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
3818                 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
3819                 not implement address mirroring*/
3820 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL
3821 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
3822 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK
3823 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                                      0x00000000
3824 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                                       1
3825 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                                        0x00000002U
3826
3827 /*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
3828                 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
3829                 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
3830                  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/
3831 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL
3832 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
3833 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK
3834 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                                     0x00000000
3835 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                                      0
3836 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                                       0x00000001U
3837
3838 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3839                 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
3840                 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
3841                 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
3842                 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
3843                 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
3844                 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
3845                 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
3846                  to the next integer.*/
3847 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL
3848 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
3849 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK
3850 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                                       0x0000066F
3851 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                                        8
3852 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                                         0x00000F00U
3853
3854 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3855                 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
3856                 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
3857                 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
3858                 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
3859                 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
3860                 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
3861                 ound it up to the next integer.*/
3862 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL
3863 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
3864 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK
3865 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                                       0x0000066F
3866 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                                        4
3867 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                                         0x000000F0U
3868
3869 /*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
3870                 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
3871                 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
3872                 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
3873                 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
3874                 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
3875                 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
3876                 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
3877                 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
3878                 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
3879                 . FOR PERFORMANCE ONLY.*/
3880 #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL
3881 #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT
3882 #undef DDRC_RANKCTL_MAX_RANK_RD_MASK
3883 #define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                                            0x0000066F
3884 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                                             0
3885 #define DDRC_RANKCTL_MAX_RANK_RD_MASK                                              0x0000000FU
3886
3887 /*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
3888                  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
3889                  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
3890                 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
3891                 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
3892                 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/
3893 #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL
3894 #undef DDRC_DRAMTMG0_WR2PRE_SHIFT
3895 #undef DDRC_DRAMTMG0_WR2PRE_MASK
3896 #define DDRC_DRAMTMG0_WR2PRE_DEFVAL                                                0x0F101B0F
3897 #define DDRC_DRAMTMG0_WR2PRE_SHIFT                                                 24
3898 #define DDRC_DRAMTMG0_WR2PRE_MASK                                                  0x7F000000U
3899
3900 /*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
3901                 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
3902                 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/
3903 #undef DDRC_DRAMTMG0_T_FAW_DEFVAL
3904 #undef DDRC_DRAMTMG0_T_FAW_SHIFT
3905 #undef DDRC_DRAMTMG0_T_FAW_MASK
3906 #define DDRC_DRAMTMG0_T_FAW_DEFVAL                                                 0x0F101B0F
3907 #define DDRC_DRAMTMG0_T_FAW_SHIFT                                                  16
3908 #define DDRC_DRAMTMG0_T_FAW_MASK                                                   0x003F0000U
3909
3910 /*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
3911                 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
3912                  No rounding up. Unit: Multiples of 1024 clocks.*/
3913 #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL
3914 #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
3915 #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK
3916 #define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                                             0x0F101B0F
3917 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                                              8
3918 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK                                               0x00007F00U
3919
3920 /*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
3921                 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
3922                  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/
3923 #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL
3924 #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
3925 #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK
3926 #define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                                             0x0F101B0F
3927 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                                              0
3928 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK                                               0x0000003FU
3929
3930 /*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
3931                  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
3932                 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/
3933 #undef DDRC_DRAMTMG1_T_XP_DEFVAL
3934 #undef DDRC_DRAMTMG1_T_XP_SHIFT
3935 #undef DDRC_DRAMTMG1_T_XP_MASK
3936 #define DDRC_DRAMTMG1_T_XP_DEFVAL                                                  0x00080414
3937 #define DDRC_DRAMTMG1_T_XP_SHIFT                                                   16
3938 #define DDRC_DRAMTMG1_T_XP_MASK                                                    0x001F0000U
3939
3940 /*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
3941                 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
3942                 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
3943                 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
3944                 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
3945                 e. Unit: Clocks.*/
3946 #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL
3947 #undef DDRC_DRAMTMG1_RD2PRE_SHIFT
3948 #undef DDRC_DRAMTMG1_RD2PRE_MASK
3949 #define DDRC_DRAMTMG1_RD2PRE_DEFVAL                                                0x00080414
3950 #define DDRC_DRAMTMG1_RD2PRE_SHIFT                                                 8
3951 #define DDRC_DRAMTMG1_RD2PRE_MASK                                                  0x00001F00U
3952
3953 /*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
3954                  up to next integer value. Unit: Clocks.*/
3955 #undef DDRC_DRAMTMG1_T_RC_DEFVAL
3956 #undef DDRC_DRAMTMG1_T_RC_SHIFT
3957 #undef DDRC_DRAMTMG1_T_RC_MASK
3958 #define DDRC_DRAMTMG1_T_RC_DEFVAL                                                  0x00080414
3959 #define DDRC_DRAMTMG1_T_RC_SHIFT                                                   0
3960 #define DDRC_DRAMTMG1_T_RC_MASK                                                    0x0000007FU
3961
3962 /*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
3963                 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
3964                 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
3965                 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
3966                  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3967 #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL
3968 #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
3969 #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK
3970 #define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                                         0x0305060D
3971 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                                          24
3972 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                                           0x3F000000U
3973
3974 /*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
3975                 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
3976                 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
3977                 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
3978                 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3979 #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL
3980 #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT
3981 #undef DDRC_DRAMTMG2_READ_LATENCY_MASK
3982 #define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                                          0x0305060D
3983 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                                           16
3984 #define DDRC_DRAMTMG2_READ_LATENCY_MASK                                            0x003F0000U
3985
3986 /*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
3987                 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
3988                 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
3989                 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
3990                 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
3991                 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
3992                 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
3993                 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
3994 #undef DDRC_DRAMTMG2_RD2WR_DEFVAL
3995 #undef DDRC_DRAMTMG2_RD2WR_SHIFT
3996 #undef DDRC_DRAMTMG2_RD2WR_MASK
3997 #define DDRC_DRAMTMG2_RD2WR_DEFVAL                                                 0x0305060D
3998 #define DDRC_DRAMTMG2_RD2WR_SHIFT                                                  8
3999 #define DDRC_DRAMTMG2_RD2WR_MASK                                                   0x00003F00U
4000
4001 /*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
4002                 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
4003                  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
4004                  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
4005                 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
4006                  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
4007                 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
4008 #undef DDRC_DRAMTMG2_WR2RD_DEFVAL
4009 #undef DDRC_DRAMTMG2_WR2RD_SHIFT
4010 #undef DDRC_DRAMTMG2_WR2RD_MASK
4011 #define DDRC_DRAMTMG2_WR2RD_DEFVAL                                                 0x0305060D
4012 #define DDRC_DRAMTMG2_WR2RD_SHIFT                                                  0
4013 #define DDRC_DRAMTMG2_WR2RD_MASK                                                   0x0000003FU
4014
4015 /*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
4016                  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
4017                 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
4018                  used for the time from a MRW/MRR to a MRW/MRR.*/
4019 #undef DDRC_DRAMTMG3_T_MRW_DEFVAL
4020 #undef DDRC_DRAMTMG3_T_MRW_SHIFT
4021 #undef DDRC_DRAMTMG3_T_MRW_MASK
4022 #define DDRC_DRAMTMG3_T_MRW_DEFVAL                                                 0x0050400C
4023 #define DDRC_DRAMTMG3_T_MRW_SHIFT                                                  20
4024 #define DDRC_DRAMTMG3_T_MRW_MASK                                                   0x3FF00000U
4025
4026 /*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
4027                 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
4028                 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
4029                 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/
4030 #undef DDRC_DRAMTMG3_T_MRD_DEFVAL
4031 #undef DDRC_DRAMTMG3_T_MRD_SHIFT
4032 #undef DDRC_DRAMTMG3_T_MRD_MASK
4033 #define DDRC_DRAMTMG3_T_MRD_DEFVAL                                                 0x0050400C
4034 #define DDRC_DRAMTMG3_T_MRD_SHIFT                                                  12
4035 #define DDRC_DRAMTMG3_T_MRD_MASK                                                   0x0003F000U
4036
4037 /*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
4038                 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
4039                  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
4040                  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/
4041 #undef DDRC_DRAMTMG3_T_MOD_DEFVAL
4042 #undef DDRC_DRAMTMG3_T_MOD_SHIFT
4043 #undef DDRC_DRAMTMG3_T_MOD_MASK
4044 #define DDRC_DRAMTMG3_T_MOD_DEFVAL                                                 0x0050400C
4045 #define DDRC_DRAMTMG3_T_MOD_SHIFT                                                  0
4046 #define DDRC_DRAMTMG3_T_MOD_MASK                                                   0x000003FFU
4047
4048 /*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
4049                 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
4050                 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/
4051 #undef DDRC_DRAMTMG4_T_RCD_DEFVAL
4052 #undef DDRC_DRAMTMG4_T_RCD_SHIFT
4053 #undef DDRC_DRAMTMG4_T_RCD_MASK
4054 #define DDRC_DRAMTMG4_T_RCD_DEFVAL                                                 0x05040405
4055 #define DDRC_DRAMTMG4_T_RCD_SHIFT                                                  24
4056 #define DDRC_DRAMTMG4_T_RCD_MASK                                                   0x1F000000U
4057
4058 /*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
4059                 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
4060                 d it up to the next integer value. Unit: clocks.*/
4061 #undef DDRC_DRAMTMG4_T_CCD_DEFVAL
4062 #undef DDRC_DRAMTMG4_T_CCD_SHIFT
4063 #undef DDRC_DRAMTMG4_T_CCD_MASK
4064 #define DDRC_DRAMTMG4_T_CCD_DEFVAL                                                 0x05040405
4065 #define DDRC_DRAMTMG4_T_CCD_SHIFT                                                  16
4066 #define DDRC_DRAMTMG4_T_CCD_MASK                                                   0x000F0000U
4067
4068 /*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
4069                  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
4070                 it up to the next integer value. Unit: Clocks.*/
4071 #undef DDRC_DRAMTMG4_T_RRD_DEFVAL
4072 #undef DDRC_DRAMTMG4_T_RRD_SHIFT
4073 #undef DDRC_DRAMTMG4_T_RRD_MASK
4074 #define DDRC_DRAMTMG4_T_RRD_DEFVAL                                                 0x05040405
4075 #define DDRC_DRAMTMG4_T_RRD_SHIFT                                                  8
4076 #define DDRC_DRAMTMG4_T_RRD_MASK                                                   0x00000F00U
4077
4078 /*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
4079                 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
4080                 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/
4081 #undef DDRC_DRAMTMG4_T_RP_DEFVAL
4082 #undef DDRC_DRAMTMG4_T_RP_SHIFT
4083 #undef DDRC_DRAMTMG4_T_RP_MASK
4084 #define DDRC_DRAMTMG4_T_RP_DEFVAL                                                  0x05040405
4085 #define DDRC_DRAMTMG4_T_RP_SHIFT                                                   0
4086 #define DDRC_DRAMTMG4_T_RP_MASK                                                    0x0000001FU
4087
4088 /*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
4089                 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
4090                 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
4091                 eger.*/
4092 #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL
4093 #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT
4094 #undef DDRC_DRAMTMG5_T_CKSRX_MASK
4095 #define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                                               0x05050403
4096 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT                                                24
4097 #define DDRC_DRAMTMG5_T_CKSRX_MASK                                                 0x0F000000U
4098
4099 /*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
4100                  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
4101                 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
4102                 to next integer.*/
4103 #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL
4104 #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT
4105 #undef DDRC_DRAMTMG5_T_CKSRE_MASK
4106 #define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                                               0x05050403
4107 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT                                                16
4108 #define DDRC_DRAMTMG5_T_CKSRE_MASK                                                 0x000F0000U
4109
4110 /*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
4111                 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
4112                  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
4113                 .*/
4114 #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL
4115 #undef DDRC_DRAMTMG5_T_CKESR_SHIFT
4116 #undef DDRC_DRAMTMG5_T_CKESR_MASK
4117 #define DDRC_DRAMTMG5_T_CKESR_DEFVAL                                               0x05050403
4118 #define DDRC_DRAMTMG5_T_CKESR_SHIFT                                                8
4119 #define DDRC_DRAMTMG5_T_CKESR_MASK                                                 0x00003F00U
4120
4121 /*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
4122                 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
4123                 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
4124                  next integer value. Unit: Clocks.*/
4125 #undef DDRC_DRAMTMG5_T_CKE_DEFVAL
4126 #undef DDRC_DRAMTMG5_T_CKE_SHIFT
4127 #undef DDRC_DRAMTMG5_T_CKE_MASK
4128 #define DDRC_DRAMTMG5_T_CKE_DEFVAL                                                 0x05050403
4129 #define DDRC_DRAMTMG5_T_CKE_SHIFT                                                  0
4130 #define DDRC_DRAMTMG5_T_CKE_MASK                                                   0x0000001FU
4131
4132 /*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
4133                 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
4134                 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
4135                 devices.*/
4136 #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL
4137 #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT
4138 #undef DDRC_DRAMTMG6_T_CKDPDE_MASK
4139 #define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                                              0x02020005
4140 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                                               24
4141 #define DDRC_DRAMTMG6_T_CKDPDE_MASK                                                0x0F000000U
4142
4143 /*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
4144                 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
4145                 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
4146                 R or LPDDR2 devices.*/
4147 #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL
4148 #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT
4149 #undef DDRC_DRAMTMG6_T_CKDPDX_MASK
4150 #define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                                              0x02020005
4151 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                                               16
4152 #define DDRC_DRAMTMG6_T_CKDPDX_MASK                                                0x000F0000U
4153
4154 /*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
4155                 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
4156                 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
4157                 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
4158 #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL
4159 #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT
4160 #undef DDRC_DRAMTMG6_T_CKCSX_MASK
4161 #define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                                               0x02020005
4162 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT                                                0
4163 #define DDRC_DRAMTMG6_T_CKCSX_MASK                                                 0x0000000FU
4164
4165 /*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
4166                 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
4167                 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
4168                 DDR2/LPDDR3/LPDDR4 devices.*/
4169 #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL
4170 #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT
4171 #undef DDRC_DRAMTMG7_T_CKPDE_MASK
4172 #define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                                               0x00000202
4173 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT                                                8
4174 #define DDRC_DRAMTMG7_T_CKPDE_MASK                                                 0x00000F00U
4175
4176 /*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
4177                 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
4178                 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
4179                 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
4180 #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL
4181 #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT
4182 #undef DDRC_DRAMTMG7_T_CKPDX_MASK
4183 #define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                                               0x00000202
4184 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT                                                0
4185 #define DDRC_DRAMTMG7_T_CKPDX_MASK                                                 0x0000000FU
4186
4187 /*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
4188                 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
4189                  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/
4190 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL
4191 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
4192 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK
4193 #define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                                         0x03034405
4194 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                                          24
4195 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                                           0x7F000000U
4196
4197 /*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
4198                 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
4199                 nsure this is less than or equal to t_xs_x32.*/
4200 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL
4201 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
4202 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK
4203 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                                        0x03034405
4204 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                                         16
4205 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                                          0x007F0000U
4206
4207 /*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
4208                 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
4209                 DR4 SDRAMs.*/
4210 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL
4211 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
4212 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK
4213 #define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                                          0x03034405
4214 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                                           8
4215 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                                            0x00007F00U
4216
4217 /*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
4218                 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
4219                 DDR4 SDRAMs.*/
4220 #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL
4221 #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT
4222 #undef DDRC_DRAMTMG8_T_XS_X32_MASK
4223 #define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                                              0x03034405
4224 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT                                               0
4225 #define DDRC_DRAMTMG8_T_XS_X32_MASK                                                0x0000007FU
4226
4227 /*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/
4228 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL
4229 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
4230 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK
4231 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                                      0x0004040D
4232 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                                       30
4233 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                                        0x40000000U
4234
4235 /*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
4236                 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
4237                 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/
4238 #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL
4239 #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT
4240 #undef DDRC_DRAMTMG9_T_CCD_S_MASK
4241 #define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                                               0x0004040D
4242 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT                                                16
4243 #define DDRC_DRAMTMG9_T_CCD_S_MASK                                                 0x00070000U
4244
4245 /*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
4246                 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
4247                 R4. Unit: Clocks.*/
4248 #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL
4249 #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT
4250 #undef DDRC_DRAMTMG9_T_RRD_S_MASK
4251 #define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                                               0x0004040D
4252 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT                                                8
4253 #define DDRC_DRAMTMG9_T_RRD_S_MASK                                                 0x00000F00U
4254
4255 /*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
4256                 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
4257                  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
4258                 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
4259                 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
4260                 he above equation by 2, and round it up to next integer.*/
4261 #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL
4262 #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT
4263 #undef DDRC_DRAMTMG9_WR2RD_S_MASK
4264 #define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                                               0x0004040D
4265 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT                                                0
4266 #define DDRC_DRAMTMG9_WR2RD_S_MASK                                                 0x0000003FU
4267
4268 /*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
4269                 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
4270                 ples of 32 clocks.*/
4271 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL
4272 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
4273 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK
4274 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                                    0x440C021C
4275 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                                     24
4276 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                                      0x7F000000U
4277
4278 /*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
4279                  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/
4280 #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL
4281 #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT
4282 #undef DDRC_DRAMTMG11_T_MPX_LH_MASK
4283 #define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                                             0x440C021C
4284 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                                              16
4285 #define DDRC_DRAMTMG11_T_MPX_LH_MASK                                               0x001F0000U
4286
4287 /*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
4288                 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/
4289 #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL
4290 #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT
4291 #undef DDRC_DRAMTMG11_T_MPX_S_MASK
4292 #define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                                              0x440C021C
4293 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT                                               8
4294 #define DDRC_DRAMTMG11_T_MPX_S_MASK                                                0x00000300U
4295
4296 /*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
4297                 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
4298                 teger.*/
4299 #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL
4300 #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT
4301 #undef DDRC_DRAMTMG11_T_CKMPE_MASK
4302 #define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                                              0x440C021C
4303 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT                                               0
4304 #define DDRC_DRAMTMG11_T_CKMPE_MASK                                                0x0000001FU
4305
4306 /*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
4307                 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/
4308 #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL
4309 #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT
4310 #undef DDRC_DRAMTMG12_T_CMDCKE_MASK
4311 #define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                                             0x00020610
4312 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                                              16
4313 #define DDRC_DRAMTMG12_T_CMDCKE_MASK                                               0x00030000U
4314
4315 /*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
4316                 /2) and round it up to next integer value.*/
4317 #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL
4318 #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
4319 #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK
4320 #define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                                            0x00020610
4321 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                                             8
4322 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK                                              0x00000F00U
4323
4324 /*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
4325                 s to (tMRD_PDA/2) and round it up to next integer value.*/
4326 #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL
4327 #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
4328 #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK
4329 #define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                                            0x00020610
4330 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                                             0
4331 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK                                              0x0000001FU
4332
4333 /*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
4334                 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
4335                 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4336 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL
4337 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
4338 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK
4339 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                                             0x02000040
4340 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                                              31
4341 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                                               0x80000000U
4342
4343 /*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
4344                 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
4345                 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
4346                 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4347 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL
4348 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
4349 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK
4350 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                                            0x02000040
4351 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                                             30
4352 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                                              0x40000000U
4353
4354 /*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
4355                 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
4356                 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4357 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL
4358 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
4359 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK
4360 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                                      0x02000040
4361 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                                       29
4362 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                                        0x20000000U
4363
4364 /*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
4365                 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
4366                 gns supporting DDR4 devices.*/
4367 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL
4368 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
4369 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK
4370 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                                          0x02000040
4371 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                                           28
4372 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                                            0x10000000U
4373
4374 /*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
4375                 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
4376                 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
4377                 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
4378                 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4379 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL
4380 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
4381 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK
4382 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                                           0x02000040
4383 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                                            16
4384 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                                             0x07FF0000U
4385
4386 /*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
4387                 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
4388                 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
4389                 s.*/
4390 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL
4391 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
4392 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK
4393 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                                          0x02000040
4394 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                                           0
4395 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                                            0x000003FFU
4396
4397 /*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
4398                 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
4399                 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/
4400 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL
4401 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
4402 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK
4403 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                                          0x02000100
4404 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                                           20
4405 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                                            0x3FF00000U
4406
4407 /*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
4408                 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
4409                 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4410 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL
4411 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
4412 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK
4413 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL                               0x02000100
4414 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT                                0
4415 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK                                 0x000FFFFFU
4416
4417 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
4418                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
4419                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
4420                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
4421 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL
4422 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
4423 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK
4424 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                                       0x07020002
4425 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                                        24
4426 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                                         0x1F000000U
4427
4428 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
4429                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
4430                 fer to PHY specification for correct value.*/
4431 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL
4432 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
4433 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK
4434 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                                     0x07020002
4435 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                                      23
4436 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                                       0x00800000U
4437
4438 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
4439                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
4440                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
4441                  latency through the RDIMM. Unit: Clocks*/
4442 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL
4443 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
4444 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK
4445 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                                        0x07020002
4446 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                                         16
4447 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                                          0x003F0000U
4448
4449 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
4450                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
4451                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
4452                 e.*/
4453 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL
4454 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
4455 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK
4456 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                                     0x07020002
4457 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                                      15
4458 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                                       0x00008000U
4459
4460 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
4461                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
4462                 te, max supported value is 8. Unit: Clocks*/
4463 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL
4464 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
4465 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK
4466 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                                        0x07020002
4467 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                                         8
4468 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                                          0x00003F00U
4469
4470 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
4471                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
4472                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
4473                 rough the RDIMM.*/
4474 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL
4475 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
4476 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK
4477 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                                         0x07020002
4478 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                                          0
4479 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                                           0x0000003FU
4480
4481 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
4482                 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
4483                 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/
4484 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL
4485 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
4486 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK
4487 #define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                                          0x00000404
4488 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                                           28
4489 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                                            0xF0000000U
4490
4491 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
4492                  is driven.*/
4493 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL
4494 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
4495 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK
4496 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                                        0x00000404
4497 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                                         24
4498 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                                          0x03000000U
4499
4500 /*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
4501                 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
4502                  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
4503                 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
4504                 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
4505                 : Clocks*/
4506 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL
4507 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
4508 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK
4509 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                                     0x00000404
4510 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                                      16
4511 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                                       0x001F0000U
4512
4513 /*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
4514                 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
4515                 ligned, this timing parameter should be rounded up to the next integer value.*/
4516 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL
4517 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
4518 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK
4519 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL                                 0x00000404
4520 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT                                  8
4521 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK                                   0x00000F00U
4522
4523 /*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
4524                 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
4525                 not phase aligned, this timing parameter should be rounded up to the next integer value.*/
4526 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL
4527 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
4528 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK
4529 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL                                  0x00000404
4530 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT                                   0
4531 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                                    0x0000000FU
4532
4533 /*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
4534                 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/
4535 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL
4536 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
4537 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK
4538 #define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                                         0x07000000
4539 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                                          24
4540 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                                           0x0F000000U
4541
4542 /*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
4543                 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
4544                 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
4545                 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
4546                 .*/
4547 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL
4548 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
4549 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK
4550 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                                    0x07000000
4551 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                                     20
4552 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                                      0x00F00000U
4553
4554 /*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
4555                 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/
4556 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL
4557 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
4558 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK
4559 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                                        0x07000000
4560 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                                         16
4561 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                                          0x00010000U
4562
4563 /*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
4564                 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
4565                 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
4566                 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4567 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL
4568 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
4569 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK
4570 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                                     0x07000000
4571 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                                      12
4572 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                                       0x0000F000U
4573
4574 /*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4575 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL
4576 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
4577 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK
4578 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                                         0x07000000
4579 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                                          8
4580 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                                           0x00000100U
4581
4582 /*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
4583                 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
4584                 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
4585                  cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4586 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL
4587 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
4588 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK
4589 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                                     0x07000000
4590 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                                      4
4591 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                                       0x000000F0U
4592
4593 /*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4594 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL
4595 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
4596 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK
4597 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                                         0x07000000
4598 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                                          0
4599 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                                           0x00000001U
4600
4601 /*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
4602                 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
4603                  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
4604                 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/
4605 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL
4606 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
4607 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK
4608 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL                                   0x00000000
4609 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                                    4
4610 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                                     0x000000F0U
4611
4612 /*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
4613                 only present for designs supporting DDR4 devices.*/
4614 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL
4615 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
4616 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK
4617 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                                       0x00000000
4618 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                                        0
4619 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                                         0x00000001U
4620
4621 /*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
4622                 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
4623                 t read request when the uMCTL2 is idle. Unit: 1024 clocks*/
4624 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL
4625 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
4626 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK
4627 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL                       0x00000000
4628 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT                        16
4629 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK                         0x00FF0000U
4630
4631 /*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
4632                 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
4633                 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
4634                 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
4635                 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
4636                 024. Unit: 1024 clocks*/
4637 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL
4638 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
4639 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK
4640 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL                       0x00000000
4641 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT                        0
4642 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK                         0x000000FFU
4643
4644 /*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/
4645 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL
4646 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
4647 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK
4648 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL                                   0x00000001
4649 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                                    2
4650 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                                     0x00000004U
4651
4652 /*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
4653                 in designs configured to support DDR4 and LPDDR4.*/
4654 #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL
4655 #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
4656 #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK
4657 #define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                                           0x00000001
4658 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                                            1
4659 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK                                             0x00000002U
4660
4661 /*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
4662                 ion*/
4663 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL
4664 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
4665 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK
4666 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL                                   0x00000001
4667 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                                    0
4668 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                                     0x00000001U
4669
4670 /*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
4671                 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/
4672 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL
4673 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
4674 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK
4675 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                                       0x00000202
4676 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                                        8
4677 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                                         0x00003F00U
4678
4679 /*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
4680                 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/
4681 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL
4682 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
4683 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK
4684 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                                       0x00000202
4685 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                                        0
4686 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                                         0x0000003FU
4687
4688 /*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
4689                 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/
4690 #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL
4691 #undef DDRC_DBICTL_RD_DBI_EN_SHIFT
4692 #undef DDRC_DBICTL_RD_DBI_EN_MASK
4693 #define DDRC_DBICTL_RD_DBI_EN_DEFVAL                                               0x00000001
4694 #define DDRC_DBICTL_RD_DBI_EN_SHIFT                                                2
4695 #define DDRC_DBICTL_RD_DBI_EN_MASK                                                 0x00000004U
4696
4697 /*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
4698                 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/
4699 #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL
4700 #undef DDRC_DBICTL_WR_DBI_EN_SHIFT
4701 #undef DDRC_DBICTL_WR_DBI_EN_MASK
4702 #define DDRC_DBICTL_WR_DBI_EN_DEFVAL                                               0x00000001
4703 #define DDRC_DBICTL_WR_DBI_EN_SHIFT                                                1
4704 #define DDRC_DBICTL_WR_DBI_EN_MASK                                                 0x00000002U
4705
4706 /*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
4707                 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
4708                 : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/
4709 #undef DDRC_DBICTL_DM_EN_DEFVAL
4710 #undef DDRC_DBICTL_DM_EN_SHIFT
4711 #undef DDRC_DBICTL_DM_EN_MASK
4712 #define DDRC_DBICTL_DM_EN_DEFVAL                                                   0x00000001
4713 #define DDRC_DBICTL_DM_EN_SHIFT                                                    0
4714 #define DDRC_DBICTL_DM_EN_MASK                                                     0x00000001U
4715
4716 /*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
4717                  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/
4718 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4719 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
4720 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK
4721 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4722 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                                        0
4723 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                                         0x0000001FU
4724
4725 /*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
4726                 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/
4727 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL
4728 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
4729 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK
4730 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                                       0x00000000
4731 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                                        16
4732 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                                         0x001F0000U
4733
4734 /*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
4735                 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4736 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL
4737 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
4738 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK
4739 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                                       0x00000000
4740 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                                        8
4741 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                                         0x00001F00U
4742
4743 /*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
4744                 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4745 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL
4746 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
4747 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK
4748 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                                       0x00000000
4749 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                                        0
4750 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                                         0x0000001FU
4751
4752 /*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
4753                 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
4754                  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
4755                  this field. If set to 15, this column address bit is set to 0.*/
4756 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL
4757 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
4758 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK
4759 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                                        0x00000000
4760 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                                         24
4761 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                                          0x0F000000U
4762
4763 /*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
4764                 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
4765                 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
4766                 this field. If set to 15, this column address bit is set to 0.*/
4767 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL
4768 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
4769 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK
4770 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                                        0x00000000
4771 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                                         16
4772 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                                          0x000F0000U
4773
4774 /*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
4775                 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
4776                 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
4777                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
4778                  this case.*/
4779 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL
4780 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
4781 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK
4782 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                                        0x00000000
4783 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                                         8
4784 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                                          0x00000F00U
4785
4786 /*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
4787                 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
4788                 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
4789                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/
4790 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL
4791 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
4792 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK
4793 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                                        0x00000000
4794 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                                         0
4795 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                                          0x0000000FU
4796
4797 /*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
4798                 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
4799                 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
4800                  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
4801                 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
4802                 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
4803                  hence column bit 10 is used.*/
4804 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL
4805 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
4806 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK
4807 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                                        0x00000000
4808 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                                         24
4809 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                                          0x0F000000U
4810
4811 /*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
4812                 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
4813                  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
4814                 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
4815                 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
4816                 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
4817                 .*/
4818 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL
4819 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
4820 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK
4821 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                                        0x00000000
4822 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                                         16
4823 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                                          0x000F0000U
4824
4825 /*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
4826                 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
4827                 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
4828                 this field. If set to 15, this column address bit is set to 0.*/
4829 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL
4830 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
4831 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK
4832 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                                        0x00000000
4833 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                                         8
4834 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                                          0x00000F00U
4835
4836 /*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
4837                 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
4838                 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
4839                 this field. If set to 15, this column address bit is set to 0.*/
4840 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL
4841 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
4842 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK
4843 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                                        0x00000000
4844 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                                         0
4845 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                                          0x0000000FU
4846
4847 /*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
4848                 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
4849                 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
4850                 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
4851                 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
4852                 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/
4853 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL
4854 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
4855 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK
4856 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                                       0x00000000
4857 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                                        8
4858 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                                         0x00000F00U
4859
4860 /*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
4861                 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
4862                 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
4863                 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
4864                 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
4865                 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
4866                 nce column bit 10 is used.*/
4867 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL
4868 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
4869 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK
4870 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                                       0x00000000
4871 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                                        0
4872 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                                         0x0000000FU
4873
4874 /*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
4875                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/
4876 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL
4877 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
4878 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK
4879 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                                       0x00000000
4880 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                                        24
4881 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                                         0x0F000000U
4882
4883 /*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
4884                 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
4885                 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
4886                 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/
4887 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL
4888 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
4889 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK
4890 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                                     0x00000000
4891 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                                      16
4892 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                                       0x000F0000U
4893
4894 /*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
4895                  each of the row address bits is determined by adding the internal base to the value of this field.*/
4896 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL
4897 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
4898 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK
4899 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                                        0x00000000
4900 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                                         8
4901 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                                          0x00000F00U
4902
4903 /*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
4904                  each of the row address bits is determined by adding the internal base to the value of this field.*/
4905 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL
4906 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
4907 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK
4908 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                                        0x00000000
4909 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                                         0
4910 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                                          0x0000000FU
4911
4912 /*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
4913                 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
4914                 y in designs configured to support LPDDR3.*/
4915 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL
4916 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
4917 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK
4918 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                                       0x00000000
4919 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                                        31
4920 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                                         0x80000000U
4921
4922 /*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
4923                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/
4924 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL
4925 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
4926 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK
4927 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                                       0x00000000
4928 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                                        24
4929 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                                         0x0F000000U
4930
4931 /*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
4932                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/
4933 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL
4934 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
4935 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK
4936 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                                       0x00000000
4937 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                                        16
4938 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                                         0x000F0000U
4939
4940 /*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
4941                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/
4942 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL
4943 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
4944 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK
4945 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                                       0x00000000
4946 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                                        8
4947 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                                         0x00000F00U
4948
4949 /*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
4950                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/
4951 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL
4952 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
4953 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK
4954 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                                       0x00000000
4955 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                                        0
4956 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                                         0x0000000FU
4957
4958 /*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
4959                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/
4960 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL
4961 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
4962 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK
4963 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                                       0x00000000
4964 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                                        8
4965 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                                         0x00000F00U
4966
4967 /*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
4968                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/
4969 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL
4970 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
4971 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK
4972 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                                       0x00000000
4973 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                                        0
4974 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                                         0x0000000FU
4975
4976 /*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
4977                 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
4978                 et to 31, bank group address bit 1 is set to 0.*/
4979 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL
4980 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
4981 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK
4982 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                                         0x00000000
4983 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                                          8
4984 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                                           0x00001F00U
4985
4986 /*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
4987                 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/
4988 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL
4989 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
4990 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK
4991 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                                         0x00000000
4992 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                                          0
4993 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                                           0x0000001FU
4994
4995 /*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
4996                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4997                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4998 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL
4999 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
5000 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK
5001 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                                        0x00000000
5002 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                                         24
5003 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                                          0x0F000000U
5004
5005 /*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
5006                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
5007                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5008 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL
5009 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
5010 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK
5011 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                                        0x00000000
5012 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                                         16
5013 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                                          0x000F0000U
5014
5015 /*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
5016                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
5017                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5018 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL
5019 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
5020 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK
5021 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                                        0x00000000
5022 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                                         8
5023 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                                          0x00000F00U
5024
5025 /*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
5026                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
5027                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5028 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL
5029 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
5030 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK
5031 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                                        0x00000000
5032 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                                         0
5033 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                                          0x0000000FU
5034
5035 /*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
5036                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
5037                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5038 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL
5039 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
5040 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK
5041 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                                       0x00000000
5042 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                                        24
5043 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                                         0x0F000000U
5044
5045 /*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
5046                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
5047                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5048 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL
5049 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
5050 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK
5051 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                                       0x00000000
5052 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                                        16
5053 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                                         0x000F0000U
5054
5055 /*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
5056                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
5057                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5058 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL
5059 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
5060 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK
5061 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                                       0x00000000
5062 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                                        8
5063 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                                         0x00000F00U
5064
5065 /*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
5066                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
5067                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5068 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL
5069 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
5070 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK
5071 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                                       0x00000000
5072 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                                        0
5073 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                                         0x0000000FU
5074
5075 /*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
5076                 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
5077                 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
5078 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
5079 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
5080 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK
5081 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
5082 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                                       0
5083 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                                        0x0000000FU
5084
5085 /*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
5086                 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
5087                 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
5088                 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/
5089 #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL
5090 #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
5091 #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK
5092 #define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                                             0x04000400
5093 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                                              24
5094 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK                                               0x0F000000U
5095
5096 /*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
5097                 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
5098                 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
5099                  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/
5100 #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL
5101 #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
5102 #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK
5103 #define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                                            0x04000400
5104 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                                             16
5105 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK                                              0x001F0000U
5106
5107 /*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
5108                  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
5109                 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
5110                 )*/
5111 #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL
5112 #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
5113 #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK
5114 #define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                                             0x04000400
5115 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                                              8
5116 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK                                               0x00000F00U
5117
5118 /*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
5119                 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
5120                 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
5121                 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
5122                 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
5123                 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/
5124 #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL
5125 #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
5126 #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK
5127 #define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                                            0x04000400
5128 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                                             2
5129 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK                                              0x0000007CU
5130
5131 /*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
5132                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
5133                  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
5134 #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL
5135 #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
5136 #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK
5137 #define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                                            0x00002211
5138 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                                             12
5139 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK                                              0x00003000U
5140
5141 /*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
5142                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
5143                 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
5144 #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL
5145 #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
5146 #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK
5147 #define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                                            0x00002211
5148 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                                             8
5149 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK                                              0x00000300U
5150
5151 /*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
5152                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
5153                  etc. For each rank, set its bit to 1 to enable its ODT.*/
5154 #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL
5155 #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
5156 #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK
5157 #define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                                            0x00002211
5158 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                                             4
5159 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK                                              0x00000030U
5160
5161 /*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
5162                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
5163                 etc. For each rank, set its bit to 1 to enable its ODT.*/
5164 #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL
5165 #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
5166 #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK
5167 #define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                                            0x00002211
5168 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                                             0
5169 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK                                              0x00000003U
5170
5171 /*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
5172                 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
5173                 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
5174                 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
5175                 OR PERFORMANCE ONLY*/
5176 #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL
5177 #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
5178 #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK
5179 #define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                                            0x00002005
5180 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                                             24
5181 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK                                              0x7F000000U
5182
5183 /*UNUSED*/
5184 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL
5185 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
5186 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK
5187 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL                                   0x00002005
5188 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                                    16
5189 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                                     0x00FF0000U
5190
5191 /*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
5192                  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
5193                 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
5194                 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
5195                  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
5196                 sing out of single bit error correction RMW operation.*/
5197 #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL
5198 #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
5199 #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK
5200 #define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                                          0x00002005
5201 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                                           8
5202 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                                            0x00003F00U
5203
5204 /*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
5205                 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
5206                 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
5207                 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
5208                 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
5209                 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
5210                 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
5211                 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/
5212 #undef DDRC_SCHED_PAGECLOSE_DEFVAL
5213 #undef DDRC_SCHED_PAGECLOSE_SHIFT
5214 #undef DDRC_SCHED_PAGECLOSE_MASK
5215 #define DDRC_SCHED_PAGECLOSE_DEFVAL                                                0x00002005
5216 #define DDRC_SCHED_PAGECLOSE_SHIFT                                                 2
5217 #define DDRC_SCHED_PAGECLOSE_MASK                                                  0x00000004U
5218
5219 /*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/
5220 #undef DDRC_SCHED_PREFER_WRITE_DEFVAL
5221 #undef DDRC_SCHED_PREFER_WRITE_SHIFT
5222 #undef DDRC_SCHED_PREFER_WRITE_MASK
5223 #define DDRC_SCHED_PREFER_WRITE_DEFVAL                                             0x00002005
5224 #define DDRC_SCHED_PREFER_WRITE_SHIFT                                              1
5225 #define DDRC_SCHED_PREFER_WRITE_MASK                                               0x00000002U
5226
5227 /*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
5228                 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
5229                 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
5230                 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/
5231 #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL
5232 #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
5233 #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK
5234 #define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                                          0x00002005
5235 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                                           0
5236 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                                            0x00000001U
5237
5238 /*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
5239                  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
5240 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL
5241 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
5242 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK
5243 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL                                   0x0F00007F
5244 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                                    24
5245 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                                     0xFF000000U
5246
5247 /*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
5248                 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
5249                 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
5250 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL
5251 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
5252 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK
5253 #define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                                        0x0F00007F
5254 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                                         0
5255 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                                          0x0000FFFFU
5256
5257 /*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
5258                 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
5259 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL
5260 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
5261 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK
5262 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                                      0x0F00007F
5263 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                                       24
5264 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                                        0xFF000000U
5265
5266 /*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
5267                 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
5268                 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
5269 #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL
5270 #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT
5271 #undef DDRC_PERFWR1_W_MAX_STARVE_MASK
5272 #define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                                           0x0F00007F
5273 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                                            0
5274 #define DDRC_PERFWR1_W_MAX_STARVE_MASK                                             0x0000FFFFU
5275
5276 /*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
5277                 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
5278                 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
5279                 port DDR4.*/
5280 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
5281 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
5282 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK
5283 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
5284 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                                         0
5285 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                                          0x00000001U
5286
5287 /*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
5288                 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
5289                 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/
5290 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL
5291 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
5292 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK
5293 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                                    0x00000000
5294 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                                     4
5295 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                                      0x00000010U
5296
5297 /*When 1, disable write combine. FOR DEBUG ONLY*/
5298 #undef DDRC_DBG0_DIS_WC_DEFVAL
5299 #undef DDRC_DBG0_DIS_WC_SHIFT
5300 #undef DDRC_DBG0_DIS_WC_MASK
5301 #define DDRC_DBG0_DIS_WC_DEFVAL                                                    0x00000000
5302 #define DDRC_DBG0_DIS_WC_SHIFT                                                     0
5303 #define DDRC_DBG0_DIS_WC_MASK                                                      0x00000001U
5304
5305 /*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
5306                 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
5307                 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
5308                 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
5309                  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/
5310 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL
5311 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
5312 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK
5313 #define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                                            0x00000000
5314 #define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                                             31
5315 #define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                                              0x80000000U
5316
5317 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
5318                 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/
5319 #undef DDRC_DBGCMD_CTRLUPD_DEFVAL
5320 #undef DDRC_DBGCMD_CTRLUPD_SHIFT
5321 #undef DDRC_DBGCMD_CTRLUPD_MASK
5322 #define DDRC_DBGCMD_CTRLUPD_DEFVAL                                                 0x00000000
5323 #define DDRC_DBGCMD_CTRLUPD_SHIFT                                                  5
5324 #define DDRC_DBGCMD_CTRLUPD_MASK                                                   0x00000020U
5325
5326 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
5327                 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
5328                 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
5329                 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
5330                 de.*/
5331 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL
5332 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
5333 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK
5334 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                                          0x00000000
5335 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                                           4
5336 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                                            0x00000010U
5337
5338 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
5339                 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
5340                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
5341                 wn operating modes or Maximum Power Saving Mode.*/
5342 #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL
5343 #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT
5344 #undef DDRC_DBGCMD_RANK1_REFRESH_MASK
5345 #define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                                           0x00000000
5346 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                                            1
5347 #define DDRC_DBGCMD_RANK1_REFRESH_MASK                                             0x00000002U
5348
5349 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
5350                 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
5351                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
5352                 wn operating modes or Maximum Power Saving Mode.*/
5353 #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL
5354 #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT
5355 #undef DDRC_DBGCMD_RANK0_REFRESH_MASK
5356 #define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                                           0x00000000
5357 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                                            0
5358 #define DDRC_DBGCMD_RANK0_REFRESH_MASK                                             0x00000001U
5359
5360 /*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
5361                 egister to 1 once programming is done.*/
5362 #undef DDRC_SWCTL_SW_DONE_DEFVAL
5363 #undef DDRC_SWCTL_SW_DONE_SHIFT
5364 #undef DDRC_SWCTL_SW_DONE_MASK
5365 #define DDRC_SWCTL_SW_DONE_DEFVAL
5366 #define DDRC_SWCTL_SW_DONE_SHIFT                                                   0
5367 #define DDRC_SWCTL_SW_DONE_MASK                                                    0x00000001U
5368
5369 /*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
5370                 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
5371                 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
5372                 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
5373                 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
5374                 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
5375                 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
5376                 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
5377                 -AC is enabled*/
5378 #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL
5379 #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT
5380 #undef DDRC_PCCFG_BL_EXP_MODE_MASK
5381 #define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                                              0x00000000
5382 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT                                               8
5383 #define DDRC_PCCFG_BL_EXP_MODE_MASK                                                0x00000100U
5384
5385 /*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
5386                 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
5387                 ge DDRC transactions.*/
5388 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL
5389 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
5390 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK
5391 #define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                                          0x00000000
5392 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                                           4
5393 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                                            0x00000010U
5394
5395 /*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
5396                 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
5397                 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/
5398 #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL
5399 #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
5400 #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK
5401 #define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                                           0x00000000
5402 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                                            0
5403 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK                                             0x00000001U
5404
5405 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5406                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5407                 imit register.*/
5408 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL
5409 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
5410 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK
5411 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5412 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5413 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5414
5415 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5416                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5417                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5418                 ess handshaking (it is not associated with any particular command).*/
5419 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL
5420 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
5421 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK
5422 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5423 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                                       13
5424 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5425
5426 /*If set to 1, enables aging function for the read channel of the port.*/
5427 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL
5428 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
5429 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK
5430 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5431 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                                        12
5432 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                                         0x00001000U
5433
5434 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5435                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5436                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5437                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5438                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5439                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5440                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5441                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5442                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5443                 he two LSBs of this register field are tied internally to 2'b00.*/
5444 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL
5445 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
5446 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK
5447 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5448 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                                        0
5449 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5450
5451 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5452                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5453                 imit register.*/
5454 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL
5455 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
5456 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK
5457 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5458 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5459 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5460
5461 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5462                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5463                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5464                 not associated with any particular command).*/
5465 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL
5466 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
5467 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK
5468 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5469 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                                       13
5470 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5471
5472 /*If set to 1, enables aging function for the write channel of the port.*/
5473 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL
5474 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
5475 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK
5476 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5477 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                                        12
5478 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                                         0x00001000U
5479
5480 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5481                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5482                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5483                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5484                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5485                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5486                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5487                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5488 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL
5489 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
5490 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK
5491 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5492 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                                        0
5493 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5494
5495 /*Enables port n.*/
5496 #undef DDRC_PCTRL_0_PORT_EN_DEFVAL
5497 #undef DDRC_PCTRL_0_PORT_EN_SHIFT
5498 #undef DDRC_PCTRL_0_PORT_EN_MASK
5499 #define DDRC_PCTRL_0_PORT_EN_DEFVAL
5500 #define DDRC_PCTRL_0_PORT_EN_SHIFT                                                 0
5501 #define DDRC_PCTRL_0_PORT_EN_MASK                                                  0x00000001U
5502
5503 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5504                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5505                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5506 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL
5507 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
5508 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK
5509 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5510 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                                     20
5511 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                                      0x00300000U
5512
5513 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5514                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5515                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5516 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL
5517 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
5518 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK
5519 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5520 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                                     16
5521 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                                      0x00030000U
5522
5523 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5524                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5525                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5526                  values.*/
5527 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL
5528 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
5529 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK
5530 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
5531 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                                      0
5532 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5533
5534 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5535 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL
5536 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
5537 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK
5538 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5539 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5540 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5541
5542 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5543 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL
5544 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
5545 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK
5546 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5547 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5548 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5549
5550 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5551                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5552                 imit register.*/
5553 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL
5554 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
5555 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK
5556 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5557 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5558 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5559
5560 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5561                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5562                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5563                 ess handshaking (it is not associated with any particular command).*/
5564 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL
5565 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
5566 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK
5567 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5568 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                                       13
5569 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5570
5571 /*If set to 1, enables aging function for the read channel of the port.*/
5572 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL
5573 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
5574 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK
5575 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5576 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                                        12
5577 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                                         0x00001000U
5578
5579 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5580                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5581                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5582                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5583                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5584                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5585                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5586                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5587                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5588                 he two LSBs of this register field are tied internally to 2'b00.*/
5589 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL
5590 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
5591 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK
5592 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5593 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                                        0
5594 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5595
5596 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5597                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5598                 imit register.*/
5599 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL
5600 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
5601 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK
5602 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5603 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5604 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5605
5606 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5607                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5608                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5609                 not associated with any particular command).*/
5610 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL
5611 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
5612 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK
5613 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5614 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                                       13
5615 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5616
5617 /*If set to 1, enables aging function for the write channel of the port.*/
5618 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL
5619 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
5620 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK
5621 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5622 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                                        12
5623 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                                         0x00001000U
5624
5625 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5626                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5627                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5628                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5629                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5630                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5631                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5632                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5633 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL
5634 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
5635 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK
5636 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5637 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                                        0
5638 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5639
5640 /*Enables port n.*/
5641 #undef DDRC_PCTRL_1_PORT_EN_DEFVAL
5642 #undef DDRC_PCTRL_1_PORT_EN_SHIFT
5643 #undef DDRC_PCTRL_1_PORT_EN_MASK
5644 #define DDRC_PCTRL_1_PORT_EN_DEFVAL
5645 #define DDRC_PCTRL_1_PORT_EN_SHIFT                                                 0
5646 #define DDRC_PCTRL_1_PORT_EN_MASK                                                  0x00000001U
5647
5648 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5649                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5650                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5651 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL
5652 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
5653 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK
5654 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
5655 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                                     24
5656 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                                      0x03000000U
5657
5658 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5659                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5660                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5661 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL
5662 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
5663 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK
5664 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
5665 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                                     20
5666 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                                      0x00300000U
5667
5668 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5669                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5670                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5671 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL
5672 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
5673 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK
5674 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
5675 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                                     16
5676 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                                      0x00030000U
5677
5678 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5679                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5680                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5681                 ust be set to distinct values.*/
5682 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL
5683 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
5684 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK
5685 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
5686 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                                      8
5687 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
5688
5689 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5690                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5691                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5692                  values.*/
5693 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL
5694 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
5695 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK
5696 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
5697 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                                      0
5698 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5699
5700 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5701 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL
5702 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
5703 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK
5704 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5705 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5706 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5707
5708 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5709 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL
5710 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
5711 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK
5712 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5713 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5714 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5715
5716 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5717                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5718                 imit register.*/
5719 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL
5720 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
5721 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK
5722 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5723 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5724 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5725
5726 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5727                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5728                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5729                 ess handshaking (it is not associated with any particular command).*/
5730 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL
5731 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
5732 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK
5733 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5734 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                                       13
5735 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5736
5737 /*If set to 1, enables aging function for the read channel of the port.*/
5738 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL
5739 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
5740 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK
5741 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5742 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                                        12
5743 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                                         0x00001000U
5744
5745 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5746                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5747                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5748                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5749                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5750                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5751                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5752                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5753                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5754                 he two LSBs of this register field are tied internally to 2'b00.*/
5755 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL
5756 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
5757 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK
5758 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5759 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                                        0
5760 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5761
5762 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5763                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5764                 imit register.*/
5765 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL
5766 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
5767 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK
5768 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5769 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5770 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5771
5772 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5773                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5774                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5775                 not associated with any particular command).*/
5776 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL
5777 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
5778 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK
5779 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5780 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                                       13
5781 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5782
5783 /*If set to 1, enables aging function for the write channel of the port.*/
5784 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL
5785 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
5786 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK
5787 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5788 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                                        12
5789 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                                         0x00001000U
5790
5791 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5792                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5793                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5794                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5795                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5796                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5797                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5798                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5799 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL
5800 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
5801 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK
5802 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5803 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                                        0
5804 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5805
5806 /*Enables port n.*/
5807 #undef DDRC_PCTRL_2_PORT_EN_DEFVAL
5808 #undef DDRC_PCTRL_2_PORT_EN_SHIFT
5809 #undef DDRC_PCTRL_2_PORT_EN_MASK
5810 #define DDRC_PCTRL_2_PORT_EN_DEFVAL
5811 #define DDRC_PCTRL_2_PORT_EN_SHIFT                                                 0
5812 #define DDRC_PCTRL_2_PORT_EN_MASK                                                  0x00000001U
5813
5814 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5815                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5816                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5817 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL
5818 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
5819 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK
5820 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
5821 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                                     24
5822 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                                      0x03000000U
5823
5824 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5825                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5826                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5827 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL
5828 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
5829 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK
5830 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
5831 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                                     20
5832 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                                      0x00300000U
5833
5834 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5835                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5836                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5837 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL
5838 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
5839 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK
5840 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
5841 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                                     16
5842 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                                      0x00030000U
5843
5844 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5845                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5846                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5847                 ust be set to distinct values.*/
5848 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL
5849 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
5850 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK
5851 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
5852 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                                      8
5853 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
5854
5855 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5856                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5857                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5858                  values.*/
5859 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL
5860 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
5861 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK
5862 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
5863 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                                      0
5864 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
5865
5866 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5867 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL
5868 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
5869 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK
5870 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
5871 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                                    16
5872 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
5873
5874 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5875 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL
5876 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
5877 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK
5878 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
5879 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                                    0
5880 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
5881
5882 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5883                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5884                 imit register.*/
5885 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL
5886 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
5887 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK
5888 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
5889 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
5890 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5891
5892 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5893                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5894                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5895                 ess handshaking (it is not associated with any particular command).*/
5896 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL
5897 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
5898 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK
5899 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
5900 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                                       13
5901 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                                        0x00002000U
5902
5903 /*If set to 1, enables aging function for the read channel of the port.*/
5904 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL
5905 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
5906 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK
5907 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
5908 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                                        12
5909 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                                         0x00001000U
5910
5911 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5912                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5913                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5914                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5915                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5916                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5917                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5918                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5919                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5920                 he two LSBs of this register field are tied internally to 2'b00.*/
5921 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL
5922 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
5923 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK
5924 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
5925 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                                        0
5926 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                                         0x000003FFU
5927
5928 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5929                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5930                 imit register.*/
5931 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL
5932 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
5933 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK
5934 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
5935 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
5936 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
5937
5938 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5939                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5940                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5941                 not associated with any particular command).*/
5942 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL
5943 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
5944 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK
5945 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
5946 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                                       13
5947 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                                        0x00002000U
5948
5949 /*If set to 1, enables aging function for the write channel of the port.*/
5950 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL
5951 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
5952 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK
5953 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
5954 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                                        12
5955 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                                         0x00001000U
5956
5957 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5958                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5959                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5960                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5961                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5962                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5963                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5964                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5965 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL
5966 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
5967 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK
5968 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
5969 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                                        0
5970 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                                         0x000003FFU
5971
5972 /*Enables port n.*/
5973 #undef DDRC_PCTRL_3_PORT_EN_DEFVAL
5974 #undef DDRC_PCTRL_3_PORT_EN_SHIFT
5975 #undef DDRC_PCTRL_3_PORT_EN_MASK
5976 #define DDRC_PCTRL_3_PORT_EN_DEFVAL
5977 #define DDRC_PCTRL_3_PORT_EN_SHIFT                                                 0
5978 #define DDRC_PCTRL_3_PORT_EN_MASK                                                  0x00000001U
5979
5980 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5981                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5982                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5983 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL
5984 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
5985 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK
5986 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
5987 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                                     20
5988 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                                      0x00300000U
5989
5990 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5991                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5992                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5993 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL
5994 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
5995 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK
5996 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
5997 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                                     16
5998 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                                      0x00030000U
5999
6000 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
6001                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
6002                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
6003                  values.*/
6004 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL
6005 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
6006 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK
6007 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
6008 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                                      0
6009 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
6010
6011 /*Specifies the timeout value for transactions mapped to the red address queue.*/
6012 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL
6013 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
6014 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK
6015 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
6016 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                                    16
6017 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
6018
6019 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
6020 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL
6021 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
6022 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK
6023 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
6024 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                                    0
6025 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
6026
6027 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6028                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
6029 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL
6030 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
6031 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK
6032 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
6033 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                                    20
6034 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                                     0x00300000U
6035
6036 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6037                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
6038 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL
6039 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
6040 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK
6041 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
6042 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                                    16
6043 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                                     0x00030000U
6044
6045 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
6046                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
6047                 s to higher port priority.*/
6048 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL
6049 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
6050 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK
6051 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
6052 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                                      0
6053 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
6054
6055 /*Specifies the timeout value for write transactions.*/
6056 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
6057 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
6058 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK
6059 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
6060 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                                    0
6061 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
6062
6063 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
6064                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
6065                 imit register.*/
6066 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL
6067 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
6068 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK
6069 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
6070 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
6071 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
6072
6073 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
6074                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
6075                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
6076                 ess handshaking (it is not associated with any particular command).*/
6077 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL
6078 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
6079 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK
6080 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
6081 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                                       13
6082 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                                        0x00002000U
6083
6084 /*If set to 1, enables aging function for the read channel of the port.*/
6085 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL
6086 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
6087 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK
6088 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
6089 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                                        12
6090 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                                         0x00001000U
6091
6092 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
6093                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
6094                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
6095                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
6096                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
6097                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
6098                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
6099                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
6100                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
6101                 he two LSBs of this register field are tied internally to 2'b00.*/
6102 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL
6103 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
6104 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK
6105 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
6106 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                                        0
6107 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                                         0x000003FFU
6108
6109 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
6110                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
6111                 imit register.*/
6112 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL
6113 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
6114 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK
6115 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
6116 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
6117 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
6118
6119 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
6120                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
6121                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
6122                 not associated with any particular command).*/
6123 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL
6124 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
6125 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK
6126 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
6127 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                                       13
6128 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                                        0x00002000U
6129
6130 /*If set to 1, enables aging function for the write channel of the port.*/
6131 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL
6132 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
6133 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK
6134 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
6135 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                                        12
6136 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                                         0x00001000U
6137
6138 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
6139                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
6140                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
6141                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
6142                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
6143                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
6144                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
6145                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
6146 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL
6147 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
6148 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK
6149 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
6150 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                                        0
6151 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                                         0x000003FFU
6152
6153 /*Enables port n.*/
6154 #undef DDRC_PCTRL_4_PORT_EN_DEFVAL
6155 #undef DDRC_PCTRL_4_PORT_EN_SHIFT
6156 #undef DDRC_PCTRL_4_PORT_EN_MASK
6157 #define DDRC_PCTRL_4_PORT_EN_DEFVAL
6158 #define DDRC_PCTRL_4_PORT_EN_SHIFT                                                 0
6159 #define DDRC_PCTRL_4_PORT_EN_MASK                                                  0x00000001U
6160
6161 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
6162                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
6163                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
6164 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL
6165 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
6166 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK
6167 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
6168 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                                     20
6169 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                                      0x00300000U
6170
6171 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
6172                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
6173                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
6174 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL
6175 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
6176 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK
6177 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
6178 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                                     16
6179 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                                      0x00030000U
6180
6181 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
6182                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
6183                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
6184                  values.*/
6185 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL
6186 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
6187 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK
6188 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
6189 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                                      0
6190 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
6191
6192 /*Specifies the timeout value for transactions mapped to the red address queue.*/
6193 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL
6194 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
6195 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK
6196 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
6197 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                                    16
6198 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
6199
6200 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
6201 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL
6202 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
6203 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK
6204 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
6205 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                                    0
6206 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
6207
6208 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6209                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
6210 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL
6211 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
6212 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK
6213 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
6214 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                                    20
6215 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                                     0x00300000U
6216
6217 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6218                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
6219 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL
6220 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
6221 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK
6222 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
6223 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                                    16
6224 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                                     0x00030000U
6225
6226 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
6227                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
6228                 s to higher port priority.*/
6229 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL
6230 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
6231 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK
6232 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
6233 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                                      0
6234 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
6235
6236 /*Specifies the timeout value for write transactions.*/
6237 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
6238 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
6239 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK
6240 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
6241 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                                    0
6242 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
6243
6244 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
6245                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
6246                 imit register.*/
6247 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL
6248 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
6249 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK
6250 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
6251 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
6252 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
6253
6254 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
6255                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
6256                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
6257                 ess handshaking (it is not associated with any particular command).*/
6258 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL
6259 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
6260 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK
6261 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
6262 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                                       13
6263 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                                        0x00002000U
6264
6265 /*If set to 1, enables aging function for the read channel of the port.*/
6266 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL
6267 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
6268 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK
6269 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
6270 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                                        12
6271 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                                         0x00001000U
6272
6273 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
6274                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
6275                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
6276                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
6277                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
6278                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
6279                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
6280                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
6281                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
6282                 he two LSBs of this register field are tied internally to 2'b00.*/
6283 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL
6284 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
6285 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK
6286 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
6287 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                                        0
6288 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                                         0x000003FFU
6289
6290 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
6291                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
6292                 imit register.*/
6293 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL
6294 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
6295 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK
6296 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
6297 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
6298 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
6299
6300 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
6301                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
6302                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
6303                 not associated with any particular command).*/
6304 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL
6305 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
6306 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK
6307 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
6308 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                                       13
6309 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                                        0x00002000U
6310
6311 /*If set to 1, enables aging function for the write channel of the port.*/
6312 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL
6313 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
6314 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK
6315 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
6316 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                                        12
6317 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                                         0x00001000U
6318
6319 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
6320                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
6321                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
6322                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
6323                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
6324                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
6325                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
6326                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
6327 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL
6328 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
6329 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK
6330 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
6331 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                                        0
6332 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                                         0x000003FFU
6333
6334 /*Enables port n.*/
6335 #undef DDRC_PCTRL_5_PORT_EN_DEFVAL
6336 #undef DDRC_PCTRL_5_PORT_EN_SHIFT
6337 #undef DDRC_PCTRL_5_PORT_EN_MASK
6338 #define DDRC_PCTRL_5_PORT_EN_DEFVAL
6339 #define DDRC_PCTRL_5_PORT_EN_SHIFT                                                 0
6340 #define DDRC_PCTRL_5_PORT_EN_MASK                                                  0x00000001U
6341
6342 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
6343                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
6344                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
6345 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL
6346 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
6347 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK
6348 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
6349 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                                     20
6350 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                                      0x00300000U
6351
6352 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
6353                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
6354                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
6355 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL
6356 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
6357 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK
6358 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
6359 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                                     16
6360 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                                      0x00030000U
6361
6362 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
6363                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
6364                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
6365                  values.*/
6366 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL
6367 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
6368 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK
6369 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
6370 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                                      0
6371 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
6372
6373 /*Specifies the timeout value for transactions mapped to the red address queue.*/
6374 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL
6375 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
6376 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK
6377 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
6378 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                                    16
6379 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
6380
6381 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
6382 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL
6383 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
6384 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK
6385 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
6386 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                                    0
6387 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
6388
6389 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6390                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
6391 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL
6392 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
6393 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK
6394 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
6395 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                                    20
6396 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                                     0x00300000U
6397
6398 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
6399                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
6400 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL
6401 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
6402 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK
6403 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
6404 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                                    16
6405 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                                     0x00030000U
6406
6407 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
6408                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
6409                 s to higher port priority.*/
6410 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL
6411 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
6412 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK
6413 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
6414 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                                      0
6415 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
6416
6417 /*Specifies the timeout value for write transactions.*/
6418 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
6419 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
6420 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK
6421 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
6422 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                                    0
6423 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
6424
6425 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
6426                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
6427 #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL
6428 #undef DDRC_SARBASE0_BASE_ADDR_SHIFT
6429 #undef DDRC_SARBASE0_BASE_ADDR_MASK
6430 #define DDRC_SARBASE0_BASE_ADDR_DEFVAL
6431 #define DDRC_SARBASE0_BASE_ADDR_SHIFT                                              0
6432 #define DDRC_SARBASE0_BASE_ADDR_MASK                                               0x000001FFU
6433
6434 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
6435                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
6436                 or example, if register is programmed to 0, region will have 1 block.*/
6437 #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL
6438 #undef DDRC_SARSIZE0_NBLOCKS_SHIFT
6439 #undef DDRC_SARSIZE0_NBLOCKS_MASK
6440 #define DDRC_SARSIZE0_NBLOCKS_DEFVAL
6441 #define DDRC_SARSIZE0_NBLOCKS_SHIFT                                                0
6442 #define DDRC_SARSIZE0_NBLOCKS_MASK                                                 0x000000FFU
6443
6444 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
6445                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
6446 #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL
6447 #undef DDRC_SARBASE1_BASE_ADDR_SHIFT
6448 #undef DDRC_SARBASE1_BASE_ADDR_MASK
6449 #define DDRC_SARBASE1_BASE_ADDR_DEFVAL
6450 #define DDRC_SARBASE1_BASE_ADDR_SHIFT                                              0
6451 #define DDRC_SARBASE1_BASE_ADDR_MASK                                               0x000001FFU
6452
6453 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
6454                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
6455                 or example, if register is programmed to 0, region will have 1 block.*/
6456 #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL
6457 #undef DDRC_SARSIZE1_NBLOCKS_SHIFT
6458 #undef DDRC_SARSIZE1_NBLOCKS_MASK
6459 #define DDRC_SARSIZE1_NBLOCKS_DEFVAL
6460 #define DDRC_SARSIZE1_NBLOCKS_SHIFT                                                0
6461 #define DDRC_SARSIZE1_NBLOCKS_MASK                                                 0x000000FFU
6462
6463 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
6464                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
6465                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
6466                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
6467 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL
6468 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
6469 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK
6470 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL                                0x07020002
6471 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT                                 24
6472 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK                                  0x1F000000U
6473
6474 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
6475                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
6476                 fer to PHY specification for correct value.*/
6477 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL
6478 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
6479 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK
6480 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL                              0x07020002
6481 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT                               23
6482 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK                                0x00800000U
6483
6484 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
6485                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
6486                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
6487                  latency through the RDIMM. Unit: Clocks*/
6488 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL
6489 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
6490 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK
6491 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL                                 0x07020002
6492 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT                                  16
6493 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK                                   0x003F0000U
6494
6495 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
6496                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
6497                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
6498                 e.*/
6499 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL
6500 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
6501 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK
6502 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL                              0x07020002
6503 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT                               15
6504 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK                                0x00008000U
6505
6506 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
6507                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
6508                 te, max supported value is 8. Unit: Clocks*/
6509 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL
6510 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
6511 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK
6512 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL                                 0x07020002
6513 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT                                  8
6514 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK                                   0x00003F00U
6515
6516 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
6517                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
6518                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
6519                 rough the RDIMM.*/
6520 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL
6521 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
6522 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK
6523 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL                                  0x07020002
6524 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT                                   0
6525 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                                    0x0000003FU
6526
6527 /*DDR block level reset inside of the DDR Sub System*/
6528 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
6529 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
6530 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
6531 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
6532 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
6533 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
6534
6535 /*Address Copy*/
6536 #undef DDR_PHY_PGCR0_ADCP_DEFVAL
6537 #undef DDR_PHY_PGCR0_ADCP_SHIFT
6538 #undef DDR_PHY_PGCR0_ADCP_MASK
6539 #define DDR_PHY_PGCR0_ADCP_DEFVAL                                                  0x07001E00
6540 #define DDR_PHY_PGCR0_ADCP_SHIFT                                                   31
6541 #define DDR_PHY_PGCR0_ADCP_MASK                                                    0x80000000U
6542
6543 /*Reserved. Returns zeroes on reads.*/
6544 #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL
6545 #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
6546 #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK
6547 #define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                                        0x07001E00
6548 #define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                                         27
6549 #define DDR_PHY_PGCR0_RESERVED_30_27_MASK                                          0x78000000U
6550
6551 /*PHY FIFO Reset*/
6552 #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL
6553 #undef DDR_PHY_PGCR0_PHYFRST_SHIFT
6554 #undef DDR_PHY_PGCR0_PHYFRST_MASK
6555 #define DDR_PHY_PGCR0_PHYFRST_DEFVAL                                               0x07001E00
6556 #define DDR_PHY_PGCR0_PHYFRST_SHIFT                                                26
6557 #define DDR_PHY_PGCR0_PHYFRST_MASK                                                 0x04000000U
6558
6559 /*Oscillator Mode Address/Command Delay Line Select*/
6560 #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL
6561 #undef DDR_PHY_PGCR0_OSCACDL_SHIFT
6562 #undef DDR_PHY_PGCR0_OSCACDL_MASK
6563 #define DDR_PHY_PGCR0_OSCACDL_DEFVAL                                               0x07001E00
6564 #define DDR_PHY_PGCR0_OSCACDL_SHIFT                                                24
6565 #define DDR_PHY_PGCR0_OSCACDL_MASK                                                 0x03000000U
6566
6567 /*Reserved. Returns zeroes on reads.*/
6568 #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL
6569 #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
6570 #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK
6571 #define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                                        0x07001E00
6572 #define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                                         19
6573 #define DDR_PHY_PGCR0_RESERVED_23_19_MASK                                          0x00F80000U
6574
6575 /*Digital Test Output Select*/
6576 #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL
6577 #undef DDR_PHY_PGCR0_DTOSEL_SHIFT
6578 #undef DDR_PHY_PGCR0_DTOSEL_MASK
6579 #define DDR_PHY_PGCR0_DTOSEL_DEFVAL                                                0x07001E00
6580 #define DDR_PHY_PGCR0_DTOSEL_SHIFT                                                 14
6581 #define DDR_PHY_PGCR0_DTOSEL_MASK                                                  0x0007C000U
6582
6583 /*Reserved. Returns zeroes on reads.*/
6584 #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL
6585 #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT
6586 #undef DDR_PHY_PGCR0_RESERVED_13_MASK
6587 #define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                                           0x07001E00
6588 #define DDR_PHY_PGCR0_RESERVED_13_SHIFT                                            13
6589 #define DDR_PHY_PGCR0_RESERVED_13_MASK                                             0x00002000U
6590
6591 /*Oscillator Mode Division*/
6592 #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL
6593 #undef DDR_PHY_PGCR0_OSCDIV_SHIFT
6594 #undef DDR_PHY_PGCR0_OSCDIV_MASK
6595 #define DDR_PHY_PGCR0_OSCDIV_DEFVAL                                                0x07001E00
6596 #define DDR_PHY_PGCR0_OSCDIV_SHIFT                                                 9
6597 #define DDR_PHY_PGCR0_OSCDIV_MASK                                                  0x00001E00U
6598
6599 /*Oscillator Enable*/
6600 #undef DDR_PHY_PGCR0_OSCEN_DEFVAL
6601 #undef DDR_PHY_PGCR0_OSCEN_SHIFT
6602 #undef DDR_PHY_PGCR0_OSCEN_MASK
6603 #define DDR_PHY_PGCR0_OSCEN_DEFVAL                                                 0x07001E00
6604 #define DDR_PHY_PGCR0_OSCEN_SHIFT                                                  8
6605 #define DDR_PHY_PGCR0_OSCEN_MASK                                                   0x00000100U
6606
6607 /*Reserved. Returns zeroes on reads.*/
6608 #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL
6609 #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
6610 #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK
6611 #define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                                          0x07001E00
6612 #define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                                           0
6613 #define DDR_PHY_PGCR0_RESERVED_7_0_MASK                                            0x000000FFU
6614
6615 /*Clear Training Status Registers*/
6616 #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL
6617 #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT
6618 #undef DDR_PHY_PGCR2_CLRTSTAT_MASK
6619 #define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                                              0x00F12480
6620 #define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                                               31
6621 #define DDR_PHY_PGCR2_CLRTSTAT_MASK                                                0x80000000U
6622
6623 /*Clear Impedance Calibration*/
6624 #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL
6625 #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT
6626 #undef DDR_PHY_PGCR2_CLRZCAL_MASK
6627 #define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                                               0x00F12480
6628 #define DDR_PHY_PGCR2_CLRZCAL_SHIFT                                                30
6629 #define DDR_PHY_PGCR2_CLRZCAL_MASK                                                 0x40000000U
6630
6631 /*Clear Parity Error*/
6632 #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL
6633 #undef DDR_PHY_PGCR2_CLRPERR_SHIFT
6634 #undef DDR_PHY_PGCR2_CLRPERR_MASK
6635 #define DDR_PHY_PGCR2_CLRPERR_DEFVAL                                               0x00F12480
6636 #define DDR_PHY_PGCR2_CLRPERR_SHIFT                                                29
6637 #define DDR_PHY_PGCR2_CLRPERR_MASK                                                 0x20000000U
6638
6639 /*Initialization Complete Pin Configuration*/
6640 #undef DDR_PHY_PGCR2_ICPC_DEFVAL
6641 #undef DDR_PHY_PGCR2_ICPC_SHIFT
6642 #undef DDR_PHY_PGCR2_ICPC_MASK
6643 #define DDR_PHY_PGCR2_ICPC_DEFVAL                                                  0x00F12480
6644 #define DDR_PHY_PGCR2_ICPC_SHIFT                                                   28
6645 #define DDR_PHY_PGCR2_ICPC_MASK                                                    0x10000000U
6646
6647 /*Data Training PUB Mode Exit Timer*/
6648 #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL
6649 #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT
6650 #undef DDR_PHY_PGCR2_DTPMXTMR_MASK
6651 #define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                                              0x00F12480
6652 #define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                                               20
6653 #define DDR_PHY_PGCR2_DTPMXTMR_MASK                                                0x0FF00000U
6654
6655 /*Initialization Bypass*/
6656 #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL
6657 #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT
6658 #undef DDR_PHY_PGCR2_INITFSMBYP_MASK
6659 #define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                                            0x00F12480
6660 #define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                                             19
6661 #define DDR_PHY_PGCR2_INITFSMBYP_MASK                                              0x00080000U
6662
6663 /*PLL FSM Bypass*/
6664 #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL
6665 #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
6666 #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK
6667 #define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                                             0x00F12480
6668 #define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                                              18
6669 #define DDR_PHY_PGCR2_PLLFSMBYP_MASK                                               0x00040000U
6670
6671 /*Refresh Period*/
6672 #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL
6673 #undef DDR_PHY_PGCR2_TREFPRD_SHIFT
6674 #undef DDR_PHY_PGCR2_TREFPRD_MASK
6675 #define DDR_PHY_PGCR2_TREFPRD_DEFVAL                                               0x00F12480
6676 #define DDR_PHY_PGCR2_TREFPRD_SHIFT                                                0
6677 #define DDR_PHY_PGCR2_TREFPRD_MASK                                                 0x0003FFFFU
6678
6679 /*Frequency B Ratio Term*/
6680 #undef DDR_PHY_PGCR5_FRQBT_DEFVAL
6681 #undef DDR_PHY_PGCR5_FRQBT_SHIFT
6682 #undef DDR_PHY_PGCR5_FRQBT_MASK
6683 #define DDR_PHY_PGCR5_FRQBT_DEFVAL                                                 0x01010000
6684 #define DDR_PHY_PGCR5_FRQBT_SHIFT                                                  24
6685 #define DDR_PHY_PGCR5_FRQBT_MASK                                                   0xFF000000U
6686
6687 /*Frequency A Ratio Term*/
6688 #undef DDR_PHY_PGCR5_FRQAT_DEFVAL
6689 #undef DDR_PHY_PGCR5_FRQAT_SHIFT
6690 #undef DDR_PHY_PGCR5_FRQAT_MASK
6691 #define DDR_PHY_PGCR5_FRQAT_DEFVAL                                                 0x01010000
6692 #define DDR_PHY_PGCR5_FRQAT_SHIFT                                                  16
6693 #define DDR_PHY_PGCR5_FRQAT_MASK                                                   0x00FF0000U
6694
6695 /*DFI Disconnect Time Period*/
6696 #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL
6697 #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
6698 #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK
6699 #define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                                           0x01010000
6700 #define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                                            8
6701 #define DDR_PHY_PGCR5_DISCNPERIOD_MASK                                             0x0000FF00U
6702
6703 /*Receiver bias core side control*/
6704 #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL
6705 #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
6706 #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK
6707 #define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                                           0x01010000
6708 #define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                                            4
6709 #define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                                             0x000000F0U
6710
6711 /*Reserved. Return zeroes on reads.*/
6712 #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL
6713 #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT
6714 #undef DDR_PHY_PGCR5_RESERVED_3_MASK
6715 #define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                                            0x01010000
6716 #define DDR_PHY_PGCR5_RESERVED_3_SHIFT                                             3
6717 #define DDR_PHY_PGCR5_RESERVED_3_MASK                                              0x00000008U
6718
6719 /*Internal VREF generator REFSEL ragne select*/
6720 #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL
6721 #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
6722 #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK
6723 #define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                                        0x01010000
6724 #define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                                         2
6725 #define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                                          0x00000004U
6726
6727 /*DDL Page Read Write select*/
6728 #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL
6729 #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT
6730 #undef DDR_PHY_PGCR5_DDLPGACT_MASK
6731 #define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                                              0x01010000
6732 #define DDR_PHY_PGCR5_DDLPGACT_SHIFT                                               1
6733 #define DDR_PHY_PGCR5_DDLPGACT_MASK                                                0x00000002U
6734
6735 /*DDL Page Read Write select*/
6736 #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL
6737 #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT
6738 #undef DDR_PHY_PGCR5_DDLPGRW_MASK
6739 #define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                                               0x01010000
6740 #define DDR_PHY_PGCR5_DDLPGRW_SHIFT                                                0
6741 #define DDR_PHY_PGCR5_DDLPGRW_MASK                                                 0x00000001U
6742
6743 /*PLL Power-Down Time*/
6744 #undef DDR_PHY_PTR0_TPLLPD_DEFVAL
6745 #undef DDR_PHY_PTR0_TPLLPD_SHIFT
6746 #undef DDR_PHY_PTR0_TPLLPD_MASK
6747 #define DDR_PHY_PTR0_TPLLPD_DEFVAL                                                 0x42C21590
6748 #define DDR_PHY_PTR0_TPLLPD_SHIFT                                                  21
6749 #define DDR_PHY_PTR0_TPLLPD_MASK                                                   0xFFE00000U
6750
6751 /*PLL Gear Shift Time*/
6752 #undef DDR_PHY_PTR0_TPLLGS_DEFVAL
6753 #undef DDR_PHY_PTR0_TPLLGS_SHIFT
6754 #undef DDR_PHY_PTR0_TPLLGS_MASK
6755 #define DDR_PHY_PTR0_TPLLGS_DEFVAL                                                 0x42C21590
6756 #define DDR_PHY_PTR0_TPLLGS_SHIFT                                                  6
6757 #define DDR_PHY_PTR0_TPLLGS_MASK                                                   0x001FFFC0U
6758
6759 /*PHY Reset Time*/
6760 #undef DDR_PHY_PTR0_TPHYRST_DEFVAL
6761 #undef DDR_PHY_PTR0_TPHYRST_SHIFT
6762 #undef DDR_PHY_PTR0_TPHYRST_MASK
6763 #define DDR_PHY_PTR0_TPHYRST_DEFVAL                                                0x42C21590
6764 #define DDR_PHY_PTR0_TPHYRST_SHIFT                                                 0
6765 #define DDR_PHY_PTR0_TPHYRST_MASK                                                  0x0000003FU
6766
6767 /*PLL Lock Time*/
6768 #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL
6769 #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT
6770 #undef DDR_PHY_PTR1_TPLLLOCK_MASK
6771 #define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                                               0xD05612C0
6772 #define DDR_PHY_PTR1_TPLLLOCK_SHIFT                                                16
6773 #define DDR_PHY_PTR1_TPLLLOCK_MASK                                                 0xFFFF0000U
6774
6775 /*Reserved. Returns zeroes on reads.*/
6776 #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL
6777 #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT
6778 #undef DDR_PHY_PTR1_RESERVED_15_13_MASK
6779 #define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                                         0xD05612C0
6780 #define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                                          13
6781 #define DDR_PHY_PTR1_RESERVED_15_13_MASK                                           0x0000E000U
6782
6783 /*PLL Reset Time*/
6784 #undef DDR_PHY_PTR1_TPLLRST_DEFVAL
6785 #undef DDR_PHY_PTR1_TPLLRST_SHIFT
6786 #undef DDR_PHY_PTR1_TPLLRST_MASK
6787 #define DDR_PHY_PTR1_TPLLRST_DEFVAL                                                0xD05612C0
6788 #define DDR_PHY_PTR1_TPLLRST_SHIFT                                                 0
6789 #define DDR_PHY_PTR1_TPLLRST_MASK                                                  0x00001FFFU
6790
6791 /*Reserved. Return zeroes on reads.*/
6792 #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL
6793 #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
6794 #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK
6795 #define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                                        0x02A04101
6796 #define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                                         28
6797 #define DDR_PHY_DSGCR_RESERVED_31_28_MASK                                          0xF0000000U
6798
6799 /*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
6800                 fault calculation.*/
6801 #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL
6802 #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT
6803 #undef DDR_PHY_DSGCR_RDBICLSEL_MASK
6804 #define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                                             0x02A04101
6805 #define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                                              27
6806 #define DDR_PHY_DSGCR_RDBICLSEL_MASK                                               0x08000000U
6807
6808 /*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/
6809 #undef DDR_PHY_DSGCR_RDBICL_DEFVAL
6810 #undef DDR_PHY_DSGCR_RDBICL_SHIFT
6811 #undef DDR_PHY_DSGCR_RDBICL_MASK
6812 #define DDR_PHY_DSGCR_RDBICL_DEFVAL                                                0x02A04101
6813 #define DDR_PHY_DSGCR_RDBICL_SHIFT                                                 24
6814 #define DDR_PHY_DSGCR_RDBICL_MASK                                                  0x07000000U
6815
6816 /*PHY Impedance Update Enable*/
6817 #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL
6818 #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT
6819 #undef DDR_PHY_DSGCR_PHYZUEN_MASK
6820 #define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                                               0x02A04101
6821 #define DDR_PHY_DSGCR_PHYZUEN_SHIFT                                                23
6822 #define DDR_PHY_DSGCR_PHYZUEN_MASK                                                 0x00800000U
6823
6824 /*Reserved. Return zeroes on reads.*/
6825 #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL
6826 #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT
6827 #undef DDR_PHY_DSGCR_RESERVED_22_MASK
6828 #define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                                           0x02A04101
6829 #define DDR_PHY_DSGCR_RESERVED_22_SHIFT                                            22
6830 #define DDR_PHY_DSGCR_RESERVED_22_MASK                                             0x00400000U
6831
6832 /*SDRAM Reset Output Enable*/
6833 #undef DDR_PHY_DSGCR_RSTOE_DEFVAL
6834 #undef DDR_PHY_DSGCR_RSTOE_SHIFT
6835 #undef DDR_PHY_DSGCR_RSTOE_MASK
6836 #define DDR_PHY_DSGCR_RSTOE_DEFVAL                                                 0x02A04101
6837 #define DDR_PHY_DSGCR_RSTOE_SHIFT                                                  21
6838 #define DDR_PHY_DSGCR_RSTOE_MASK                                                   0x00200000U
6839
6840 /*Single Data Rate Mode*/
6841 #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL
6842 #undef DDR_PHY_DSGCR_SDRMODE_SHIFT
6843 #undef DDR_PHY_DSGCR_SDRMODE_MASK
6844 #define DDR_PHY_DSGCR_SDRMODE_DEFVAL                                               0x02A04101
6845 #define DDR_PHY_DSGCR_SDRMODE_SHIFT                                                19
6846 #define DDR_PHY_DSGCR_SDRMODE_MASK                                                 0x00180000U
6847
6848 /*Reserved. Return zeroes on reads.*/
6849 #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL
6850 #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT
6851 #undef DDR_PHY_DSGCR_RESERVED_18_MASK
6852 #define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                                           0x02A04101
6853 #define DDR_PHY_DSGCR_RESERVED_18_SHIFT                                            18
6854 #define DDR_PHY_DSGCR_RESERVED_18_MASK                                             0x00040000U
6855
6856 /*ATO Analog Test Enable*/
6857 #undef DDR_PHY_DSGCR_ATOAE_DEFVAL
6858 #undef DDR_PHY_DSGCR_ATOAE_SHIFT
6859 #undef DDR_PHY_DSGCR_ATOAE_MASK
6860 #define DDR_PHY_DSGCR_ATOAE_DEFVAL                                                 0x02A04101
6861 #define DDR_PHY_DSGCR_ATOAE_SHIFT                                                  17
6862 #define DDR_PHY_DSGCR_ATOAE_MASK                                                   0x00020000U
6863
6864 /*DTO Output Enable*/
6865 #undef DDR_PHY_DSGCR_DTOOE_DEFVAL
6866 #undef DDR_PHY_DSGCR_DTOOE_SHIFT
6867 #undef DDR_PHY_DSGCR_DTOOE_MASK
6868 #define DDR_PHY_DSGCR_DTOOE_DEFVAL                                                 0x02A04101
6869 #define DDR_PHY_DSGCR_DTOOE_SHIFT                                                  16
6870 #define DDR_PHY_DSGCR_DTOOE_MASK                                                   0x00010000U
6871
6872 /*DTO I/O Mode*/
6873 #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL
6874 #undef DDR_PHY_DSGCR_DTOIOM_SHIFT
6875 #undef DDR_PHY_DSGCR_DTOIOM_MASK
6876 #define DDR_PHY_DSGCR_DTOIOM_DEFVAL                                                0x02A04101
6877 #define DDR_PHY_DSGCR_DTOIOM_SHIFT                                                 15
6878 #define DDR_PHY_DSGCR_DTOIOM_MASK                                                  0x00008000U
6879
6880 /*DTO Power Down Receiver*/
6881 #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL
6882 #undef DDR_PHY_DSGCR_DTOPDR_SHIFT
6883 #undef DDR_PHY_DSGCR_DTOPDR_MASK
6884 #define DDR_PHY_DSGCR_DTOPDR_DEFVAL                                                0x02A04101
6885 #define DDR_PHY_DSGCR_DTOPDR_SHIFT                                                 14
6886 #define DDR_PHY_DSGCR_DTOPDR_MASK                                                  0x00004000U
6887
6888 /*Reserved. Return zeroes on reads*/
6889 #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL
6890 #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT
6891 #undef DDR_PHY_DSGCR_RESERVED_13_MASK
6892 #define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                                           0x02A04101
6893 #define DDR_PHY_DSGCR_RESERVED_13_SHIFT                                            13
6894 #define DDR_PHY_DSGCR_RESERVED_13_MASK                                             0x00002000U
6895
6896 /*DTO On-Die Termination*/
6897 #undef DDR_PHY_DSGCR_DTOODT_DEFVAL
6898 #undef DDR_PHY_DSGCR_DTOODT_SHIFT
6899 #undef DDR_PHY_DSGCR_DTOODT_MASK
6900 #define DDR_PHY_DSGCR_DTOODT_DEFVAL                                                0x02A04101
6901 #define DDR_PHY_DSGCR_DTOODT_SHIFT                                                 12
6902 #define DDR_PHY_DSGCR_DTOODT_MASK                                                  0x00001000U
6903
6904 /*PHY Update Acknowledge Delay*/
6905 #undef DDR_PHY_DSGCR_PUAD_DEFVAL
6906 #undef DDR_PHY_DSGCR_PUAD_SHIFT
6907 #undef DDR_PHY_DSGCR_PUAD_MASK
6908 #define DDR_PHY_DSGCR_PUAD_DEFVAL                                                  0x02A04101
6909 #define DDR_PHY_DSGCR_PUAD_SHIFT                                                   6
6910 #define DDR_PHY_DSGCR_PUAD_MASK                                                    0x00000FC0U
6911
6912 /*Controller Update Acknowledge Enable*/
6913 #undef DDR_PHY_DSGCR_CUAEN_DEFVAL
6914 #undef DDR_PHY_DSGCR_CUAEN_SHIFT
6915 #undef DDR_PHY_DSGCR_CUAEN_MASK
6916 #define DDR_PHY_DSGCR_CUAEN_DEFVAL                                                 0x02A04101
6917 #define DDR_PHY_DSGCR_CUAEN_SHIFT                                                  5
6918 #define DDR_PHY_DSGCR_CUAEN_MASK                                                   0x00000020U
6919
6920 /*Reserved. Return zeroes on reads*/
6921 #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL
6922 #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
6923 #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK
6924 #define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                                          0x02A04101
6925 #define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                                           3
6926 #define DDR_PHY_DSGCR_RESERVED_4_3_MASK                                            0x00000018U
6927
6928 /*Controller Impedance Update Enable*/
6929 #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL
6930 #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT
6931 #undef DDR_PHY_DSGCR_CTLZUEN_MASK
6932 #define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                                               0x02A04101
6933 #define DDR_PHY_DSGCR_CTLZUEN_SHIFT                                                2
6934 #define DDR_PHY_DSGCR_CTLZUEN_MASK                                                 0x00000004U
6935
6936 /*Reserved. Return zeroes on reads*/
6937 #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL
6938 #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT
6939 #undef DDR_PHY_DSGCR_RESERVED_1_MASK
6940 #define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                                            0x02A04101
6941 #define DDR_PHY_DSGCR_RESERVED_1_SHIFT                                             1
6942 #define DDR_PHY_DSGCR_RESERVED_1_MASK                                              0x00000002U
6943
6944 /*PHY Update Request Enable*/
6945 #undef DDR_PHY_DSGCR_PUREN_DEFVAL
6946 #undef DDR_PHY_DSGCR_PUREN_SHIFT
6947 #undef DDR_PHY_DSGCR_PUREN_MASK
6948 #define DDR_PHY_DSGCR_PUREN_DEFVAL                                                 0x02A04101
6949 #define DDR_PHY_DSGCR_PUREN_SHIFT                                                  0
6950 #define DDR_PHY_DSGCR_PUREN_MASK                                                   0x00000001U
6951
6952 /*DDR4 Gear Down Timing.*/
6953 #undef DDR_PHY_DCR_GEARDN_DEFVAL
6954 #undef DDR_PHY_DCR_GEARDN_SHIFT
6955 #undef DDR_PHY_DCR_GEARDN_MASK
6956 #define DDR_PHY_DCR_GEARDN_DEFVAL                                                  0x0000040D
6957 #define DDR_PHY_DCR_GEARDN_SHIFT                                                   31
6958 #define DDR_PHY_DCR_GEARDN_MASK                                                    0x80000000U
6959
6960 /*Un-used Bank Group*/
6961 #undef DDR_PHY_DCR_UBG_DEFVAL
6962 #undef DDR_PHY_DCR_UBG_SHIFT
6963 #undef DDR_PHY_DCR_UBG_MASK
6964 #define DDR_PHY_DCR_UBG_DEFVAL                                                     0x0000040D
6965 #define DDR_PHY_DCR_UBG_SHIFT                                                      30
6966 #define DDR_PHY_DCR_UBG_MASK                                                       0x40000000U
6967
6968 /*Un-buffered DIMM Address Mirroring*/
6969 #undef DDR_PHY_DCR_UDIMM_DEFVAL
6970 #undef DDR_PHY_DCR_UDIMM_SHIFT
6971 #undef DDR_PHY_DCR_UDIMM_MASK
6972 #define DDR_PHY_DCR_UDIMM_DEFVAL                                                   0x0000040D
6973 #define DDR_PHY_DCR_UDIMM_SHIFT                                                    29
6974 #define DDR_PHY_DCR_UDIMM_MASK                                                     0x20000000U
6975
6976 /*DDR 2T Timing*/
6977 #undef DDR_PHY_DCR_DDR2T_DEFVAL
6978 #undef DDR_PHY_DCR_DDR2T_SHIFT
6979 #undef DDR_PHY_DCR_DDR2T_MASK
6980 #define DDR_PHY_DCR_DDR2T_DEFVAL                                                   0x0000040D
6981 #define DDR_PHY_DCR_DDR2T_SHIFT                                                    28
6982 #define DDR_PHY_DCR_DDR2T_MASK                                                     0x10000000U
6983
6984 /*No Simultaneous Rank Access*/
6985 #undef DDR_PHY_DCR_NOSRA_DEFVAL
6986 #undef DDR_PHY_DCR_NOSRA_SHIFT
6987 #undef DDR_PHY_DCR_NOSRA_MASK
6988 #define DDR_PHY_DCR_NOSRA_DEFVAL                                                   0x0000040D
6989 #define DDR_PHY_DCR_NOSRA_SHIFT                                                    27
6990 #define DDR_PHY_DCR_NOSRA_MASK                                                     0x08000000U
6991
6992 /*Reserved. Return zeroes on reads.*/
6993 #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL
6994 #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT
6995 #undef DDR_PHY_DCR_RESERVED_26_18_MASK
6996 #define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                                          0x0000040D
6997 #define DDR_PHY_DCR_RESERVED_26_18_SHIFT                                           18
6998 #define DDR_PHY_DCR_RESERVED_26_18_MASK                                            0x07FC0000U
6999
7000 /*Byte Mask*/
7001 #undef DDR_PHY_DCR_BYTEMASK_DEFVAL
7002 #undef DDR_PHY_DCR_BYTEMASK_SHIFT
7003 #undef DDR_PHY_DCR_BYTEMASK_MASK
7004 #define DDR_PHY_DCR_BYTEMASK_DEFVAL                                                0x0000040D
7005 #define DDR_PHY_DCR_BYTEMASK_SHIFT                                                 10
7006 #define DDR_PHY_DCR_BYTEMASK_MASK                                                  0x0003FC00U
7007
7008 /*DDR Type*/
7009 #undef DDR_PHY_DCR_DDRTYPE_DEFVAL
7010 #undef DDR_PHY_DCR_DDRTYPE_SHIFT
7011 #undef DDR_PHY_DCR_DDRTYPE_MASK
7012 #define DDR_PHY_DCR_DDRTYPE_DEFVAL                                                 0x0000040D
7013 #define DDR_PHY_DCR_DDRTYPE_SHIFT                                                  8
7014 #define DDR_PHY_DCR_DDRTYPE_MASK                                                   0x00000300U
7015
7016 /*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/
7017 #undef DDR_PHY_DCR_MPRDQ_DEFVAL
7018 #undef DDR_PHY_DCR_MPRDQ_SHIFT
7019 #undef DDR_PHY_DCR_MPRDQ_MASK
7020 #define DDR_PHY_DCR_MPRDQ_DEFVAL                                                   0x0000040D
7021 #define DDR_PHY_DCR_MPRDQ_SHIFT                                                    7
7022 #define DDR_PHY_DCR_MPRDQ_MASK                                                     0x00000080U
7023
7024 /*Primary DQ (DDR3 Only)*/
7025 #undef DDR_PHY_DCR_PDQ_DEFVAL
7026 #undef DDR_PHY_DCR_PDQ_SHIFT
7027 #undef DDR_PHY_DCR_PDQ_MASK
7028 #define DDR_PHY_DCR_PDQ_DEFVAL                                                     0x0000040D
7029 #define DDR_PHY_DCR_PDQ_SHIFT                                                      4
7030 #define DDR_PHY_DCR_PDQ_MASK                                                       0x00000070U
7031
7032 /*DDR 8-Bank*/
7033 #undef DDR_PHY_DCR_DDR8BNK_DEFVAL
7034 #undef DDR_PHY_DCR_DDR8BNK_SHIFT
7035 #undef DDR_PHY_DCR_DDR8BNK_MASK
7036 #define DDR_PHY_DCR_DDR8BNK_DEFVAL                                                 0x0000040D
7037 #define DDR_PHY_DCR_DDR8BNK_SHIFT                                                  3
7038 #define DDR_PHY_DCR_DDR8BNK_MASK                                                   0x00000008U
7039
7040 /*DDR Mode*/
7041 #undef DDR_PHY_DCR_DDRMD_DEFVAL
7042 #undef DDR_PHY_DCR_DDRMD_SHIFT
7043 #undef DDR_PHY_DCR_DDRMD_MASK
7044 #define DDR_PHY_DCR_DDRMD_DEFVAL                                                   0x0000040D
7045 #define DDR_PHY_DCR_DDRMD_SHIFT                                                    0
7046 #define DDR_PHY_DCR_DDRMD_MASK                                                     0x00000007U
7047
7048 /*Reserved. Return zeroes on reads.*/
7049 #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL
7050 #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
7051 #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK
7052 #define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                                        0x105A2D08
7053 #define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                                         29
7054 #define DDR_PHY_DTPR0_RESERVED_31_29_MASK                                          0xE0000000U
7055
7056 /*Activate to activate command delay (different banks)*/
7057 #undef DDR_PHY_DTPR0_TRRD_DEFVAL
7058 #undef DDR_PHY_DTPR0_TRRD_SHIFT
7059 #undef DDR_PHY_DTPR0_TRRD_MASK
7060 #define DDR_PHY_DTPR0_TRRD_DEFVAL                                                  0x105A2D08
7061 #define DDR_PHY_DTPR0_TRRD_SHIFT                                                   24
7062 #define DDR_PHY_DTPR0_TRRD_MASK                                                    0x1F000000U
7063
7064 /*Reserved. Return zeroes on reads.*/
7065 #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL
7066 #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT
7067 #undef DDR_PHY_DTPR0_RESERVED_23_MASK
7068 #define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                                           0x105A2D08
7069 #define DDR_PHY_DTPR0_RESERVED_23_SHIFT                                            23
7070 #define DDR_PHY_DTPR0_RESERVED_23_MASK                                             0x00800000U
7071
7072 /*Activate to precharge command delay*/
7073 #undef DDR_PHY_DTPR0_TRAS_DEFVAL
7074 #undef DDR_PHY_DTPR0_TRAS_SHIFT
7075 #undef DDR_PHY_DTPR0_TRAS_MASK
7076 #define DDR_PHY_DTPR0_TRAS_DEFVAL                                                  0x105A2D08
7077 #define DDR_PHY_DTPR0_TRAS_SHIFT                                                   16
7078 #define DDR_PHY_DTPR0_TRAS_MASK                                                    0x007F0000U
7079
7080 /*Reserved. Return zeroes on reads.*/
7081 #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL
7082 #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT
7083 #undef DDR_PHY_DTPR0_RESERVED_15_MASK
7084 #define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                                           0x105A2D08
7085 #define DDR_PHY_DTPR0_RESERVED_15_SHIFT                                            15
7086 #define DDR_PHY_DTPR0_RESERVED_15_MASK                                             0x00008000U
7087
7088 /*Precharge command period*/
7089 #undef DDR_PHY_DTPR0_TRP_DEFVAL
7090 #undef DDR_PHY_DTPR0_TRP_SHIFT
7091 #undef DDR_PHY_DTPR0_TRP_MASK
7092 #define DDR_PHY_DTPR0_TRP_DEFVAL                                                   0x105A2D08
7093 #define DDR_PHY_DTPR0_TRP_SHIFT                                                    8
7094 #define DDR_PHY_DTPR0_TRP_MASK                                                     0x00007F00U
7095
7096 /*Reserved. Return zeroes on reads.*/
7097 #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL
7098 #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
7099 #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK
7100 #define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                                          0x105A2D08
7101 #define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                                           5
7102 #define DDR_PHY_DTPR0_RESERVED_7_5_MASK                                            0x000000E0U
7103
7104 /*Internal read to precharge command delay*/
7105 #undef DDR_PHY_DTPR0_TRTP_DEFVAL
7106 #undef DDR_PHY_DTPR0_TRTP_SHIFT
7107 #undef DDR_PHY_DTPR0_TRTP_MASK
7108 #define DDR_PHY_DTPR0_TRTP_DEFVAL                                                  0x105A2D08
7109 #define DDR_PHY_DTPR0_TRTP_SHIFT                                                   0
7110 #define DDR_PHY_DTPR0_TRTP_MASK                                                    0x0000001FU
7111
7112 /*Reserved. Return zeroes on reads.*/
7113 #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL
7114 #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT
7115 #undef DDR_PHY_DTPR1_RESERVED_31_MASK
7116 #define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                                           0x5656041E
7117 #define DDR_PHY_DTPR1_RESERVED_31_SHIFT                                            31
7118 #define DDR_PHY_DTPR1_RESERVED_31_MASK                                             0x80000000U
7119
7120 /*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/
7121 #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL
7122 #undef DDR_PHY_DTPR1_TWLMRD_SHIFT
7123 #undef DDR_PHY_DTPR1_TWLMRD_MASK
7124 #define DDR_PHY_DTPR1_TWLMRD_DEFVAL                                                0x5656041E
7125 #define DDR_PHY_DTPR1_TWLMRD_SHIFT                                                 24
7126 #define DDR_PHY_DTPR1_TWLMRD_MASK                                                  0x7F000000U
7127
7128 /*Reserved. Return zeroes on reads.*/
7129 #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL
7130 #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT
7131 #undef DDR_PHY_DTPR1_RESERVED_23_MASK
7132 #define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                                           0x5656041E
7133 #define DDR_PHY_DTPR1_RESERVED_23_SHIFT                                            23
7134 #define DDR_PHY_DTPR1_RESERVED_23_MASK                                             0x00800000U
7135
7136 /*4-bank activate period*/
7137 #undef DDR_PHY_DTPR1_TFAW_DEFVAL
7138 #undef DDR_PHY_DTPR1_TFAW_SHIFT
7139 #undef DDR_PHY_DTPR1_TFAW_MASK
7140 #define DDR_PHY_DTPR1_TFAW_DEFVAL                                                  0x5656041E
7141 #define DDR_PHY_DTPR1_TFAW_SHIFT                                                   16
7142 #define DDR_PHY_DTPR1_TFAW_MASK                                                    0x007F0000U
7143
7144 /*Reserved. Return zeroes on reads.*/
7145 #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL
7146 #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
7147 #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK
7148 #define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                                        0x5656041E
7149 #define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                                         11
7150 #define DDR_PHY_DTPR1_RESERVED_15_11_MASK                                          0x0000F800U
7151
7152 /*Load mode update delay (DDR4 and DDR3 only)*/
7153 #undef DDR_PHY_DTPR1_TMOD_DEFVAL
7154 #undef DDR_PHY_DTPR1_TMOD_SHIFT
7155 #undef DDR_PHY_DTPR1_TMOD_MASK
7156 #define DDR_PHY_DTPR1_TMOD_DEFVAL                                                  0x5656041E
7157 #define DDR_PHY_DTPR1_TMOD_SHIFT                                                   8
7158 #define DDR_PHY_DTPR1_TMOD_MASK                                                    0x00000700U
7159
7160 /*Reserved. Return zeroes on reads.*/
7161 #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL
7162 #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
7163 #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK
7164 #define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                                          0x5656041E
7165 #define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                                           5
7166 #define DDR_PHY_DTPR1_RESERVED_7_5_MASK                                            0x000000E0U
7167
7168 /*Load mode cycle time*/
7169 #undef DDR_PHY_DTPR1_TMRD_DEFVAL
7170 #undef DDR_PHY_DTPR1_TMRD_SHIFT
7171 #undef DDR_PHY_DTPR1_TMRD_MASK
7172 #define DDR_PHY_DTPR1_TMRD_DEFVAL                                                  0x5656041E
7173 #define DDR_PHY_DTPR1_TMRD_SHIFT                                                   0
7174 #define DDR_PHY_DTPR1_TMRD_MASK                                                    0x0000001FU
7175
7176 /*Reserved. Return zeroes on reads.*/
7177 #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL
7178 #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
7179 #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK
7180 #define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                                        0x000B01D0
7181 #define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                                         29
7182 #define DDR_PHY_DTPR2_RESERVED_31_29_MASK                                          0xE0000000U
7183
7184 /*Read to Write command delay. Valid values are*/
7185 #undef DDR_PHY_DTPR2_TRTW_DEFVAL
7186 #undef DDR_PHY_DTPR2_TRTW_SHIFT
7187 #undef DDR_PHY_DTPR2_TRTW_MASK
7188 #define DDR_PHY_DTPR2_TRTW_DEFVAL                                                  0x000B01D0
7189 #define DDR_PHY_DTPR2_TRTW_SHIFT                                                   28
7190 #define DDR_PHY_DTPR2_TRTW_MASK                                                    0x10000000U
7191
7192 /*Reserved. Return zeroes on reads.*/
7193 #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL
7194 #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
7195 #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK
7196 #define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                                        0x000B01D0
7197 #define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                                         25
7198 #define DDR_PHY_DTPR2_RESERVED_27_25_MASK                                          0x0E000000U
7199
7200 /*Read to ODT delay (DDR3 only)*/
7201 #undef DDR_PHY_DTPR2_TRTODT_DEFVAL
7202 #undef DDR_PHY_DTPR2_TRTODT_SHIFT
7203 #undef DDR_PHY_DTPR2_TRTODT_MASK
7204 #define DDR_PHY_DTPR2_TRTODT_DEFVAL                                                0x000B01D0
7205 #define DDR_PHY_DTPR2_TRTODT_SHIFT                                                 24
7206 #define DDR_PHY_DTPR2_TRTODT_MASK                                                  0x01000000U
7207
7208 /*Reserved. Return zeroes on reads.*/
7209 #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL
7210 #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
7211 #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK
7212 #define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                                        0x000B01D0
7213 #define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                                         20
7214 #define DDR_PHY_DTPR2_RESERVED_23_20_MASK                                          0x00F00000U
7215
7216 /*CKE minimum pulse width*/
7217 #undef DDR_PHY_DTPR2_TCKE_DEFVAL
7218 #undef DDR_PHY_DTPR2_TCKE_SHIFT
7219 #undef DDR_PHY_DTPR2_TCKE_MASK
7220 #define DDR_PHY_DTPR2_TCKE_DEFVAL                                                  0x000B01D0
7221 #define DDR_PHY_DTPR2_TCKE_SHIFT                                                   16
7222 #define DDR_PHY_DTPR2_TCKE_MASK                                                    0x000F0000U
7223
7224 /*Reserved. Return zeroes on reads.*/
7225 #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL
7226 #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
7227 #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK
7228 #define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                                        0x000B01D0
7229 #define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                                         10
7230 #define DDR_PHY_DTPR2_RESERVED_15_10_MASK                                          0x0000FC00U
7231
7232 /*Self refresh exit delay*/
7233 #undef DDR_PHY_DTPR2_TXS_DEFVAL
7234 #undef DDR_PHY_DTPR2_TXS_SHIFT
7235 #undef DDR_PHY_DTPR2_TXS_MASK
7236 #define DDR_PHY_DTPR2_TXS_DEFVAL                                                   0x000B01D0
7237 #define DDR_PHY_DTPR2_TXS_SHIFT                                                    0
7238 #define DDR_PHY_DTPR2_TXS_MASK                                                     0x000003FFU
7239
7240 /*ODT turn-off delay extension*/
7241 #undef DDR_PHY_DTPR3_TOFDX_DEFVAL
7242 #undef DDR_PHY_DTPR3_TOFDX_SHIFT
7243 #undef DDR_PHY_DTPR3_TOFDX_MASK
7244 #define DDR_PHY_DTPR3_TOFDX_DEFVAL                                                 0x02000804
7245 #define DDR_PHY_DTPR3_TOFDX_SHIFT                                                  29
7246 #define DDR_PHY_DTPR3_TOFDX_MASK                                                   0xE0000000U
7247
7248 /*Read to read and write to write command delay*/
7249 #undef DDR_PHY_DTPR3_TCCD_DEFVAL
7250 #undef DDR_PHY_DTPR3_TCCD_SHIFT
7251 #undef DDR_PHY_DTPR3_TCCD_MASK
7252 #define DDR_PHY_DTPR3_TCCD_DEFVAL                                                  0x02000804
7253 #define DDR_PHY_DTPR3_TCCD_SHIFT                                                   26
7254 #define DDR_PHY_DTPR3_TCCD_MASK                                                    0x1C000000U
7255
7256 /*DLL locking time*/
7257 #undef DDR_PHY_DTPR3_TDLLK_DEFVAL
7258 #undef DDR_PHY_DTPR3_TDLLK_SHIFT
7259 #undef DDR_PHY_DTPR3_TDLLK_MASK
7260 #define DDR_PHY_DTPR3_TDLLK_DEFVAL                                                 0x02000804
7261 #define DDR_PHY_DTPR3_TDLLK_SHIFT                                                  16
7262 #define DDR_PHY_DTPR3_TDLLK_MASK                                                   0x03FF0000U
7263
7264 /*Reserved. Return zeroes on reads.*/
7265 #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL
7266 #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
7267 #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK
7268 #define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                                        0x02000804
7269 #define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                                         12
7270 #define DDR_PHY_DTPR3_RESERVED_15_12_MASK                                          0x0000F000U
7271
7272 /*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/
7273 #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL
7274 #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
7275 #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK
7276 #define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                                             0x02000804
7277 #define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                                              8
7278 #define DDR_PHY_DTPR3_TDQSCKMAX_MASK                                               0x00000F00U
7279
7280 /*Reserved. Return zeroes on reads.*/
7281 #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL
7282 #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
7283 #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK
7284 #define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                                          0x02000804
7285 #define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                                           3
7286 #define DDR_PHY_DTPR3_RESERVED_7_3_MASK                                            0x000000F8U
7287
7288 /*DQS output access time from CK/CK# (LPDDR2/3 only)*/
7289 #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL
7290 #undef DDR_PHY_DTPR3_TDQSCK_SHIFT
7291 #undef DDR_PHY_DTPR3_TDQSCK_MASK
7292 #define DDR_PHY_DTPR3_TDQSCK_DEFVAL                                                0x02000804
7293 #define DDR_PHY_DTPR3_TDQSCK_SHIFT                                                 0
7294 #define DDR_PHY_DTPR3_TDQSCK_MASK                                                  0x00000007U
7295
7296 /*Reserved. Return zeroes on reads.*/
7297 #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL
7298 #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
7299 #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK
7300 #define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                                        0x01C02B10
7301 #define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                                         30
7302 #define DDR_PHY_DTPR4_RESERVED_31_30_MASK                                          0xC0000000U
7303
7304 /*ODT turn-on/turn-off delays (DDR2 only)*/
7305 #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL
7306 #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
7307 #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK
7308 #define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                                           0x01C02B10
7309 #define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                                            28
7310 #define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                                             0x30000000U
7311
7312 /*Reserved. Return zeroes on reads.*/
7313 #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL
7314 #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
7315 #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK
7316 #define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                                        0x01C02B10
7317 #define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                                         26
7318 #define DDR_PHY_DTPR4_RESERVED_27_26_MASK                                          0x0C000000U
7319
7320 /*Refresh-to-Refresh*/
7321 #undef DDR_PHY_DTPR4_TRFC_DEFVAL
7322 #undef DDR_PHY_DTPR4_TRFC_SHIFT
7323 #undef DDR_PHY_DTPR4_TRFC_MASK
7324 #define DDR_PHY_DTPR4_TRFC_DEFVAL                                                  0x01C02B10
7325 #define DDR_PHY_DTPR4_TRFC_SHIFT                                                   16
7326 #define DDR_PHY_DTPR4_TRFC_MASK                                                    0x03FF0000U
7327
7328 /*Reserved. Return zeroes on reads.*/
7329 #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL
7330 #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
7331 #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK
7332 #define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                                        0x01C02B10
7333 #define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                                         14
7334 #define DDR_PHY_DTPR4_RESERVED_15_14_MASK                                          0x0000C000U
7335
7336 /*Write leveling output delay*/
7337 #undef DDR_PHY_DTPR4_TWLO_DEFVAL
7338 #undef DDR_PHY_DTPR4_TWLO_SHIFT
7339 #undef DDR_PHY_DTPR4_TWLO_MASK
7340 #define DDR_PHY_DTPR4_TWLO_DEFVAL                                                  0x01C02B10
7341 #define DDR_PHY_DTPR4_TWLO_SHIFT                                                   8
7342 #define DDR_PHY_DTPR4_TWLO_MASK                                                    0x00003F00U
7343
7344 /*Reserved. Return zeroes on reads.*/
7345 #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL
7346 #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
7347 #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK
7348 #define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                                          0x01C02B10
7349 #define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                                           5
7350 #define DDR_PHY_DTPR4_RESERVED_7_5_MASK                                            0x000000E0U
7351
7352 /*Power down exit delay*/
7353 #undef DDR_PHY_DTPR4_TXP_DEFVAL
7354 #undef DDR_PHY_DTPR4_TXP_SHIFT
7355 #undef DDR_PHY_DTPR4_TXP_MASK
7356 #define DDR_PHY_DTPR4_TXP_DEFVAL                                                   0x01C02B10
7357 #define DDR_PHY_DTPR4_TXP_SHIFT                                                    0
7358 #define DDR_PHY_DTPR4_TXP_MASK                                                     0x0000001FU
7359
7360 /*Reserved. Return zeroes on reads.*/
7361 #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL
7362 #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
7363 #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK
7364 #define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                                        0x00872716
7365 #define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                                         24
7366 #define DDR_PHY_DTPR5_RESERVED_31_24_MASK                                          0xFF000000U
7367
7368 /*Activate to activate command delay (same bank)*/
7369 #undef DDR_PHY_DTPR5_TRC_DEFVAL
7370 #undef DDR_PHY_DTPR5_TRC_SHIFT
7371 #undef DDR_PHY_DTPR5_TRC_MASK
7372 #define DDR_PHY_DTPR5_TRC_DEFVAL                                                   0x00872716
7373 #define DDR_PHY_DTPR5_TRC_SHIFT                                                    16
7374 #define DDR_PHY_DTPR5_TRC_MASK                                                     0x00FF0000U
7375
7376 /*Reserved. Return zeroes on reads.*/
7377 #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL
7378 #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT
7379 #undef DDR_PHY_DTPR5_RESERVED_15_MASK
7380 #define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                                           0x00872716
7381 #define DDR_PHY_DTPR5_RESERVED_15_SHIFT                                            15
7382 #define DDR_PHY_DTPR5_RESERVED_15_MASK                                             0x00008000U
7383
7384 /*Activate to read or write delay*/
7385 #undef DDR_PHY_DTPR5_TRCD_DEFVAL
7386 #undef DDR_PHY_DTPR5_TRCD_SHIFT
7387 #undef DDR_PHY_DTPR5_TRCD_MASK
7388 #define DDR_PHY_DTPR5_TRCD_DEFVAL                                                  0x00872716
7389 #define DDR_PHY_DTPR5_TRCD_SHIFT                                                   8
7390 #define DDR_PHY_DTPR5_TRCD_MASK                                                    0x00007F00U
7391
7392 /*Reserved. Return zeroes on reads.*/
7393 #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL
7394 #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
7395 #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK
7396 #define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                                          0x00872716
7397 #define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                                           5
7398 #define DDR_PHY_DTPR5_RESERVED_7_5_MASK                                            0x000000E0U
7399
7400 /*Internal write to read command delay*/
7401 #undef DDR_PHY_DTPR5_TWTR_DEFVAL
7402 #undef DDR_PHY_DTPR5_TWTR_SHIFT
7403 #undef DDR_PHY_DTPR5_TWTR_MASK
7404 #define DDR_PHY_DTPR5_TWTR_DEFVAL                                                  0x00872716
7405 #define DDR_PHY_DTPR5_TWTR_SHIFT                                                   0
7406 #define DDR_PHY_DTPR5_TWTR_MASK                                                    0x0000001FU
7407
7408 /*PUB Write Latency Enable*/
7409 #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL
7410 #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT
7411 #undef DDR_PHY_DTPR6_PUBWLEN_MASK
7412 #define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                                               0x00000505
7413 #define DDR_PHY_DTPR6_PUBWLEN_SHIFT                                                31
7414 #define DDR_PHY_DTPR6_PUBWLEN_MASK                                                 0x80000000U
7415
7416 /*PUB Read Latency Enable*/
7417 #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL
7418 #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT
7419 #undef DDR_PHY_DTPR6_PUBRLEN_MASK
7420 #define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                                               0x00000505
7421 #define DDR_PHY_DTPR6_PUBRLEN_SHIFT                                                30
7422 #define DDR_PHY_DTPR6_PUBRLEN_MASK                                                 0x40000000U
7423
7424 /*Reserved. Return zeroes on reads.*/
7425 #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL
7426 #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
7427 #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK
7428 #define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                                        0x00000505
7429 #define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                                         14
7430 #define DDR_PHY_DTPR6_RESERVED_29_14_MASK                                          0x3FFFC000U
7431
7432 /*Write Latency*/
7433 #undef DDR_PHY_DTPR6_PUBWL_DEFVAL
7434 #undef DDR_PHY_DTPR6_PUBWL_SHIFT
7435 #undef DDR_PHY_DTPR6_PUBWL_MASK
7436 #define DDR_PHY_DTPR6_PUBWL_DEFVAL                                                 0x00000505
7437 #define DDR_PHY_DTPR6_PUBWL_SHIFT                                                  8
7438 #define DDR_PHY_DTPR6_PUBWL_MASK                                                   0x00003F00U
7439
7440 /*Reserved. Return zeroes on reads.*/
7441 #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL
7442 #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
7443 #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK
7444 #define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                                          0x00000505
7445 #define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                                           6
7446 #define DDR_PHY_DTPR6_RESERVED_7_6_MASK                                            0x000000C0U
7447
7448 /*Read Latency*/
7449 #undef DDR_PHY_DTPR6_PUBRL_DEFVAL
7450 #undef DDR_PHY_DTPR6_PUBRL_SHIFT
7451 #undef DDR_PHY_DTPR6_PUBRL_MASK
7452 #define DDR_PHY_DTPR6_PUBRL_DEFVAL                                                 0x00000505
7453 #define DDR_PHY_DTPR6_PUBRL_SHIFT                                                  0
7454 #define DDR_PHY_DTPR6_PUBRL_MASK                                                   0x0000003FU
7455
7456 /*Reserved. Return zeroes on reads.*/
7457 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL
7458 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
7459 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK
7460 #define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                                       0x08400020
7461 #define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                                        31
7462 #define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                                         0x80000000U
7463
7464 /*RDMIMM Quad CS Enable*/
7465 #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL
7466 #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
7467 #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK
7468 #define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                                             0x08400020
7469 #define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                                              30
7470 #define DDR_PHY_RDIMMGCR0_QCSEN_MASK                                               0x40000000U
7471
7472 /*Reserved. Return zeroes on reads.*/
7473 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL
7474 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
7475 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK
7476 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                                    0x08400020
7477 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                                     28
7478 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                                      0x30000000U
7479
7480 /*RDIMM Outputs I/O Mode*/
7481 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL
7482 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
7483 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK
7484 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                                          0x08400020
7485 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                                           27
7486 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                                            0x08000000U
7487
7488 /*Reserved. Return zeroes on reads.*/
7489 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL
7490 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
7491 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK
7492 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                                    0x08400020
7493 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                                     24
7494 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                                      0x07000000U
7495
7496 /*ERROUT# Output Enable*/
7497 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL
7498 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
7499 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK
7500 #define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                                          0x08400020
7501 #define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                                           23
7502 #define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                                            0x00800000U
7503
7504 /*ERROUT# I/O Mode*/
7505 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL
7506 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
7507 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK
7508 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                                         0x08400020
7509 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                                          22
7510 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                                           0x00400000U
7511
7512 /*ERROUT# Power Down Receiver*/
7513 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL
7514 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
7515 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK
7516 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                                         0x08400020
7517 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                                          21
7518 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                                           0x00200000U
7519
7520 /*Reserved. Return zeroes on reads.*/
7521 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL
7522 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
7523 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK
7524 #define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                                       0x08400020
7525 #define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                                        20
7526 #define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                                         0x00100000U
7527
7528 /*ERROUT# On-Die Termination*/
7529 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL
7530 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
7531 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK
7532 #define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                                         0x08400020
7533 #define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                                          19
7534 #define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                                           0x00080000U
7535
7536 /*Load Reduced DIMM*/
7537 #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL
7538 #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
7539 #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK
7540 #define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                                            0x08400020
7541 #define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                                             18
7542 #define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                                              0x00040000U
7543
7544 /*PAR_IN I/O Mode*/
7545 #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL
7546 #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
7547 #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK
7548 #define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                                          0x08400020
7549 #define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                                           17
7550 #define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                                            0x00020000U
7551
7552 /*Reserved. Return zeroes on reads.*/
7553 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL
7554 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
7555 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK
7556 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                                     0x08400020
7557 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                                      8
7558 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                                       0x0001FF00U
7559
7560 /*Reserved. Return zeroes on reads.*/
7561 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL
7562 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
7563 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK
7564 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                                     0x08400020
7565 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                                      6
7566 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                                       0x000000C0U
7567
7568 /*Rank Mirror Enable.*/
7569 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL
7570 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
7571 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK
7572 #define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                                          0x08400020
7573 #define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                                           4
7574 #define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                                            0x00000030U
7575
7576 /*Reserved. Return zeroes on reads.*/
7577 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL
7578 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
7579 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK
7580 #define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                                        0x08400020
7581 #define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                                         3
7582 #define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                                          0x00000008U
7583
7584 /*Stop on Parity Error*/
7585 #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL
7586 #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
7587 #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK
7588 #define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                                            0x08400020
7589 #define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                                             2
7590 #define DDR_PHY_RDIMMGCR0_SOPERR_MASK                                              0x00000004U
7591
7592 /*Parity Error No Registering*/
7593 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL
7594 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
7595 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK
7596 #define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                                          0x08400020
7597 #define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                                           1
7598 #define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                                            0x00000002U
7599
7600 /*Registered DIMM*/
7601 #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL
7602 #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
7603 #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK
7604 #define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                                             0x08400020
7605 #define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                                              0
7606 #define DDR_PHY_RDIMMGCR0_RDIMM_MASK                                               0x00000001U
7607
7608 /*Reserved. Return zeroes on reads.*/
7609 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL
7610 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
7611 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK
7612 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                                    0x00000C80
7613 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                                     29
7614 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                                      0xE0000000U
7615
7616 /*Address [17] B-side Inversion Disable*/
7617 #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL
7618 #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT
7619 #undef DDR_PHY_RDIMMGCR1_A17BID_MASK
7620 #define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                                            0x00000C80
7621 #define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                                             28
7622 #define DDR_PHY_RDIMMGCR1_A17BID_MASK                                              0x10000000U
7623
7624 /*Reserved. Return zeroes on reads.*/
7625 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL
7626 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
7627 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK
7628 #define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                                       0x00000C80
7629 #define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                                        27
7630 #define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                                         0x08000000U
7631
7632 /*Command word to command word programming delay*/
7633 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL
7634 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
7635 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK
7636 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                                         0x00000C80
7637 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                                          24
7638 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                                           0x07000000U
7639
7640 /*Reserved. Return zeroes on reads.*/
7641 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL
7642 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
7643 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK
7644 #define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                                       0x00000C80
7645 #define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                                        23
7646 #define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                                         0x00800000U
7647
7648 /*Command word to command word programming delay*/
7649 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL
7650 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
7651 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK
7652 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                                          0x00000C80
7653 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                                           20
7654 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                                            0x00700000U
7655
7656 /*Reserved. Return zeroes on reads.*/
7657 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL
7658 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
7659 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK
7660 #define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                                       0x00000C80
7661 #define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                                        19
7662 #define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                                         0x00080000U
7663
7664 /*Command word to command word programming delay*/
7665 #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL
7666 #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
7667 #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK
7668 #define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                                            0x00000C80
7669 #define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                                             16
7670 #define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                                              0x00070000U
7671
7672 /*Reserved. Return zeroes on reads.*/
7673 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL
7674 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
7675 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK
7676 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                                    0x00000C80
7677 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                                     14
7678 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                                      0x0000C000U
7679
7680 /*Stabilization time*/
7681 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL
7682 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
7683 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK
7684 #define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                                           0x00000C80
7685 #define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                                            0
7686 #define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                                             0x00003FFFU
7687
7688 /*Control Word 15*/
7689 #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
7690 #undef DDR_PHY_RDIMMCR1_RC15_SHIFT
7691 #undef DDR_PHY_RDIMMCR1_RC15_MASK
7692 #define DDR_PHY_RDIMMCR1_RC15_DEFVAL                                               0x00000000
7693 #define DDR_PHY_RDIMMCR1_RC15_SHIFT                                                28
7694 #define DDR_PHY_RDIMMCR1_RC15_MASK                                                 0xF0000000U
7695
7696 /*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/
7697 #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL
7698 #undef DDR_PHY_RDIMMCR1_RC14_SHIFT
7699 #undef DDR_PHY_RDIMMCR1_RC14_MASK
7700 #define DDR_PHY_RDIMMCR1_RC14_DEFVAL                                               0x00000000
7701 #define DDR_PHY_RDIMMCR1_RC14_SHIFT                                                24
7702 #define DDR_PHY_RDIMMCR1_RC14_MASK                                                 0x0F000000U
7703
7704 /*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/
7705 #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL
7706 #undef DDR_PHY_RDIMMCR1_RC13_SHIFT
7707 #undef DDR_PHY_RDIMMCR1_RC13_MASK
7708 #define DDR_PHY_RDIMMCR1_RC13_DEFVAL                                               0x00000000
7709 #define DDR_PHY_RDIMMCR1_RC13_SHIFT                                                20
7710 #define DDR_PHY_RDIMMCR1_RC13_MASK                                                 0x00F00000U
7711
7712 /*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/
7713 #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL
7714 #undef DDR_PHY_RDIMMCR1_RC12_SHIFT
7715 #undef DDR_PHY_RDIMMCR1_RC12_MASK
7716 #define DDR_PHY_RDIMMCR1_RC12_DEFVAL                                               0x00000000
7717 #define DDR_PHY_RDIMMCR1_RC12_SHIFT                                                16
7718 #define DDR_PHY_RDIMMCR1_RC12_MASK                                                 0x000F0000U
7719
7720 /*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
7721                 rol Word)*/
7722 #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL
7723 #undef DDR_PHY_RDIMMCR1_RC11_SHIFT
7724 #undef DDR_PHY_RDIMMCR1_RC11_MASK
7725 #define DDR_PHY_RDIMMCR1_RC11_DEFVAL                                               0x00000000
7726 #define DDR_PHY_RDIMMCR1_RC11_SHIFT                                                12
7727 #define DDR_PHY_RDIMMCR1_RC11_MASK                                                 0x0000F000U
7728
7729 /*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/
7730 #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL
7731 #undef DDR_PHY_RDIMMCR1_RC10_SHIFT
7732 #undef DDR_PHY_RDIMMCR1_RC10_MASK
7733 #define DDR_PHY_RDIMMCR1_RC10_DEFVAL                                               0x00000000
7734 #define DDR_PHY_RDIMMCR1_RC10_SHIFT                                                8
7735 #define DDR_PHY_RDIMMCR1_RC10_MASK                                                 0x00000F00U
7736
7737 /*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/
7738 #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL
7739 #undef DDR_PHY_RDIMMCR1_RC9_SHIFT
7740 #undef DDR_PHY_RDIMMCR1_RC9_MASK
7741 #define DDR_PHY_RDIMMCR1_RC9_DEFVAL                                                0x00000000
7742 #define DDR_PHY_RDIMMCR1_RC9_SHIFT                                                 4
7743 #define DDR_PHY_RDIMMCR1_RC9_MASK                                                  0x000000F0U
7744
7745 /*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
7746                 Control Word)*/
7747 #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL
7748 #undef DDR_PHY_RDIMMCR1_RC8_SHIFT
7749 #undef DDR_PHY_RDIMMCR1_RC8_MASK
7750 #define DDR_PHY_RDIMMCR1_RC8_DEFVAL                                                0x00000000
7751 #define DDR_PHY_RDIMMCR1_RC8_SHIFT                                                 0
7752 #define DDR_PHY_RDIMMCR1_RC8_MASK                                                  0x0000000FU
7753
7754 /*Reserved. Return zeroes on reads.*/
7755 #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL
7756 #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT
7757 #undef DDR_PHY_MR0_RESERVED_31_8_MASK
7758 #define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                                           0x00000052
7759 #define DDR_PHY_MR0_RESERVED_31_8_SHIFT                                            8
7760 #define DDR_PHY_MR0_RESERVED_31_8_MASK                                             0xFFFFFF00U
7761
7762 /*CA Terminating Rank*/
7763 #undef DDR_PHY_MR0_CATR_DEFVAL
7764 #undef DDR_PHY_MR0_CATR_SHIFT
7765 #undef DDR_PHY_MR0_CATR_MASK
7766 #define DDR_PHY_MR0_CATR_DEFVAL                                                    0x00000052
7767 #define DDR_PHY_MR0_CATR_SHIFT                                                     7
7768 #define DDR_PHY_MR0_CATR_MASK                                                      0x00000080U
7769
7770 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7771 #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL
7772 #undef DDR_PHY_MR0_RSVD_6_5_SHIFT
7773 #undef DDR_PHY_MR0_RSVD_6_5_MASK
7774 #define DDR_PHY_MR0_RSVD_6_5_DEFVAL                                                0x00000052
7775 #define DDR_PHY_MR0_RSVD_6_5_SHIFT                                                 5
7776 #define DDR_PHY_MR0_RSVD_6_5_MASK                                                  0x00000060U
7777
7778 /*Built-in Self-Test for RZQ*/
7779 #undef DDR_PHY_MR0_RZQI_DEFVAL
7780 #undef DDR_PHY_MR0_RZQI_SHIFT
7781 #undef DDR_PHY_MR0_RZQI_MASK
7782 #define DDR_PHY_MR0_RZQI_DEFVAL                                                    0x00000052
7783 #define DDR_PHY_MR0_RZQI_SHIFT                                                     3
7784 #define DDR_PHY_MR0_RZQI_MASK                                                      0x00000018U
7785
7786 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7787 #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL
7788 #undef DDR_PHY_MR0_RSVD_2_0_SHIFT
7789 #undef DDR_PHY_MR0_RSVD_2_0_MASK
7790 #define DDR_PHY_MR0_RSVD_2_0_DEFVAL                                                0x00000052
7791 #define DDR_PHY_MR0_RSVD_2_0_SHIFT                                                 0
7792 #define DDR_PHY_MR0_RSVD_2_0_MASK                                                  0x00000007U
7793
7794 /*Reserved. Return zeroes on reads.*/
7795 #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL
7796 #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT
7797 #undef DDR_PHY_MR1_RESERVED_31_8_MASK
7798 #define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                                           0x00000004
7799 #define DDR_PHY_MR1_RESERVED_31_8_SHIFT                                            8
7800 #define DDR_PHY_MR1_RESERVED_31_8_MASK                                             0xFFFFFF00U
7801
7802 /*Read Postamble Length*/
7803 #undef DDR_PHY_MR1_RDPST_DEFVAL
7804 #undef DDR_PHY_MR1_RDPST_SHIFT
7805 #undef DDR_PHY_MR1_RDPST_MASK
7806 #define DDR_PHY_MR1_RDPST_DEFVAL                                                   0x00000004
7807 #define DDR_PHY_MR1_RDPST_SHIFT                                                    7
7808 #define DDR_PHY_MR1_RDPST_MASK                                                     0x00000080U
7809
7810 /*Write-recovery for auto-precharge command*/
7811 #undef DDR_PHY_MR1_NWR_DEFVAL
7812 #undef DDR_PHY_MR1_NWR_SHIFT
7813 #undef DDR_PHY_MR1_NWR_MASK
7814 #define DDR_PHY_MR1_NWR_DEFVAL                                                     0x00000004
7815 #define DDR_PHY_MR1_NWR_SHIFT                                                      4
7816 #define DDR_PHY_MR1_NWR_MASK                                                       0x00000070U
7817
7818 /*Read Preamble Length*/
7819 #undef DDR_PHY_MR1_RDPRE_DEFVAL
7820 #undef DDR_PHY_MR1_RDPRE_SHIFT
7821 #undef DDR_PHY_MR1_RDPRE_MASK
7822 #define DDR_PHY_MR1_RDPRE_DEFVAL                                                   0x00000004
7823 #define DDR_PHY_MR1_RDPRE_SHIFT                                                    3
7824 #define DDR_PHY_MR1_RDPRE_MASK                                                     0x00000008U
7825
7826 /*Write Preamble Length*/
7827 #undef DDR_PHY_MR1_WRPRE_DEFVAL
7828 #undef DDR_PHY_MR1_WRPRE_SHIFT
7829 #undef DDR_PHY_MR1_WRPRE_MASK
7830 #define DDR_PHY_MR1_WRPRE_DEFVAL                                                   0x00000004
7831 #define DDR_PHY_MR1_WRPRE_SHIFT                                                    2
7832 #define DDR_PHY_MR1_WRPRE_MASK                                                     0x00000004U
7833
7834 /*Burst Length*/
7835 #undef DDR_PHY_MR1_BL_DEFVAL
7836 #undef DDR_PHY_MR1_BL_SHIFT
7837 #undef DDR_PHY_MR1_BL_MASK
7838 #define DDR_PHY_MR1_BL_DEFVAL                                                      0x00000004
7839 #define DDR_PHY_MR1_BL_SHIFT                                                       0
7840 #define DDR_PHY_MR1_BL_MASK                                                        0x00000003U
7841
7842 /*Reserved. Return zeroes on reads.*/
7843 #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL
7844 #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT
7845 #undef DDR_PHY_MR2_RESERVED_31_8_MASK
7846 #define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                                           0x00000000
7847 #define DDR_PHY_MR2_RESERVED_31_8_SHIFT                                            8
7848 #define DDR_PHY_MR2_RESERVED_31_8_MASK                                             0xFFFFFF00U
7849
7850 /*Write Leveling*/
7851 #undef DDR_PHY_MR2_WRL_DEFVAL
7852 #undef DDR_PHY_MR2_WRL_SHIFT
7853 #undef DDR_PHY_MR2_WRL_MASK
7854 #define DDR_PHY_MR2_WRL_DEFVAL                                                     0x00000000
7855 #define DDR_PHY_MR2_WRL_SHIFT                                                      7
7856 #define DDR_PHY_MR2_WRL_MASK                                                       0x00000080U
7857
7858 /*Write Latency Set*/
7859 #undef DDR_PHY_MR2_WLS_DEFVAL
7860 #undef DDR_PHY_MR2_WLS_SHIFT
7861 #undef DDR_PHY_MR2_WLS_MASK
7862 #define DDR_PHY_MR2_WLS_DEFVAL                                                     0x00000000
7863 #define DDR_PHY_MR2_WLS_SHIFT                                                      6
7864 #define DDR_PHY_MR2_WLS_MASK                                                       0x00000040U
7865
7866 /*Write Latency*/
7867 #undef DDR_PHY_MR2_WL_DEFVAL
7868 #undef DDR_PHY_MR2_WL_SHIFT
7869 #undef DDR_PHY_MR2_WL_MASK
7870 #define DDR_PHY_MR2_WL_DEFVAL                                                      0x00000000
7871 #define DDR_PHY_MR2_WL_SHIFT                                                       3
7872 #define DDR_PHY_MR2_WL_MASK                                                        0x00000038U
7873
7874 /*Read Latency*/
7875 #undef DDR_PHY_MR2_RL_DEFVAL
7876 #undef DDR_PHY_MR2_RL_SHIFT
7877 #undef DDR_PHY_MR2_RL_MASK
7878 #define DDR_PHY_MR2_RL_DEFVAL                                                      0x00000000
7879 #define DDR_PHY_MR2_RL_SHIFT                                                       0
7880 #define DDR_PHY_MR2_RL_MASK                                                        0x00000007U
7881
7882 /*Reserved. Return zeroes on reads.*/
7883 #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL
7884 #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT
7885 #undef DDR_PHY_MR3_RESERVED_31_8_MASK
7886 #define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                                           0x00000031
7887 #define DDR_PHY_MR3_RESERVED_31_8_SHIFT                                            8
7888 #define DDR_PHY_MR3_RESERVED_31_8_MASK                                             0xFFFFFF00U
7889
7890 /*DBI-Write Enable*/
7891 #undef DDR_PHY_MR3_DBIWR_DEFVAL
7892 #undef DDR_PHY_MR3_DBIWR_SHIFT
7893 #undef DDR_PHY_MR3_DBIWR_MASK
7894 #define DDR_PHY_MR3_DBIWR_DEFVAL                                                   0x00000031
7895 #define DDR_PHY_MR3_DBIWR_SHIFT                                                    7
7896 #define DDR_PHY_MR3_DBIWR_MASK                                                     0x00000080U
7897
7898 /*DBI-Read Enable*/
7899 #undef DDR_PHY_MR3_DBIRD_DEFVAL
7900 #undef DDR_PHY_MR3_DBIRD_SHIFT
7901 #undef DDR_PHY_MR3_DBIRD_MASK
7902 #define DDR_PHY_MR3_DBIRD_DEFVAL                                                   0x00000031
7903 #define DDR_PHY_MR3_DBIRD_SHIFT                                                    6
7904 #define DDR_PHY_MR3_DBIRD_MASK                                                     0x00000040U
7905
7906 /*Pull-down Drive Strength*/
7907 #undef DDR_PHY_MR3_PDDS_DEFVAL
7908 #undef DDR_PHY_MR3_PDDS_SHIFT
7909 #undef DDR_PHY_MR3_PDDS_MASK
7910 #define DDR_PHY_MR3_PDDS_DEFVAL                                                    0x00000031
7911 #define DDR_PHY_MR3_PDDS_SHIFT                                                     3
7912 #define DDR_PHY_MR3_PDDS_MASK                                                      0x00000038U
7913
7914 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7915 #undef DDR_PHY_MR3_RSVD_DEFVAL
7916 #undef DDR_PHY_MR3_RSVD_SHIFT
7917 #undef DDR_PHY_MR3_RSVD_MASK
7918 #define DDR_PHY_MR3_RSVD_DEFVAL                                                    0x00000031
7919 #define DDR_PHY_MR3_RSVD_SHIFT                                                     2
7920 #define DDR_PHY_MR3_RSVD_MASK                                                      0x00000004U
7921
7922 /*Write Postamble Length*/
7923 #undef DDR_PHY_MR3_WRPST_DEFVAL
7924 #undef DDR_PHY_MR3_WRPST_SHIFT
7925 #undef DDR_PHY_MR3_WRPST_MASK
7926 #define DDR_PHY_MR3_WRPST_DEFVAL                                                   0x00000031
7927 #define DDR_PHY_MR3_WRPST_SHIFT                                                    1
7928 #define DDR_PHY_MR3_WRPST_MASK                                                     0x00000002U
7929
7930 /*Pull-up Calibration Point*/
7931 #undef DDR_PHY_MR3_PUCAL_DEFVAL
7932 #undef DDR_PHY_MR3_PUCAL_SHIFT
7933 #undef DDR_PHY_MR3_PUCAL_MASK
7934 #define DDR_PHY_MR3_PUCAL_DEFVAL                                                   0x00000031
7935 #define DDR_PHY_MR3_PUCAL_SHIFT                                                    0
7936 #define DDR_PHY_MR3_PUCAL_MASK                                                     0x00000001U
7937
7938 /*Reserved. Return zeroes on reads.*/
7939 #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL
7940 #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT
7941 #undef DDR_PHY_MR4_RESERVED_31_16_MASK
7942 #define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                                          0x00000000
7943 #define DDR_PHY_MR4_RESERVED_31_16_SHIFT                                           16
7944 #define DDR_PHY_MR4_RESERVED_31_16_MASK                                            0xFFFF0000U
7945
7946 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7947 #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL
7948 #undef DDR_PHY_MR4_RSVD_15_13_SHIFT
7949 #undef DDR_PHY_MR4_RSVD_15_13_MASK
7950 #define DDR_PHY_MR4_RSVD_15_13_DEFVAL                                              0x00000000
7951 #define DDR_PHY_MR4_RSVD_15_13_SHIFT                                               13
7952 #define DDR_PHY_MR4_RSVD_15_13_MASK                                                0x0000E000U
7953
7954 /*Write Preamble*/
7955 #undef DDR_PHY_MR4_WRP_DEFVAL
7956 #undef DDR_PHY_MR4_WRP_SHIFT
7957 #undef DDR_PHY_MR4_WRP_MASK
7958 #define DDR_PHY_MR4_WRP_DEFVAL                                                     0x00000000
7959 #define DDR_PHY_MR4_WRP_SHIFT                                                      12
7960 #define DDR_PHY_MR4_WRP_MASK                                                       0x00001000U
7961
7962 /*Read Preamble*/
7963 #undef DDR_PHY_MR4_RDP_DEFVAL
7964 #undef DDR_PHY_MR4_RDP_SHIFT
7965 #undef DDR_PHY_MR4_RDP_MASK
7966 #define DDR_PHY_MR4_RDP_DEFVAL                                                     0x00000000
7967 #define DDR_PHY_MR4_RDP_SHIFT                                                      11
7968 #define DDR_PHY_MR4_RDP_MASK                                                       0x00000800U
7969
7970 /*Read Preamble Training Mode*/
7971 #undef DDR_PHY_MR4_RPTM_DEFVAL
7972 #undef DDR_PHY_MR4_RPTM_SHIFT
7973 #undef DDR_PHY_MR4_RPTM_MASK
7974 #define DDR_PHY_MR4_RPTM_DEFVAL                                                    0x00000000
7975 #define DDR_PHY_MR4_RPTM_SHIFT                                                     10
7976 #define DDR_PHY_MR4_RPTM_MASK                                                      0x00000400U
7977
7978 /*Self Refresh Abort*/
7979 #undef DDR_PHY_MR4_SRA_DEFVAL
7980 #undef DDR_PHY_MR4_SRA_SHIFT
7981 #undef DDR_PHY_MR4_SRA_MASK
7982 #define DDR_PHY_MR4_SRA_DEFVAL                                                     0x00000000
7983 #define DDR_PHY_MR4_SRA_SHIFT                                                      9
7984 #define DDR_PHY_MR4_SRA_MASK                                                       0x00000200U
7985
7986 /*CS to Command Latency Mode*/
7987 #undef DDR_PHY_MR4_CS2CMDL_DEFVAL
7988 #undef DDR_PHY_MR4_CS2CMDL_SHIFT
7989 #undef DDR_PHY_MR4_CS2CMDL_MASK
7990 #define DDR_PHY_MR4_CS2CMDL_DEFVAL                                                 0x00000000
7991 #define DDR_PHY_MR4_CS2CMDL_SHIFT                                                  6
7992 #define DDR_PHY_MR4_CS2CMDL_MASK                                                   0x000001C0U
7993
7994 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7995 #undef DDR_PHY_MR4_RSVD1_DEFVAL
7996 #undef DDR_PHY_MR4_RSVD1_SHIFT
7997 #undef DDR_PHY_MR4_RSVD1_MASK
7998 #define DDR_PHY_MR4_RSVD1_DEFVAL                                                   0x00000000
7999 #define DDR_PHY_MR4_RSVD1_SHIFT                                                    5
8000 #define DDR_PHY_MR4_RSVD1_MASK                                                     0x00000020U
8001
8002 /*Internal VREF Monitor*/
8003 #undef DDR_PHY_MR4_IVM_DEFVAL
8004 #undef DDR_PHY_MR4_IVM_SHIFT
8005 #undef DDR_PHY_MR4_IVM_MASK
8006 #define DDR_PHY_MR4_IVM_DEFVAL                                                     0x00000000
8007 #define DDR_PHY_MR4_IVM_SHIFT                                                      4
8008 #define DDR_PHY_MR4_IVM_MASK                                                       0x00000010U
8009
8010 /*Temperature Controlled Refresh Mode*/
8011 #undef DDR_PHY_MR4_TCRM_DEFVAL
8012 #undef DDR_PHY_MR4_TCRM_SHIFT
8013 #undef DDR_PHY_MR4_TCRM_MASK
8014 #define DDR_PHY_MR4_TCRM_DEFVAL                                                    0x00000000
8015 #define DDR_PHY_MR4_TCRM_SHIFT                                                     3
8016 #define DDR_PHY_MR4_TCRM_MASK                                                      0x00000008U
8017
8018 /*Temperature Controlled Refresh Range*/
8019 #undef DDR_PHY_MR4_TCRR_DEFVAL
8020 #undef DDR_PHY_MR4_TCRR_SHIFT
8021 #undef DDR_PHY_MR4_TCRR_MASK
8022 #define DDR_PHY_MR4_TCRR_DEFVAL                                                    0x00000000
8023 #define DDR_PHY_MR4_TCRR_SHIFT                                                     2
8024 #define DDR_PHY_MR4_TCRR_MASK                                                      0x00000004U
8025
8026 /*Maximum Power Down Mode*/
8027 #undef DDR_PHY_MR4_MPDM_DEFVAL
8028 #undef DDR_PHY_MR4_MPDM_SHIFT
8029 #undef DDR_PHY_MR4_MPDM_MASK
8030 #define DDR_PHY_MR4_MPDM_DEFVAL                                                    0x00000000
8031 #define DDR_PHY_MR4_MPDM_SHIFT                                                     1
8032 #define DDR_PHY_MR4_MPDM_MASK                                                      0x00000002U
8033
8034 /*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/
8035 #undef DDR_PHY_MR4_RSVD_0_DEFVAL
8036 #undef DDR_PHY_MR4_RSVD_0_SHIFT
8037 #undef DDR_PHY_MR4_RSVD_0_MASK
8038 #define DDR_PHY_MR4_RSVD_0_DEFVAL                                                  0x00000000
8039 #define DDR_PHY_MR4_RSVD_0_SHIFT                                                   0
8040 #define DDR_PHY_MR4_RSVD_0_MASK                                                    0x00000001U
8041
8042 /*Reserved. Return zeroes on reads.*/
8043 #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL
8044 #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT
8045 #undef DDR_PHY_MR5_RESERVED_31_16_MASK
8046 #define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                                          0x00000000
8047 #define DDR_PHY_MR5_RESERVED_31_16_SHIFT                                           16
8048 #define DDR_PHY_MR5_RESERVED_31_16_MASK                                            0xFFFF0000U
8049
8050 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8051 #undef DDR_PHY_MR5_RSVD_DEFVAL
8052 #undef DDR_PHY_MR5_RSVD_SHIFT
8053 #undef DDR_PHY_MR5_RSVD_MASK
8054 #define DDR_PHY_MR5_RSVD_DEFVAL                                                    0x00000000
8055 #define DDR_PHY_MR5_RSVD_SHIFT                                                     13
8056 #define DDR_PHY_MR5_RSVD_MASK                                                      0x0000E000U
8057
8058 /*Read DBI*/
8059 #undef DDR_PHY_MR5_RDBI_DEFVAL
8060 #undef DDR_PHY_MR5_RDBI_SHIFT
8061 #undef DDR_PHY_MR5_RDBI_MASK
8062 #define DDR_PHY_MR5_RDBI_DEFVAL                                                    0x00000000
8063 #define DDR_PHY_MR5_RDBI_SHIFT                                                     12
8064 #define DDR_PHY_MR5_RDBI_MASK                                                      0x00001000U
8065
8066 /*Write DBI*/
8067 #undef DDR_PHY_MR5_WDBI_DEFVAL
8068 #undef DDR_PHY_MR5_WDBI_SHIFT
8069 #undef DDR_PHY_MR5_WDBI_MASK
8070 #define DDR_PHY_MR5_WDBI_DEFVAL                                                    0x00000000
8071 #define DDR_PHY_MR5_WDBI_SHIFT                                                     11
8072 #define DDR_PHY_MR5_WDBI_MASK                                                      0x00000800U
8073
8074 /*Data Mask*/
8075 #undef DDR_PHY_MR5_DM_DEFVAL
8076 #undef DDR_PHY_MR5_DM_SHIFT
8077 #undef DDR_PHY_MR5_DM_MASK
8078 #define DDR_PHY_MR5_DM_DEFVAL                                                      0x00000000
8079 #define DDR_PHY_MR5_DM_SHIFT                                                       10
8080 #define DDR_PHY_MR5_DM_MASK                                                        0x00000400U
8081
8082 /*CA Parity Persistent Error*/
8083 #undef DDR_PHY_MR5_CAPPE_DEFVAL
8084 #undef DDR_PHY_MR5_CAPPE_SHIFT
8085 #undef DDR_PHY_MR5_CAPPE_MASK
8086 #define DDR_PHY_MR5_CAPPE_DEFVAL                                                   0x00000000
8087 #define DDR_PHY_MR5_CAPPE_SHIFT                                                    9
8088 #define DDR_PHY_MR5_CAPPE_MASK                                                     0x00000200U
8089
8090 /*RTT_PARK*/
8091 #undef DDR_PHY_MR5_RTTPARK_DEFVAL
8092 #undef DDR_PHY_MR5_RTTPARK_SHIFT
8093 #undef DDR_PHY_MR5_RTTPARK_MASK
8094 #define DDR_PHY_MR5_RTTPARK_DEFVAL                                                 0x00000000
8095 #define DDR_PHY_MR5_RTTPARK_SHIFT                                                  6
8096 #define DDR_PHY_MR5_RTTPARK_MASK                                                   0x000001C0U
8097
8098 /*ODT Input Buffer during Power Down mode*/
8099 #undef DDR_PHY_MR5_ODTIBPD_DEFVAL
8100 #undef DDR_PHY_MR5_ODTIBPD_SHIFT
8101 #undef DDR_PHY_MR5_ODTIBPD_MASK
8102 #define DDR_PHY_MR5_ODTIBPD_DEFVAL                                                 0x00000000
8103 #define DDR_PHY_MR5_ODTIBPD_SHIFT                                                  5
8104 #define DDR_PHY_MR5_ODTIBPD_MASK                                                   0x00000020U
8105
8106 /*C/A Parity Error Status*/
8107 #undef DDR_PHY_MR5_CAPES_DEFVAL
8108 #undef DDR_PHY_MR5_CAPES_SHIFT
8109 #undef DDR_PHY_MR5_CAPES_MASK
8110 #define DDR_PHY_MR5_CAPES_DEFVAL                                                   0x00000000
8111 #define DDR_PHY_MR5_CAPES_SHIFT                                                    4
8112 #define DDR_PHY_MR5_CAPES_MASK                                                     0x00000010U
8113
8114 /*CRC Error Clear*/
8115 #undef DDR_PHY_MR5_CRCEC_DEFVAL
8116 #undef DDR_PHY_MR5_CRCEC_SHIFT
8117 #undef DDR_PHY_MR5_CRCEC_MASK
8118 #define DDR_PHY_MR5_CRCEC_DEFVAL                                                   0x00000000
8119 #define DDR_PHY_MR5_CRCEC_SHIFT                                                    3
8120 #define DDR_PHY_MR5_CRCEC_MASK                                                     0x00000008U
8121
8122 /*C/A Parity Latency Mode*/
8123 #undef DDR_PHY_MR5_CAPM_DEFVAL
8124 #undef DDR_PHY_MR5_CAPM_SHIFT
8125 #undef DDR_PHY_MR5_CAPM_MASK
8126 #define DDR_PHY_MR5_CAPM_DEFVAL                                                    0x00000000
8127 #define DDR_PHY_MR5_CAPM_SHIFT                                                     0
8128 #define DDR_PHY_MR5_CAPM_MASK                                                      0x00000007U
8129
8130 /*Reserved. Return zeroes on reads.*/
8131 #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL
8132 #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT
8133 #undef DDR_PHY_MR6_RESERVED_31_16_MASK
8134 #define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                                          0x00000000
8135 #define DDR_PHY_MR6_RESERVED_31_16_SHIFT                                           16
8136 #define DDR_PHY_MR6_RESERVED_31_16_MASK                                            0xFFFF0000U
8137
8138 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8139 #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL
8140 #undef DDR_PHY_MR6_RSVD_15_13_SHIFT
8141 #undef DDR_PHY_MR6_RSVD_15_13_MASK
8142 #define DDR_PHY_MR6_RSVD_15_13_DEFVAL                                              0x00000000
8143 #define DDR_PHY_MR6_RSVD_15_13_SHIFT                                               13
8144 #define DDR_PHY_MR6_RSVD_15_13_MASK                                                0x0000E000U
8145
8146 /*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/
8147 #undef DDR_PHY_MR6_TCCDL_DEFVAL
8148 #undef DDR_PHY_MR6_TCCDL_SHIFT
8149 #undef DDR_PHY_MR6_TCCDL_MASK
8150 #define DDR_PHY_MR6_TCCDL_DEFVAL                                                   0x00000000
8151 #define DDR_PHY_MR6_TCCDL_SHIFT                                                    10
8152 #define DDR_PHY_MR6_TCCDL_MASK                                                     0x00001C00U
8153
8154 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8155 #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL
8156 #undef DDR_PHY_MR6_RSVD_9_8_SHIFT
8157 #undef DDR_PHY_MR6_RSVD_9_8_MASK
8158 #define DDR_PHY_MR6_RSVD_9_8_DEFVAL                                                0x00000000
8159 #define DDR_PHY_MR6_RSVD_9_8_SHIFT                                                 8
8160 #define DDR_PHY_MR6_RSVD_9_8_MASK                                                  0x00000300U
8161
8162 /*VrefDQ Training Enable*/
8163 #undef DDR_PHY_MR6_VDDQTEN_DEFVAL
8164 #undef DDR_PHY_MR6_VDDQTEN_SHIFT
8165 #undef DDR_PHY_MR6_VDDQTEN_MASK
8166 #define DDR_PHY_MR6_VDDQTEN_DEFVAL                                                 0x00000000
8167 #define DDR_PHY_MR6_VDDQTEN_SHIFT                                                  7
8168 #define DDR_PHY_MR6_VDDQTEN_MASK                                                   0x00000080U
8169
8170 /*VrefDQ Training Range*/
8171 #undef DDR_PHY_MR6_VDQTRG_DEFVAL
8172 #undef DDR_PHY_MR6_VDQTRG_SHIFT
8173 #undef DDR_PHY_MR6_VDQTRG_MASK
8174 #define DDR_PHY_MR6_VDQTRG_DEFVAL                                                  0x00000000
8175 #define DDR_PHY_MR6_VDQTRG_SHIFT                                                   6
8176 #define DDR_PHY_MR6_VDQTRG_MASK                                                    0x00000040U
8177
8178 /*VrefDQ Training Values*/
8179 #undef DDR_PHY_MR6_VDQTVAL_DEFVAL
8180 #undef DDR_PHY_MR6_VDQTVAL_SHIFT
8181 #undef DDR_PHY_MR6_VDQTVAL_MASK
8182 #define DDR_PHY_MR6_VDQTVAL_DEFVAL                                                 0x00000000
8183 #define DDR_PHY_MR6_VDQTVAL_SHIFT                                                  0
8184 #define DDR_PHY_MR6_VDQTVAL_MASK                                                   0x0000003FU
8185
8186 /*Reserved. Return zeroes on reads.*/
8187 #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL
8188 #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT
8189 #undef DDR_PHY_MR11_RESERVED_31_8_MASK
8190 #define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                                          0x00000000
8191 #define DDR_PHY_MR11_RESERVED_31_8_SHIFT                                           8
8192 #define DDR_PHY_MR11_RESERVED_31_8_MASK                                            0xFFFFFF00U
8193
8194 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8195 #undef DDR_PHY_MR11_RSVD_DEFVAL
8196 #undef DDR_PHY_MR11_RSVD_SHIFT
8197 #undef DDR_PHY_MR11_RSVD_MASK
8198 #define DDR_PHY_MR11_RSVD_DEFVAL                                                   0x00000000
8199 #define DDR_PHY_MR11_RSVD_SHIFT                                                    3
8200 #define DDR_PHY_MR11_RSVD_MASK                                                     0x000000F8U
8201
8202 /*Power Down Control*/
8203 #undef DDR_PHY_MR11_PDCTL_DEFVAL
8204 #undef DDR_PHY_MR11_PDCTL_SHIFT
8205 #undef DDR_PHY_MR11_PDCTL_MASK
8206 #define DDR_PHY_MR11_PDCTL_DEFVAL                                                  0x00000000
8207 #define DDR_PHY_MR11_PDCTL_SHIFT                                                   2
8208 #define DDR_PHY_MR11_PDCTL_MASK                                                    0x00000004U
8209
8210 /*DQ Bus Receiver On-Die-Termination*/
8211 #undef DDR_PHY_MR11_DQODT_DEFVAL
8212 #undef DDR_PHY_MR11_DQODT_SHIFT
8213 #undef DDR_PHY_MR11_DQODT_MASK
8214 #define DDR_PHY_MR11_DQODT_DEFVAL                                                  0x00000000
8215 #define DDR_PHY_MR11_DQODT_SHIFT                                                   0
8216 #define DDR_PHY_MR11_DQODT_MASK                                                    0x00000003U
8217
8218 /*Reserved. Return zeroes on reads.*/
8219 #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL
8220 #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT
8221 #undef DDR_PHY_MR12_RESERVED_31_8_MASK
8222 #define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                                          0x0000004D
8223 #define DDR_PHY_MR12_RESERVED_31_8_SHIFT                                           8
8224 #define DDR_PHY_MR12_RESERVED_31_8_MASK                                            0xFFFFFF00U
8225
8226 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8227 #undef DDR_PHY_MR12_RSVD_DEFVAL
8228 #undef DDR_PHY_MR12_RSVD_SHIFT
8229 #undef DDR_PHY_MR12_RSVD_MASK
8230 #define DDR_PHY_MR12_RSVD_DEFVAL                                                   0x0000004D
8231 #define DDR_PHY_MR12_RSVD_SHIFT                                                    7
8232 #define DDR_PHY_MR12_RSVD_MASK                                                     0x00000080U
8233
8234 /*VREF_CA Range Select.*/
8235 #undef DDR_PHY_MR12_VR_CA_DEFVAL
8236 #undef DDR_PHY_MR12_VR_CA_SHIFT
8237 #undef DDR_PHY_MR12_VR_CA_MASK
8238 #define DDR_PHY_MR12_VR_CA_DEFVAL                                                  0x0000004D
8239 #define DDR_PHY_MR12_VR_CA_SHIFT                                                   6
8240 #define DDR_PHY_MR12_VR_CA_MASK                                                    0x00000040U
8241
8242 /*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/
8243 #undef DDR_PHY_MR12_VREF_CA_DEFVAL
8244 #undef DDR_PHY_MR12_VREF_CA_SHIFT
8245 #undef DDR_PHY_MR12_VREF_CA_MASK
8246 #define DDR_PHY_MR12_VREF_CA_DEFVAL                                                0x0000004D
8247 #define DDR_PHY_MR12_VREF_CA_SHIFT                                                 0
8248 #define DDR_PHY_MR12_VREF_CA_MASK                                                  0x0000003FU
8249
8250 /*Reserved. Return zeroes on reads.*/
8251 #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL
8252 #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT
8253 #undef DDR_PHY_MR13_RESERVED_31_8_MASK
8254 #define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                                          0x00000000
8255 #define DDR_PHY_MR13_RESERVED_31_8_SHIFT                                           8
8256 #define DDR_PHY_MR13_RESERVED_31_8_MASK                                            0xFFFFFF00U
8257
8258 /*Frequency Set Point Operation Mode*/
8259 #undef DDR_PHY_MR13_FSPOP_DEFVAL
8260 #undef DDR_PHY_MR13_FSPOP_SHIFT
8261 #undef DDR_PHY_MR13_FSPOP_MASK
8262 #define DDR_PHY_MR13_FSPOP_DEFVAL                                                  0x00000000
8263 #define DDR_PHY_MR13_FSPOP_SHIFT                                                   7
8264 #define DDR_PHY_MR13_FSPOP_MASK                                                    0x00000080U
8265
8266 /*Frequency Set Point Write Enable*/
8267 #undef DDR_PHY_MR13_FSPWR_DEFVAL
8268 #undef DDR_PHY_MR13_FSPWR_SHIFT
8269 #undef DDR_PHY_MR13_FSPWR_MASK
8270 #define DDR_PHY_MR13_FSPWR_DEFVAL                                                  0x00000000
8271 #define DDR_PHY_MR13_FSPWR_SHIFT                                                   6
8272 #define DDR_PHY_MR13_FSPWR_MASK                                                    0x00000040U
8273
8274 /*Data Mask Enable*/
8275 #undef DDR_PHY_MR13_DMD_DEFVAL
8276 #undef DDR_PHY_MR13_DMD_SHIFT
8277 #undef DDR_PHY_MR13_DMD_MASK
8278 #define DDR_PHY_MR13_DMD_DEFVAL                                                    0x00000000
8279 #define DDR_PHY_MR13_DMD_SHIFT                                                     5
8280 #define DDR_PHY_MR13_DMD_MASK                                                      0x00000020U
8281
8282 /*Refresh Rate Option*/
8283 #undef DDR_PHY_MR13_RRO_DEFVAL
8284 #undef DDR_PHY_MR13_RRO_SHIFT
8285 #undef DDR_PHY_MR13_RRO_MASK
8286 #define DDR_PHY_MR13_RRO_DEFVAL                                                    0x00000000
8287 #define DDR_PHY_MR13_RRO_SHIFT                                                     4
8288 #define DDR_PHY_MR13_RRO_MASK                                                      0x00000010U
8289
8290 /*VREF Current Generator*/
8291 #undef DDR_PHY_MR13_VRCG_DEFVAL
8292 #undef DDR_PHY_MR13_VRCG_SHIFT
8293 #undef DDR_PHY_MR13_VRCG_MASK
8294 #define DDR_PHY_MR13_VRCG_DEFVAL                                                   0x00000000
8295 #define DDR_PHY_MR13_VRCG_SHIFT                                                    3
8296 #define DDR_PHY_MR13_VRCG_MASK                                                     0x00000008U
8297
8298 /*VREF Output*/
8299 #undef DDR_PHY_MR13_VRO_DEFVAL
8300 #undef DDR_PHY_MR13_VRO_SHIFT
8301 #undef DDR_PHY_MR13_VRO_MASK
8302 #define DDR_PHY_MR13_VRO_DEFVAL                                                    0x00000000
8303 #define DDR_PHY_MR13_VRO_SHIFT                                                     2
8304 #define DDR_PHY_MR13_VRO_MASK                                                      0x00000004U
8305
8306 /*Read Preamble Training Mode*/
8307 #undef DDR_PHY_MR13_RPT_DEFVAL
8308 #undef DDR_PHY_MR13_RPT_SHIFT
8309 #undef DDR_PHY_MR13_RPT_MASK
8310 #define DDR_PHY_MR13_RPT_DEFVAL                                                    0x00000000
8311 #define DDR_PHY_MR13_RPT_SHIFT                                                     1
8312 #define DDR_PHY_MR13_RPT_MASK                                                      0x00000002U
8313
8314 /*Command Bus Training*/
8315 #undef DDR_PHY_MR13_CBT_DEFVAL
8316 #undef DDR_PHY_MR13_CBT_SHIFT
8317 #undef DDR_PHY_MR13_CBT_MASK
8318 #define DDR_PHY_MR13_CBT_DEFVAL                                                    0x00000000
8319 #define DDR_PHY_MR13_CBT_SHIFT                                                     0
8320 #define DDR_PHY_MR13_CBT_MASK                                                      0x00000001U
8321
8322 /*Reserved. Return zeroes on reads.*/
8323 #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL
8324 #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT
8325 #undef DDR_PHY_MR14_RESERVED_31_8_MASK
8326 #define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                                          0x0000004D
8327 #define DDR_PHY_MR14_RESERVED_31_8_SHIFT                                           8
8328 #define DDR_PHY_MR14_RESERVED_31_8_MASK                                            0xFFFFFF00U
8329
8330 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8331 #undef DDR_PHY_MR14_RSVD_DEFVAL
8332 #undef DDR_PHY_MR14_RSVD_SHIFT
8333 #undef DDR_PHY_MR14_RSVD_MASK
8334 #define DDR_PHY_MR14_RSVD_DEFVAL                                                   0x0000004D
8335 #define DDR_PHY_MR14_RSVD_SHIFT                                                    7
8336 #define DDR_PHY_MR14_RSVD_MASK                                                     0x00000080U
8337
8338 /*VREFDQ Range Selects.*/
8339 #undef DDR_PHY_MR14_VR_DQ_DEFVAL
8340 #undef DDR_PHY_MR14_VR_DQ_SHIFT
8341 #undef DDR_PHY_MR14_VR_DQ_MASK
8342 #define DDR_PHY_MR14_VR_DQ_DEFVAL                                                  0x0000004D
8343 #define DDR_PHY_MR14_VR_DQ_SHIFT                                                   6
8344 #define DDR_PHY_MR14_VR_DQ_MASK                                                    0x00000040U
8345
8346 /*Reserved. Return zeroes on reads.*/
8347 #undef DDR_PHY_MR14_VREF_DQ_DEFVAL
8348 #undef DDR_PHY_MR14_VREF_DQ_SHIFT
8349 #undef DDR_PHY_MR14_VREF_DQ_MASK
8350 #define DDR_PHY_MR14_VREF_DQ_DEFVAL                                                0x0000004D
8351 #define DDR_PHY_MR14_VREF_DQ_SHIFT                                                 0
8352 #define DDR_PHY_MR14_VREF_DQ_MASK                                                  0x0000003FU
8353
8354 /*Reserved. Return zeroes on reads.*/
8355 #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL
8356 #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT
8357 #undef DDR_PHY_MR22_RESERVED_31_8_MASK
8358 #define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                                          0x00000000
8359 #define DDR_PHY_MR22_RESERVED_31_8_SHIFT                                           8
8360 #define DDR_PHY_MR22_RESERVED_31_8_MASK                                            0xFFFFFF00U
8361
8362 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8363 #undef DDR_PHY_MR22_RSVD_DEFVAL
8364 #undef DDR_PHY_MR22_RSVD_SHIFT
8365 #undef DDR_PHY_MR22_RSVD_MASK
8366 #define DDR_PHY_MR22_RSVD_DEFVAL                                                   0x00000000
8367 #define DDR_PHY_MR22_RSVD_SHIFT                                                    6
8368 #define DDR_PHY_MR22_RSVD_MASK                                                     0x000000C0U
8369
8370 /*CA ODT termination disable.*/
8371 #undef DDR_PHY_MR22_ODTD_CA_DEFVAL
8372 #undef DDR_PHY_MR22_ODTD_CA_SHIFT
8373 #undef DDR_PHY_MR22_ODTD_CA_MASK
8374 #define DDR_PHY_MR22_ODTD_CA_DEFVAL                                                0x00000000
8375 #define DDR_PHY_MR22_ODTD_CA_SHIFT                                                 5
8376 #define DDR_PHY_MR22_ODTD_CA_MASK                                                  0x00000020U
8377
8378 /*ODT CS override.*/
8379 #undef DDR_PHY_MR22_ODTE_CS_DEFVAL
8380 #undef DDR_PHY_MR22_ODTE_CS_SHIFT
8381 #undef DDR_PHY_MR22_ODTE_CS_MASK
8382 #define DDR_PHY_MR22_ODTE_CS_DEFVAL                                                0x00000000
8383 #define DDR_PHY_MR22_ODTE_CS_SHIFT                                                 4
8384 #define DDR_PHY_MR22_ODTE_CS_MASK                                                  0x00000010U
8385
8386 /*ODT CK override.*/
8387 #undef DDR_PHY_MR22_ODTE_CK_DEFVAL
8388 #undef DDR_PHY_MR22_ODTE_CK_SHIFT
8389 #undef DDR_PHY_MR22_ODTE_CK_MASK
8390 #define DDR_PHY_MR22_ODTE_CK_DEFVAL                                                0x00000000
8391 #define DDR_PHY_MR22_ODTE_CK_SHIFT                                                 3
8392 #define DDR_PHY_MR22_ODTE_CK_MASK                                                  0x00000008U
8393
8394 /*Controller ODT value for VOH calibration.*/
8395 #undef DDR_PHY_MR22_CODT_DEFVAL
8396 #undef DDR_PHY_MR22_CODT_SHIFT
8397 #undef DDR_PHY_MR22_CODT_MASK
8398 #define DDR_PHY_MR22_CODT_DEFVAL                                                   0x00000000
8399 #define DDR_PHY_MR22_CODT_SHIFT                                                    0
8400 #define DDR_PHY_MR22_CODT_MASK                                                     0x00000007U
8401
8402 /*Refresh During Training*/
8403 #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL
8404 #undef DDR_PHY_DTCR0_RFSHDT_SHIFT
8405 #undef DDR_PHY_DTCR0_RFSHDT_MASK
8406 #define DDR_PHY_DTCR0_RFSHDT_DEFVAL                                                0x800091C7
8407 #define DDR_PHY_DTCR0_RFSHDT_SHIFT                                                 28
8408 #define DDR_PHY_DTCR0_RFSHDT_MASK                                                  0xF0000000U
8409
8410 /*Reserved. Return zeroes on reads.*/
8411 #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL
8412 #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
8413 #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK
8414 #define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                                        0x800091C7
8415 #define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                                         26
8416 #define DDR_PHY_DTCR0_RESERVED_27_26_MASK                                          0x0C000000U
8417
8418 /*Data Training Debug Rank Select*/
8419 #undef DDR_PHY_DTCR0_DTDRS_DEFVAL
8420 #undef DDR_PHY_DTCR0_DTDRS_SHIFT
8421 #undef DDR_PHY_DTCR0_DTDRS_MASK
8422 #define DDR_PHY_DTCR0_DTDRS_DEFVAL                                                 0x800091C7
8423 #define DDR_PHY_DTCR0_DTDRS_SHIFT                                                  24
8424 #define DDR_PHY_DTCR0_DTDRS_MASK                                                   0x03000000U
8425
8426 /*Data Training with Early/Extended Gate*/
8427 #undef DDR_PHY_DTCR0_DTEXG_DEFVAL
8428 #undef DDR_PHY_DTCR0_DTEXG_SHIFT
8429 #undef DDR_PHY_DTCR0_DTEXG_MASK
8430 #define DDR_PHY_DTCR0_DTEXG_DEFVAL                                                 0x800091C7
8431 #define DDR_PHY_DTCR0_DTEXG_SHIFT                                                  23
8432 #define DDR_PHY_DTCR0_DTEXG_MASK                                                   0x00800000U
8433
8434 /*Data Training Extended Write DQS*/
8435 #undef DDR_PHY_DTCR0_DTEXD_DEFVAL
8436 #undef DDR_PHY_DTCR0_DTEXD_SHIFT
8437 #undef DDR_PHY_DTCR0_DTEXD_MASK
8438 #define DDR_PHY_DTCR0_DTEXD_DEFVAL                                                 0x800091C7
8439 #define DDR_PHY_DTCR0_DTEXD_SHIFT                                                  22
8440 #define DDR_PHY_DTCR0_DTEXD_MASK                                                   0x00400000U
8441
8442 /*Data Training Debug Step*/
8443 #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL
8444 #undef DDR_PHY_DTCR0_DTDSTP_SHIFT
8445 #undef DDR_PHY_DTCR0_DTDSTP_MASK
8446 #define DDR_PHY_DTCR0_DTDSTP_DEFVAL                                                0x800091C7
8447 #define DDR_PHY_DTCR0_DTDSTP_SHIFT                                                 21
8448 #define DDR_PHY_DTCR0_DTDSTP_MASK                                                  0x00200000U
8449
8450 /*Data Training Debug Enable*/
8451 #undef DDR_PHY_DTCR0_DTDEN_DEFVAL
8452 #undef DDR_PHY_DTCR0_DTDEN_SHIFT
8453 #undef DDR_PHY_DTCR0_DTDEN_MASK
8454 #define DDR_PHY_DTCR0_DTDEN_DEFVAL                                                 0x800091C7
8455 #define DDR_PHY_DTCR0_DTDEN_SHIFT                                                  20
8456 #define DDR_PHY_DTCR0_DTDEN_MASK                                                   0x00100000U
8457
8458 /*Data Training Debug Byte Select*/
8459 #undef DDR_PHY_DTCR0_DTDBS_DEFVAL
8460 #undef DDR_PHY_DTCR0_DTDBS_SHIFT
8461 #undef DDR_PHY_DTCR0_DTDBS_MASK
8462 #define DDR_PHY_DTCR0_DTDBS_DEFVAL                                                 0x800091C7
8463 #define DDR_PHY_DTCR0_DTDBS_SHIFT                                                  16
8464 #define DDR_PHY_DTCR0_DTDBS_MASK                                                   0x000F0000U
8465
8466 /*Data Training read DBI deskewing configuration*/
8467 #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL
8468 #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT
8469 #undef DDR_PHY_DTCR0_DTRDBITR_MASK
8470 #define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                                              0x800091C7
8471 #define DDR_PHY_DTCR0_DTRDBITR_SHIFT                                               14
8472 #define DDR_PHY_DTCR0_DTRDBITR_MASK                                                0x0000C000U
8473
8474 /*Reserved. Return zeroes on reads.*/
8475 #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL
8476 #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT
8477 #undef DDR_PHY_DTCR0_RESERVED_13_MASK
8478 #define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                                           0x800091C7
8479 #define DDR_PHY_DTCR0_RESERVED_13_SHIFT                                            13
8480 #define DDR_PHY_DTCR0_RESERVED_13_MASK                                             0x00002000U
8481
8482 /*Data Training Write Bit Deskew Data Mask*/
8483 #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL
8484 #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT
8485 #undef DDR_PHY_DTCR0_DTWBDDM_MASK
8486 #define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                                               0x800091C7
8487 #define DDR_PHY_DTCR0_DTWBDDM_SHIFT                                                12
8488 #define DDR_PHY_DTCR0_DTWBDDM_MASK                                                 0x00001000U
8489
8490 /*Refreshes Issued During Entry to Training*/
8491 #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL
8492 #undef DDR_PHY_DTCR0_RFSHEN_SHIFT
8493 #undef DDR_PHY_DTCR0_RFSHEN_MASK
8494 #define DDR_PHY_DTCR0_RFSHEN_DEFVAL                                                0x800091C7
8495 #define DDR_PHY_DTCR0_RFSHEN_SHIFT                                                 8
8496 #define DDR_PHY_DTCR0_RFSHEN_MASK                                                  0x00000F00U
8497
8498 /*Data Training Compare Data*/
8499 #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL
8500 #undef DDR_PHY_DTCR0_DTCMPD_SHIFT
8501 #undef DDR_PHY_DTCR0_DTCMPD_MASK
8502 #define DDR_PHY_DTCR0_DTCMPD_DEFVAL                                                0x800091C7
8503 #define DDR_PHY_DTCR0_DTCMPD_SHIFT                                                 7
8504 #define DDR_PHY_DTCR0_DTCMPD_MASK                                                  0x00000080U
8505
8506 /*Data Training Using MPR*/
8507 #undef DDR_PHY_DTCR0_DTMPR_DEFVAL
8508 #undef DDR_PHY_DTCR0_DTMPR_SHIFT
8509 #undef DDR_PHY_DTCR0_DTMPR_MASK
8510 #define DDR_PHY_DTCR0_DTMPR_DEFVAL                                                 0x800091C7
8511 #define DDR_PHY_DTCR0_DTMPR_SHIFT                                                  6
8512 #define DDR_PHY_DTCR0_DTMPR_MASK                                                   0x00000040U
8513
8514 /*Reserved. Return zeroes on reads.*/
8515 #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL
8516 #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
8517 #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK
8518 #define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                                          0x800091C7
8519 #define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                                           4
8520 #define DDR_PHY_DTCR0_RESERVED_5_4_MASK                                            0x00000030U
8521
8522 /*Data Training Repeat Number*/
8523 #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL
8524 #undef DDR_PHY_DTCR0_DTRPTN_SHIFT
8525 #undef DDR_PHY_DTCR0_DTRPTN_MASK
8526 #define DDR_PHY_DTCR0_DTRPTN_DEFVAL                                                0x800091C7
8527 #define DDR_PHY_DTCR0_DTRPTN_SHIFT                                                 0
8528 #define DDR_PHY_DTCR0_DTRPTN_MASK                                                  0x0000000FU
8529
8530 /*Rank Enable.*/
8531 #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL
8532 #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
8533 #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK
8534 #define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                                           0x00030237
8535 #define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                                            18
8536 #define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                                             0xFFFC0000U
8537
8538 /*Rank Enable.*/
8539 #undef DDR_PHY_DTCR1_RANKEN_DEFVAL
8540 #undef DDR_PHY_DTCR1_RANKEN_SHIFT
8541 #undef DDR_PHY_DTCR1_RANKEN_MASK
8542 #define DDR_PHY_DTCR1_RANKEN_DEFVAL                                                0x00030237
8543 #define DDR_PHY_DTCR1_RANKEN_SHIFT                                                 16
8544 #define DDR_PHY_DTCR1_RANKEN_MASK                                                  0x00030000U
8545
8546 /*Reserved. Return zeroes on reads.*/
8547 #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL
8548 #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
8549 #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK
8550 #define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                                        0x00030237
8551 #define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                                         14
8552 #define DDR_PHY_DTCR1_RESERVED_15_14_MASK                                          0x0000C000U
8553
8554 /*Data Training Rank*/
8555 #undef DDR_PHY_DTCR1_DTRANK_DEFVAL
8556 #undef DDR_PHY_DTCR1_DTRANK_SHIFT
8557 #undef DDR_PHY_DTCR1_DTRANK_MASK
8558 #define DDR_PHY_DTCR1_DTRANK_DEFVAL                                                0x00030237
8559 #define DDR_PHY_DTCR1_DTRANK_SHIFT                                                 12
8560 #define DDR_PHY_DTCR1_DTRANK_MASK                                                  0x00003000U
8561
8562 /*Reserved. Return zeroes on reads.*/
8563 #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL
8564 #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT
8565 #undef DDR_PHY_DTCR1_RESERVED_11_MASK
8566 #define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                                           0x00030237
8567 #define DDR_PHY_DTCR1_RESERVED_11_SHIFT                                            11
8568 #define DDR_PHY_DTCR1_RESERVED_11_MASK                                             0x00000800U
8569
8570 /*Read Leveling Gate Sampling Difference*/
8571 #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL
8572 #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
8573 #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK
8574 #define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                                            0x00030237
8575 #define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                                             8
8576 #define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                                              0x00000700U
8577
8578 /*Reserved. Return zeroes on reads.*/
8579 #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL
8580 #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT
8581 #undef DDR_PHY_DTCR1_RESERVED_7_MASK
8582 #define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                                            0x00030237
8583 #define DDR_PHY_DTCR1_RESERVED_7_SHIFT                                             7
8584 #define DDR_PHY_DTCR1_RESERVED_7_MASK                                              0x00000080U
8585
8586 /*Read Leveling Gate Shift*/
8587 #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL
8588 #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT
8589 #undef DDR_PHY_DTCR1_RDLVLGS_MASK
8590 #define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                                               0x00030237
8591 #define DDR_PHY_DTCR1_RDLVLGS_SHIFT                                                4
8592 #define DDR_PHY_DTCR1_RDLVLGS_MASK                                                 0x00000070U
8593
8594 /*Reserved. Return zeroes on reads.*/
8595 #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL
8596 #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT
8597 #undef DDR_PHY_DTCR1_RESERVED_3_MASK
8598 #define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                                            0x00030237
8599 #define DDR_PHY_DTCR1_RESERVED_3_SHIFT                                             3
8600 #define DDR_PHY_DTCR1_RESERVED_3_MASK                                              0x00000008U
8601
8602 /*Read Preamble Training enable*/
8603 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL
8604 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
8605 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK
8606 #define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                                           0x00030237
8607 #define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                                            2
8608 #define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                                             0x00000004U
8609
8610 /*Read Leveling Enable*/
8611 #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL
8612 #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT
8613 #undef DDR_PHY_DTCR1_RDLVLEN_MASK
8614 #define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                                               0x00030237
8615 #define DDR_PHY_DTCR1_RDLVLEN_SHIFT                                                1
8616 #define DDR_PHY_DTCR1_RDLVLEN_MASK                                                 0x00000002U
8617
8618 /*Basic Gate Training Enable*/
8619 #undef DDR_PHY_DTCR1_BSTEN_DEFVAL
8620 #undef DDR_PHY_DTCR1_BSTEN_SHIFT
8621 #undef DDR_PHY_DTCR1_BSTEN_MASK
8622 #define DDR_PHY_DTCR1_BSTEN_DEFVAL                                                 0x00030237
8623 #define DDR_PHY_DTCR1_BSTEN_SHIFT                                                  0
8624 #define DDR_PHY_DTCR1_BSTEN_MASK                                                   0x00000001U
8625
8626 /*Reserved. Return zeroes on reads.*/
8627 #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL
8628 #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT
8629 #undef DDR_PHY_CATR0_RESERVED_31_21_MASK
8630 #define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                                        0x00141054
8631 #define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                                         21
8632 #define DDR_PHY_CATR0_RESERVED_31_21_MASK                                          0xFFE00000U
8633
8634 /*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/
8635 #undef DDR_PHY_CATR0_CACD_DEFVAL
8636 #undef DDR_PHY_CATR0_CACD_SHIFT
8637 #undef DDR_PHY_CATR0_CACD_MASK
8638 #define DDR_PHY_CATR0_CACD_DEFVAL                                                  0x00141054
8639 #define DDR_PHY_CATR0_CACD_SHIFT                                                   16
8640 #define DDR_PHY_CATR0_CACD_MASK                                                    0x001F0000U
8641
8642 /*Reserved. Return zeroes on reads.*/
8643 #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL
8644 #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT
8645 #undef DDR_PHY_CATR0_RESERVED_15_13_MASK
8646 #define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                                        0x00141054
8647 #define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                                         13
8648 #define DDR_PHY_CATR0_RESERVED_15_13_MASK                                          0x0000E000U
8649
8650 /*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
8651                  been sent to the memory*/
8652 #undef DDR_PHY_CATR0_CAADR_DEFVAL
8653 #undef DDR_PHY_CATR0_CAADR_SHIFT
8654 #undef DDR_PHY_CATR0_CAADR_MASK
8655 #define DDR_PHY_CATR0_CAADR_DEFVAL                                                 0x00141054
8656 #define DDR_PHY_CATR0_CAADR_SHIFT                                                  8
8657 #define DDR_PHY_CATR0_CAADR_MASK                                                   0x00001F00U
8658
8659 /*CA_1 Response Byte Lane 1*/
8660 #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL
8661 #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT
8662 #undef DDR_PHY_CATR0_CA1BYTE1_MASK
8663 #define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                                              0x00141054
8664 #define DDR_PHY_CATR0_CA1BYTE1_SHIFT                                               4
8665 #define DDR_PHY_CATR0_CA1BYTE1_MASK                                                0x000000F0U
8666
8667 /*CA_1 Response Byte Lane 0*/
8668 #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL
8669 #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT
8670 #undef DDR_PHY_CATR0_CA1BYTE0_MASK
8671 #define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                                              0x00141054
8672 #define DDR_PHY_CATR0_CA1BYTE0_SHIFT                                               0
8673 #define DDR_PHY_CATR0_CA1BYTE0_MASK                                                0x0000000FU
8674
8675 /*Reserved. Return zeroes on reads.*/
8676 #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
8677 #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
8678 #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK
8679 #define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                                       0x00000005
8680 #define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                                        16
8681 #define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                                         0xFFFF0000U
8682
8683 /*Reserved. Return zeros on reads.*/
8684 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL
8685 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
8686 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK
8687 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                                       0x00000005
8688 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                                        4
8689 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                                         0x0000FFF0U
8690
8691 /*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/
8692 #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL
8693 #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
8694 #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK
8695 #define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                                            0x00000005
8696 #define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                                             0
8697 #define DDR_PHY_RIOCR5_ODTOEMODE_MASK                                              0x0000000FU
8698
8699 /*Address/Command Slew Rate (D3F I/O Only)*/
8700 #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL
8701 #undef DDR_PHY_ACIOCR0_ACSR_SHIFT
8702 #undef DDR_PHY_ACIOCR0_ACSR_MASK
8703 #define DDR_PHY_ACIOCR0_ACSR_DEFVAL                                                0x30000000
8704 #define DDR_PHY_ACIOCR0_ACSR_SHIFT                                                 30
8705 #define DDR_PHY_ACIOCR0_ACSR_MASK                                                  0xC0000000U
8706
8707 /*SDRAM Reset I/O Mode*/
8708 #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL
8709 #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT
8710 #undef DDR_PHY_ACIOCR0_RSTIOM_MASK
8711 #define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                                              0x30000000
8712 #define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                                               29
8713 #define DDR_PHY_ACIOCR0_RSTIOM_MASK                                                0x20000000U
8714
8715 /*SDRAM Reset Power Down Receiver*/
8716 #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL
8717 #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT
8718 #undef DDR_PHY_ACIOCR0_RSTPDR_MASK
8719 #define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                                              0x30000000
8720 #define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                                               28
8721 #define DDR_PHY_ACIOCR0_RSTPDR_MASK                                                0x10000000U
8722
8723 /*Reserved. Return zeroes on reads.*/
8724 #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL
8725 #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
8726 #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK
8727 #define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                                         0x30000000
8728 #define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                                          27
8729 #define DDR_PHY_ACIOCR0_RESERVED_27_MASK                                           0x08000000U
8730
8731 /*SDRAM Reset On-Die Termination*/
8732 #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL
8733 #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT
8734 #undef DDR_PHY_ACIOCR0_RSTODT_MASK
8735 #define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                                              0x30000000
8736 #define DDR_PHY_ACIOCR0_RSTODT_SHIFT                                               26
8737 #define DDR_PHY_ACIOCR0_RSTODT_MASK                                                0x04000000U
8738
8739 /*Reserved. Return zeroes on reads.*/
8740 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL
8741 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
8742 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK
8743 #define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                                      0x30000000
8744 #define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                                       10
8745 #define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                                        0x03FFFC00U
8746
8747 /*CK Duty Cycle Correction*/
8748 #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL
8749 #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT
8750 #undef DDR_PHY_ACIOCR0_CKDCC_MASK
8751 #define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                                               0x30000000
8752 #define DDR_PHY_ACIOCR0_CKDCC_SHIFT                                                6
8753 #define DDR_PHY_ACIOCR0_CKDCC_MASK                                                 0x000003C0U
8754
8755 /*AC Power Down Receiver Mode*/
8756 #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL
8757 #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
8758 #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK
8759 #define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                                           0x30000000
8760 #define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                                            4
8761 #define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                                             0x00000030U
8762
8763 /*AC On-die Termination Mode*/
8764 #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL
8765 #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
8766 #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK
8767 #define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                                           0x30000000
8768 #define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                                            2
8769 #define DDR_PHY_ACIOCR0_ACODTMODE_MASK                                             0x0000000CU
8770
8771 /*Reserved. Return zeroes on reads.*/
8772 #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL
8773 #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
8774 #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK
8775 #define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                                          0x30000000
8776 #define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                                           1
8777 #define DDR_PHY_ACIOCR0_RESERVED_1_MASK                                            0x00000002U
8778
8779 /*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/
8780 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL
8781 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
8782 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK
8783 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                                        0x30000000
8784 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                                         0
8785 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                                          0x00000001U
8786
8787 /*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/
8788 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL
8789 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
8790 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK
8791 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                                       0x00000000
8792 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                                        31
8793 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                                         0x80000000U
8794
8795 /*Clock gating for Output Enable D slices [0]*/
8796 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL
8797 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
8798 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK
8799 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                                        0x00000000
8800 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                                         30
8801 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                                          0x40000000U
8802
8803 /*Clock gating for Power Down Receiver D slices [0]*/
8804 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL
8805 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
8806 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK
8807 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                                       0x00000000
8808 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                                        29
8809 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                                         0x20000000U
8810
8811 /*Clock gating for Termination Enable D slices [0]*/
8812 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL
8813 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
8814 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK
8815 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                                        0x00000000
8816 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                                         28
8817 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                                          0x10000000U
8818
8819 /*Clock gating for CK# D slices [1:0]*/
8820 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL
8821 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
8822 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK
8823 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                                         0x00000000
8824 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                                          26
8825 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                                           0x0C000000U
8826
8827 /*Clock gating for CK D slices [1:0]*/
8828 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL
8829 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
8830 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK
8831 #define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                                          0x00000000
8832 #define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                                           24
8833 #define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                                            0x03000000U
8834
8835 /*Clock gating for AC D slices [23:0]*/
8836 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL
8837 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
8838 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK
8839 #define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                                          0x00000000
8840 #define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                                           0
8841 #define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                                            0x00FFFFFFU
8842
8843 /*SDRAM Parity Output Enable (OE) Mode Selection*/
8844 #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL
8845 #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
8846 #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK
8847 #define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                                           0x00000005
8848 #define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                                            30
8849 #define DDR_PHY_ACIOCR3_PAROEMODE_MASK                                             0xC0000000U
8850
8851 /*SDRAM Bank Group Output Enable (OE) Mode Selection*/
8852 #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL
8853 #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
8854 #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK
8855 #define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                                            0x00000005
8856 #define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                                             26
8857 #define DDR_PHY_ACIOCR3_BGOEMODE_MASK                                              0x3C000000U
8858
8859 /*SDRAM Bank Address Output Enable (OE) Mode Selection*/
8860 #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL
8861 #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
8862 #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK
8863 #define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                                            0x00000005
8864 #define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                                             22
8865 #define DDR_PHY_ACIOCR3_BAOEMODE_MASK                                              0x03C00000U
8866
8867 /*SDRAM A[17] Output Enable (OE) Mode Selection*/
8868 #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL
8869 #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
8870 #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK
8871 #define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                                           0x00000005
8872 #define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                                            20
8873 #define DDR_PHY_ACIOCR3_A17OEMODE_MASK                                             0x00300000U
8874
8875 /*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/
8876 #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL
8877 #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
8878 #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK
8879 #define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                                           0x00000005
8880 #define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                                            18
8881 #define DDR_PHY_ACIOCR3_A16OEMODE_MASK                                             0x000C0000U
8882
8883 /*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/
8884 #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL
8885 #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
8886 #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK
8887 #define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                                           0x00000005
8888 #define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                                            16
8889 #define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                                             0x00030000U
8890
8891 /*Reserved. Return zeroes on reads.*/
8892 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL
8893 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
8894 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK
8895 #define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                                       0x00000005
8896 #define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                                        8
8897 #define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                                         0x0000FF00U
8898
8899 /*Reserved. Return zeros on reads.*/
8900 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL
8901 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
8902 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK
8903 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                                       0x00000005
8904 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                                        4
8905 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                                         0x000000F0U
8906
8907 /*SDRAM CK Output Enable (OE) Mode Selection.*/
8908 #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL
8909 #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
8910 #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK
8911 #define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                                            0x00000005
8912 #define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                                             0
8913 #define DDR_PHY_ACIOCR3_CKOEMODE_MASK                                              0x0000000FU
8914
8915 /*Clock gating for AC LB slices and loopback read valid slices*/
8916 #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL
8917 #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
8918 #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK
8919 #define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                                           0x00000000
8920 #define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                                            31
8921 #define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                                             0x80000000U
8922
8923 /*Clock gating for Output Enable D slices [1]*/
8924 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL
8925 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
8926 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK
8927 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                                        0x00000000
8928 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                                         30
8929 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                                          0x40000000U
8930
8931 /*Clock gating for Power Down Receiver D slices [1]*/
8932 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL
8933 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
8934 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK
8935 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                                       0x00000000
8936 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                                        29
8937 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                                         0x20000000U
8938
8939 /*Clock gating for Termination Enable D slices [1]*/
8940 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL
8941 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
8942 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK
8943 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                                        0x00000000
8944 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                                         28
8945 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                                          0x10000000U
8946
8947 /*Clock gating for CK# D slices [3:2]*/
8948 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL
8949 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
8950 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK
8951 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                                         0x00000000
8952 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                                          26
8953 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                                           0x0C000000U
8954
8955 /*Clock gating for CK D slices [3:2]*/
8956 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL
8957 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
8958 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK
8959 #define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                                          0x00000000
8960 #define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                                           24
8961 #define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                                            0x03000000U
8962
8963 /*Clock gating for AC D slices [47:24]*/
8964 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL
8965 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
8966 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK
8967 #define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                                          0x00000000
8968 #define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                                           0
8969 #define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                                            0x00FFFFFFU
8970
8971 /*Reserved. Return zeroes on reads.*/
8972 #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL
8973 #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
8974 #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK
8975 #define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                                       0x0F000000
8976 #define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                                        29
8977 #define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                                         0xE0000000U
8978
8979 /*Address/command lane VREF Pad Enable*/
8980 #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL
8981 #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT
8982 #undef DDR_PHY_IOVCR0_ACREFPEN_MASK
8983 #define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                                             0x0F000000
8984 #define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                                              28
8985 #define DDR_PHY_IOVCR0_ACREFPEN_MASK                                               0x10000000U
8986
8987 /*Address/command lane Internal VREF Enable*/
8988 #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL
8989 #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT
8990 #undef DDR_PHY_IOVCR0_ACREFEEN_MASK
8991 #define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                                             0x0F000000
8992 #define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                                              26
8993 #define DDR_PHY_IOVCR0_ACREFEEN_MASK                                               0x0C000000U
8994
8995 /*Address/command lane Single-End VREF Enable*/
8996 #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL
8997 #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT
8998 #undef DDR_PHY_IOVCR0_ACREFSEN_MASK
8999 #define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                                             0x0F000000
9000 #define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                                              25
9001 #define DDR_PHY_IOVCR0_ACREFSEN_MASK                                               0x02000000U
9002
9003 /*Address/command lane Internal VREF Enable*/
9004 #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL
9005 #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT
9006 #undef DDR_PHY_IOVCR0_ACREFIEN_MASK
9007 #define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                                             0x0F000000
9008 #define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                                              24
9009 #define DDR_PHY_IOVCR0_ACREFIEN_MASK                                               0x01000000U
9010
9011 /*External VREF generato REFSEL range select*/
9012 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL
9013 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
9014 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK
9015 #define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                                       0x0F000000
9016 #define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                                        23
9017 #define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                                         0x00800000U
9018
9019 /*Address/command lane External VREF Select*/
9020 #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL
9021 #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT
9022 #undef DDR_PHY_IOVCR0_ACREFESEL_MASK
9023 #define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                                            0x0F000000
9024 #define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                                             16
9025 #define DDR_PHY_IOVCR0_ACREFESEL_MASK                                              0x007F0000U
9026
9027 /*Single ended VREF generator REFSEL range select*/
9028 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL
9029 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
9030 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK
9031 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                                       0x0F000000
9032 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                                        15
9033 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                                         0x00008000U
9034
9035 /*Address/command lane Single-End VREF Select*/
9036 #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL
9037 #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
9038 #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK
9039 #define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                                            0x0F000000
9040 #define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                                             8
9041 #define DDR_PHY_IOVCR0_ACREFSSEL_MASK                                              0x00007F00U
9042
9043 /*Internal VREF generator REFSEL ragne select*/
9044 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL
9045 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
9046 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK
9047 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                                      0x0F000000
9048 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                                       7
9049 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                                        0x00000080U
9050
9051 /*REFSEL Control for internal AC IOs*/
9052 #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL
9053 #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
9054 #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK
9055 #define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                                           0x0F000000
9056 #define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                                            0
9057 #define DDR_PHY_IOVCR0_ACVREFISEL_MASK                                             0x0000007FU
9058
9059 /*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/
9060 #undef DDR_PHY_VTCR0_TVREF_DEFVAL
9061 #undef DDR_PHY_VTCR0_TVREF_SHIFT
9062 #undef DDR_PHY_VTCR0_TVREF_MASK
9063 #define DDR_PHY_VTCR0_TVREF_DEFVAL                                                 0x70032019
9064 #define DDR_PHY_VTCR0_TVREF_SHIFT                                                  29
9065 #define DDR_PHY_VTCR0_TVREF_MASK                                                   0xE0000000U
9066
9067 /*DRM DQ VREF training Enable*/
9068 #undef DDR_PHY_VTCR0_DVEN_DEFVAL
9069 #undef DDR_PHY_VTCR0_DVEN_SHIFT
9070 #undef DDR_PHY_VTCR0_DVEN_MASK
9071 #define DDR_PHY_VTCR0_DVEN_DEFVAL                                                  0x70032019
9072 #define DDR_PHY_VTCR0_DVEN_SHIFT                                                   28
9073 #define DDR_PHY_VTCR0_DVEN_MASK                                                    0x10000000U
9074
9075 /*Per Device Addressability Enable*/
9076 #undef DDR_PHY_VTCR0_PDAEN_DEFVAL
9077 #undef DDR_PHY_VTCR0_PDAEN_SHIFT
9078 #undef DDR_PHY_VTCR0_PDAEN_MASK
9079 #define DDR_PHY_VTCR0_PDAEN_DEFVAL                                                 0x70032019
9080 #define DDR_PHY_VTCR0_PDAEN_SHIFT                                                  27
9081 #define DDR_PHY_VTCR0_PDAEN_MASK                                                   0x08000000U
9082
9083 /*Reserved. Returns zeroes on reads.*/
9084 #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL
9085 #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT
9086 #undef DDR_PHY_VTCR0_RESERVED_26_MASK
9087 #define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                                           0x70032019
9088 #define DDR_PHY_VTCR0_RESERVED_26_SHIFT                                            26
9089 #define DDR_PHY_VTCR0_RESERVED_26_MASK                                             0x04000000U
9090
9091 /*VREF Word Count*/
9092 #undef DDR_PHY_VTCR0_VWCR_DEFVAL
9093 #undef DDR_PHY_VTCR0_VWCR_SHIFT
9094 #undef DDR_PHY_VTCR0_VWCR_MASK
9095 #define DDR_PHY_VTCR0_VWCR_DEFVAL                                                  0x70032019
9096 #define DDR_PHY_VTCR0_VWCR_SHIFT                                                   22
9097 #define DDR_PHY_VTCR0_VWCR_MASK                                                    0x03C00000U
9098
9099 /*DRAM DQ VREF step size used during DRAM VREF training*/
9100 #undef DDR_PHY_VTCR0_DVSS_DEFVAL
9101 #undef DDR_PHY_VTCR0_DVSS_SHIFT
9102 #undef DDR_PHY_VTCR0_DVSS_MASK
9103 #define DDR_PHY_VTCR0_DVSS_DEFVAL                                                  0x70032019
9104 #define DDR_PHY_VTCR0_DVSS_SHIFT                                                   18
9105 #define DDR_PHY_VTCR0_DVSS_MASK                                                    0x003C0000U
9106
9107 /*Maximum VREF limit value used during DRAM VREF training*/
9108 #undef DDR_PHY_VTCR0_DVMAX_DEFVAL
9109 #undef DDR_PHY_VTCR0_DVMAX_SHIFT
9110 #undef DDR_PHY_VTCR0_DVMAX_MASK
9111 #define DDR_PHY_VTCR0_DVMAX_DEFVAL                                                 0x70032019
9112 #define DDR_PHY_VTCR0_DVMAX_SHIFT                                                  12
9113 #define DDR_PHY_VTCR0_DVMAX_MASK                                                   0x0003F000U
9114
9115 /*Minimum VREF limit value used during DRAM VREF training*/
9116 #undef DDR_PHY_VTCR0_DVMIN_DEFVAL
9117 #undef DDR_PHY_VTCR0_DVMIN_SHIFT
9118 #undef DDR_PHY_VTCR0_DVMIN_MASK
9119 #define DDR_PHY_VTCR0_DVMIN_DEFVAL                                                 0x70032019
9120 #define DDR_PHY_VTCR0_DVMIN_SHIFT                                                  6
9121 #define DDR_PHY_VTCR0_DVMIN_MASK                                                   0x00000FC0U
9122
9123 /*Initial DRAM DQ VREF value used during DRAM VREF training*/
9124 #undef DDR_PHY_VTCR0_DVINIT_DEFVAL
9125 #undef DDR_PHY_VTCR0_DVINIT_SHIFT
9126 #undef DDR_PHY_VTCR0_DVINIT_MASK
9127 #define DDR_PHY_VTCR0_DVINIT_DEFVAL                                                0x70032019
9128 #define DDR_PHY_VTCR0_DVINIT_SHIFT                                                 0
9129 #define DDR_PHY_VTCR0_DVINIT_MASK                                                  0x0000003FU
9130
9131 /*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/
9132 #undef DDR_PHY_VTCR1_HVSS_DEFVAL
9133 #undef DDR_PHY_VTCR1_HVSS_SHIFT
9134 #undef DDR_PHY_VTCR1_HVSS_MASK
9135 #define DDR_PHY_VTCR1_HVSS_DEFVAL                                                  0x07F00072
9136 #define DDR_PHY_VTCR1_HVSS_SHIFT                                                   28
9137 #define DDR_PHY_VTCR1_HVSS_MASK                                                    0xF0000000U
9138
9139 /*Reserved. Returns zeroes on reads.*/
9140 #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL
9141 #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT
9142 #undef DDR_PHY_VTCR1_RESERVED_27_MASK
9143 #define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                                           0x07F00072
9144 #define DDR_PHY_VTCR1_RESERVED_27_SHIFT                                            27
9145 #define DDR_PHY_VTCR1_RESERVED_27_MASK                                             0x08000000U
9146
9147 /*Maximum VREF limit value used during DRAM VREF training.*/
9148 #undef DDR_PHY_VTCR1_HVMAX_DEFVAL
9149 #undef DDR_PHY_VTCR1_HVMAX_SHIFT
9150 #undef DDR_PHY_VTCR1_HVMAX_MASK
9151 #define DDR_PHY_VTCR1_HVMAX_DEFVAL                                                 0x07F00072
9152 #define DDR_PHY_VTCR1_HVMAX_SHIFT                                                  20
9153 #define DDR_PHY_VTCR1_HVMAX_MASK                                                   0x07F00000U
9154
9155 /*Reserved. Returns zeroes on reads.*/
9156 #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL
9157 #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT
9158 #undef DDR_PHY_VTCR1_RESERVED_19_MASK
9159 #define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                                           0x07F00072
9160 #define DDR_PHY_VTCR1_RESERVED_19_SHIFT                                            19
9161 #define DDR_PHY_VTCR1_RESERVED_19_MASK                                             0x00080000U
9162
9163 /*Minimum VREF limit value used during DRAM VREF training.*/
9164 #undef DDR_PHY_VTCR1_HVMIN_DEFVAL
9165 #undef DDR_PHY_VTCR1_HVMIN_SHIFT
9166 #undef DDR_PHY_VTCR1_HVMIN_MASK
9167 #define DDR_PHY_VTCR1_HVMIN_DEFVAL                                                 0x07F00072
9168 #define DDR_PHY_VTCR1_HVMIN_SHIFT                                                  12
9169 #define DDR_PHY_VTCR1_HVMIN_MASK                                                   0x0007F000U
9170
9171 /*Reserved. Returns zeroes on reads.*/
9172 #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL
9173 #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT
9174 #undef DDR_PHY_VTCR1_RESERVED_11_MASK
9175 #define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                                           0x07F00072
9176 #define DDR_PHY_VTCR1_RESERVED_11_SHIFT                                            11
9177 #define DDR_PHY_VTCR1_RESERVED_11_MASK                                             0x00000800U
9178
9179 /*Static Host Vref Rank Value*/
9180 #undef DDR_PHY_VTCR1_SHRNK_DEFVAL
9181 #undef DDR_PHY_VTCR1_SHRNK_SHIFT
9182 #undef DDR_PHY_VTCR1_SHRNK_MASK
9183 #define DDR_PHY_VTCR1_SHRNK_DEFVAL                                                 0x07F00072
9184 #define DDR_PHY_VTCR1_SHRNK_SHIFT                                                  9
9185 #define DDR_PHY_VTCR1_SHRNK_MASK                                                   0x00000600U
9186
9187 /*Static Host Vref Rank Enable*/
9188 #undef DDR_PHY_VTCR1_SHREN_DEFVAL
9189 #undef DDR_PHY_VTCR1_SHREN_SHIFT
9190 #undef DDR_PHY_VTCR1_SHREN_MASK
9191 #define DDR_PHY_VTCR1_SHREN_DEFVAL                                                 0x07F00072
9192 #define DDR_PHY_VTCR1_SHREN_SHIFT                                                  8
9193 #define DDR_PHY_VTCR1_SHREN_MASK                                                   0x00000100U
9194
9195 /*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/
9196 #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL
9197 #undef DDR_PHY_VTCR1_TVREFIO_SHIFT
9198 #undef DDR_PHY_VTCR1_TVREFIO_MASK
9199 #define DDR_PHY_VTCR1_TVREFIO_DEFVAL                                               0x07F00072
9200 #define DDR_PHY_VTCR1_TVREFIO_SHIFT                                                5
9201 #define DDR_PHY_VTCR1_TVREFIO_MASK                                                 0x000000E0U
9202
9203 /*Eye LCDL Offset value for VREF training*/
9204 #undef DDR_PHY_VTCR1_EOFF_DEFVAL
9205 #undef DDR_PHY_VTCR1_EOFF_SHIFT
9206 #undef DDR_PHY_VTCR1_EOFF_MASK
9207 #define DDR_PHY_VTCR1_EOFF_DEFVAL                                                  0x07F00072
9208 #define DDR_PHY_VTCR1_EOFF_SHIFT                                                   3
9209 #define DDR_PHY_VTCR1_EOFF_MASK                                                    0x00000018U
9210
9211 /*Number of LCDL Eye points for which VREF training is repeated*/
9212 #undef DDR_PHY_VTCR1_ENUM_DEFVAL
9213 #undef DDR_PHY_VTCR1_ENUM_SHIFT
9214 #undef DDR_PHY_VTCR1_ENUM_MASK
9215 #define DDR_PHY_VTCR1_ENUM_DEFVAL                                                  0x07F00072
9216 #define DDR_PHY_VTCR1_ENUM_SHIFT                                                   2
9217 #define DDR_PHY_VTCR1_ENUM_MASK                                                    0x00000004U
9218
9219 /*HOST (IO) internal VREF training Enable*/
9220 #undef DDR_PHY_VTCR1_HVEN_DEFVAL
9221 #undef DDR_PHY_VTCR1_HVEN_SHIFT
9222 #undef DDR_PHY_VTCR1_HVEN_MASK
9223 #define DDR_PHY_VTCR1_HVEN_DEFVAL                                                  0x07F00072
9224 #define DDR_PHY_VTCR1_HVEN_SHIFT                                                   1
9225 #define DDR_PHY_VTCR1_HVEN_MASK                                                    0x00000002U
9226
9227 /*Host IO Type Control*/
9228 #undef DDR_PHY_VTCR1_HVIO_DEFVAL
9229 #undef DDR_PHY_VTCR1_HVIO_SHIFT
9230 #undef DDR_PHY_VTCR1_HVIO_MASK
9231 #define DDR_PHY_VTCR1_HVIO_DEFVAL                                                  0x07F00072
9232 #define DDR_PHY_VTCR1_HVIO_SHIFT                                                   0
9233 #define DDR_PHY_VTCR1_HVIO_MASK                                                    0x00000001U
9234
9235 /*Reserved. Return zeroes on reads.*/
9236 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
9237 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
9238 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK
9239 #define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                                      0x00000000
9240 #define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                                       30
9241 #define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                                        0xC0000000U
9242
9243 /*Delay select for the BDL on Address A[3].*/
9244 #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL
9245 #undef DDR_PHY_ACBDLR6_A03BD_SHIFT
9246 #undef DDR_PHY_ACBDLR6_A03BD_MASK
9247 #define DDR_PHY_ACBDLR6_A03BD_DEFVAL                                               0x00000000
9248 #define DDR_PHY_ACBDLR6_A03BD_SHIFT                                                24
9249 #define DDR_PHY_ACBDLR6_A03BD_MASK                                                 0x3F000000U
9250
9251 /*Reserved. Return zeroes on reads.*/
9252 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL
9253 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
9254 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK
9255 #define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                                      0x00000000
9256 #define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                                       22
9257 #define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                                        0x00C00000U
9258
9259 /*Delay select for the BDL on Address A[2].*/
9260 #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL
9261 #undef DDR_PHY_ACBDLR6_A02BD_SHIFT
9262 #undef DDR_PHY_ACBDLR6_A02BD_MASK
9263 #define DDR_PHY_ACBDLR6_A02BD_DEFVAL                                               0x00000000
9264 #define DDR_PHY_ACBDLR6_A02BD_SHIFT                                                16
9265 #define DDR_PHY_ACBDLR6_A02BD_MASK                                                 0x003F0000U
9266
9267 /*Reserved. Return zeroes on reads.*/
9268 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL
9269 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
9270 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK
9271 #define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                                      0x00000000
9272 #define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                                       14
9273 #define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                                        0x0000C000U
9274
9275 /*Delay select for the BDL on Address A[1].*/
9276 #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL
9277 #undef DDR_PHY_ACBDLR6_A01BD_SHIFT
9278 #undef DDR_PHY_ACBDLR6_A01BD_MASK
9279 #define DDR_PHY_ACBDLR6_A01BD_DEFVAL                                               0x00000000
9280 #define DDR_PHY_ACBDLR6_A01BD_SHIFT                                                8
9281 #define DDR_PHY_ACBDLR6_A01BD_MASK                                                 0x00003F00U
9282
9283 /*Reserved. Return zeroes on reads.*/
9284 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL
9285 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
9286 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK
9287 #define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                                        0x00000000
9288 #define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                                         6
9289 #define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                                          0x000000C0U
9290
9291 /*Delay select for the BDL on Address A[0].*/
9292 #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL
9293 #undef DDR_PHY_ACBDLR6_A00BD_SHIFT
9294 #undef DDR_PHY_ACBDLR6_A00BD_MASK
9295 #define DDR_PHY_ACBDLR6_A00BD_DEFVAL                                               0x00000000
9296 #define DDR_PHY_ACBDLR6_A00BD_SHIFT                                                0
9297 #define DDR_PHY_ACBDLR6_A00BD_MASK                                                 0x0000003FU
9298
9299 /*Reserved. Return zeroes on reads.*/
9300 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL
9301 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
9302 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK
9303 #define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                                      0x00000000
9304 #define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                                       30
9305 #define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                                        0xC0000000U
9306
9307 /*Delay select for the BDL on Address A[7].*/
9308 #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL
9309 #undef DDR_PHY_ACBDLR7_A07BD_SHIFT
9310 #undef DDR_PHY_ACBDLR7_A07BD_MASK
9311 #define DDR_PHY_ACBDLR7_A07BD_DEFVAL                                               0x00000000
9312 #define DDR_PHY_ACBDLR7_A07BD_SHIFT                                                24
9313 #define DDR_PHY_ACBDLR7_A07BD_MASK                                                 0x3F000000U
9314
9315 /*Reserved. Return zeroes on reads.*/
9316 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL
9317 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
9318 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK
9319 #define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                                      0x00000000
9320 #define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                                       22
9321 #define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                                        0x00C00000U
9322
9323 /*Delay select for the BDL on Address A[6].*/
9324 #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL
9325 #undef DDR_PHY_ACBDLR7_A06BD_SHIFT
9326 #undef DDR_PHY_ACBDLR7_A06BD_MASK
9327 #define DDR_PHY_ACBDLR7_A06BD_DEFVAL                                               0x00000000
9328 #define DDR_PHY_ACBDLR7_A06BD_SHIFT                                                16
9329 #define DDR_PHY_ACBDLR7_A06BD_MASK                                                 0x003F0000U
9330
9331 /*Reserved. Return zeroes on reads.*/
9332 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL
9333 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
9334 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK
9335 #define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                                      0x00000000
9336 #define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                                       14
9337 #define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                                        0x0000C000U
9338
9339 /*Delay select for the BDL on Address A[5].*/
9340 #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL
9341 #undef DDR_PHY_ACBDLR7_A05BD_SHIFT
9342 #undef DDR_PHY_ACBDLR7_A05BD_MASK
9343 #define DDR_PHY_ACBDLR7_A05BD_DEFVAL                                               0x00000000
9344 #define DDR_PHY_ACBDLR7_A05BD_SHIFT                                                8
9345 #define DDR_PHY_ACBDLR7_A05BD_MASK                                                 0x00003F00U
9346
9347 /*Reserved. Return zeroes on reads.*/
9348 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL
9349 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
9350 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK
9351 #define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                                        0x00000000
9352 #define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                                         6
9353 #define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                                          0x000000C0U
9354
9355 /*Delay select for the BDL on Address A[4].*/
9356 #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL
9357 #undef DDR_PHY_ACBDLR7_A04BD_SHIFT
9358 #undef DDR_PHY_ACBDLR7_A04BD_MASK
9359 #define DDR_PHY_ACBDLR7_A04BD_DEFVAL                                               0x00000000
9360 #define DDR_PHY_ACBDLR7_A04BD_SHIFT                                                0
9361 #define DDR_PHY_ACBDLR7_A04BD_MASK                                                 0x0000003FU
9362
9363 /*Reserved. Return zeroes on reads.*/
9364 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL
9365 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
9366 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK
9367 #define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                                      0x00000000
9368 #define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                                       30
9369 #define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                                        0xC0000000U
9370
9371 /*Delay select for the BDL on Address A[11].*/
9372 #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL
9373 #undef DDR_PHY_ACBDLR8_A11BD_SHIFT
9374 #undef DDR_PHY_ACBDLR8_A11BD_MASK
9375 #define DDR_PHY_ACBDLR8_A11BD_DEFVAL                                               0x00000000
9376 #define DDR_PHY_ACBDLR8_A11BD_SHIFT                                                24
9377 #define DDR_PHY_ACBDLR8_A11BD_MASK                                                 0x3F000000U
9378
9379 /*Reserved. Return zeroes on reads.*/
9380 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL
9381 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
9382 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK
9383 #define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                                      0x00000000
9384 #define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                                       22
9385 #define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                                        0x00C00000U
9386
9387 /*Delay select for the BDL on Address A[10].*/
9388 #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL
9389 #undef DDR_PHY_ACBDLR8_A10BD_SHIFT
9390 #undef DDR_PHY_ACBDLR8_A10BD_MASK
9391 #define DDR_PHY_ACBDLR8_A10BD_DEFVAL                                               0x00000000
9392 #define DDR_PHY_ACBDLR8_A10BD_SHIFT                                                16
9393 #define DDR_PHY_ACBDLR8_A10BD_MASK                                                 0x003F0000U
9394
9395 /*Reserved. Return zeroes on reads.*/
9396 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL
9397 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
9398 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK
9399 #define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                                      0x00000000
9400 #define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                                       14
9401 #define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                                        0x0000C000U
9402
9403 /*Delay select for the BDL on Address A[9].*/
9404 #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL
9405 #undef DDR_PHY_ACBDLR8_A09BD_SHIFT
9406 #undef DDR_PHY_ACBDLR8_A09BD_MASK
9407 #define DDR_PHY_ACBDLR8_A09BD_DEFVAL                                               0x00000000
9408 #define DDR_PHY_ACBDLR8_A09BD_SHIFT                                                8
9409 #define DDR_PHY_ACBDLR8_A09BD_MASK                                                 0x00003F00U
9410
9411 /*Reserved. Return zeroes on reads.*/
9412 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL
9413 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
9414 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK
9415 #define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                                        0x00000000
9416 #define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                                         6
9417 #define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                                          0x000000C0U
9418
9419 /*Delay select for the BDL on Address A[8].*/
9420 #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL
9421 #undef DDR_PHY_ACBDLR8_A08BD_SHIFT
9422 #undef DDR_PHY_ACBDLR8_A08BD_MASK
9423 #define DDR_PHY_ACBDLR8_A08BD_DEFVAL                                               0x00000000
9424 #define DDR_PHY_ACBDLR8_A08BD_SHIFT                                                0
9425 #define DDR_PHY_ACBDLR8_A08BD_MASK                                                 0x0000003FU
9426
9427 /*Reserved. Return zeroes on reads.*/
9428 #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
9429 #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
9430 #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK
9431 #define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                                         0x008A2858
9432 #define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                                          26
9433 #define DDR_PHY_ZQCR_RESERVED_31_26_MASK                                           0xFC000000U
9434
9435 /*ZQ VREF Range*/
9436 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL
9437 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
9438 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK
9439 #define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                                         0x008A2858
9440 #define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                                          25
9441 #define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                                           0x02000000U
9442
9443 /*Programmable Wait for Frequency B*/
9444 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL
9445 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
9446 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK
9447 #define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                                            0x008A2858
9448 #define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                                             19
9449 #define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                                              0x01F80000U
9450
9451 /*Programmable Wait for Frequency A*/
9452 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL
9453 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
9454 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK
9455 #define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                                            0x008A2858
9456 #define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                                             13
9457 #define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                                              0x0007E000U
9458
9459 /*ZQ VREF Pad Enable*/
9460 #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL
9461 #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT
9462 #undef DDR_PHY_ZQCR_ZQREFPEN_MASK
9463 #define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                                               0x008A2858
9464 #define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                                                12
9465 #define DDR_PHY_ZQCR_ZQREFPEN_MASK                                                 0x00001000U
9466
9467 /*ZQ Internal VREF Enable*/
9468 #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL
9469 #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT
9470 #undef DDR_PHY_ZQCR_ZQREFIEN_MASK
9471 #define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                                               0x008A2858
9472 #define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                                                11
9473 #define DDR_PHY_ZQCR_ZQREFIEN_MASK                                                 0x00000800U
9474
9475 /*Choice of termination mode*/
9476 #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL
9477 #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT
9478 #undef DDR_PHY_ZQCR_ODT_MODE_MASK
9479 #define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                                               0x008A2858
9480 #define DDR_PHY_ZQCR_ODT_MODE_SHIFT                                                9
9481 #define DDR_PHY_ZQCR_ODT_MODE_MASK                                                 0x00000600U
9482
9483 /*Force ZCAL VT update*/
9484 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL
9485 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
9486 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK
9487 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL                                   0x008A2858
9488 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                                    8
9489 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                                     0x00000100U
9490
9491 /*IO VT Drift Limit*/
9492 #undef DDR_PHY_ZQCR_IODLMT_DEFVAL
9493 #undef DDR_PHY_ZQCR_IODLMT_SHIFT
9494 #undef DDR_PHY_ZQCR_IODLMT_MASK
9495 #define DDR_PHY_ZQCR_IODLMT_DEFVAL                                                 0x008A2858
9496 #define DDR_PHY_ZQCR_IODLMT_SHIFT                                                  5
9497 #define DDR_PHY_ZQCR_IODLMT_MASK                                                   0x000000E0U
9498
9499 /*Averaging algorithm enable, if set, enables averaging algorithm*/
9500 #undef DDR_PHY_ZQCR_AVGEN_DEFVAL
9501 #undef DDR_PHY_ZQCR_AVGEN_SHIFT
9502 #undef DDR_PHY_ZQCR_AVGEN_MASK
9503 #define DDR_PHY_ZQCR_AVGEN_DEFVAL                                                  0x008A2858
9504 #define DDR_PHY_ZQCR_AVGEN_SHIFT                                                   4
9505 #define DDR_PHY_ZQCR_AVGEN_MASK                                                    0x00000010U
9506
9507 /*Maximum number of averaging rounds to be used by averaging algorithm*/
9508 #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL
9509 #undef DDR_PHY_ZQCR_AVGMAX_SHIFT
9510 #undef DDR_PHY_ZQCR_AVGMAX_MASK
9511 #define DDR_PHY_ZQCR_AVGMAX_DEFVAL                                                 0x008A2858
9512 #define DDR_PHY_ZQCR_AVGMAX_SHIFT                                                  2
9513 #define DDR_PHY_ZQCR_AVGMAX_MASK                                                   0x0000000CU
9514
9515 /*ZQ Calibration Type*/
9516 #undef DDR_PHY_ZQCR_ZCALT_DEFVAL
9517 #undef DDR_PHY_ZQCR_ZCALT_SHIFT
9518 #undef DDR_PHY_ZQCR_ZCALT_MASK
9519 #define DDR_PHY_ZQCR_ZCALT_DEFVAL                                                  0x008A2858
9520 #define DDR_PHY_ZQCR_ZCALT_SHIFT                                                   1
9521 #define DDR_PHY_ZQCR_ZCALT_MASK                                                    0x00000002U
9522
9523 /*ZQ Power Down*/
9524 #undef DDR_PHY_ZQCR_ZQPD_DEFVAL
9525 #undef DDR_PHY_ZQCR_ZQPD_SHIFT
9526 #undef DDR_PHY_ZQCR_ZQPD_MASK
9527 #define DDR_PHY_ZQCR_ZQPD_DEFVAL                                                   0x008A2858
9528 #define DDR_PHY_ZQCR_ZQPD_SHIFT                                                    0
9529 #define DDR_PHY_ZQCR_ZQPD_MASK                                                     0x00000001U
9530
9531 /*Pull-down drive strength ZCTRL over-ride enable*/
9532 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL
9533 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
9534 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK
9535 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
9536 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                                           31
9537 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
9538
9539 /*Pull-up drive strength ZCTRL over-ride enable*/
9540 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL
9541 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
9542 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK
9543 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
9544 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                                           30
9545 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
9546
9547 /*Pull-down termination ZCTRL over-ride enable*/
9548 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL
9549 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
9550 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK
9551 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
9552 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                                           29
9553 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
9554
9555 /*Pull-up termination ZCTRL over-ride enable*/
9556 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL
9557 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
9558 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK
9559 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
9560 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                                           28
9561 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
9562
9563 /*Calibration segment bypass*/
9564 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL
9565 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
9566 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK
9567 #define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                                              0x000077BB
9568 #define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                                               27
9569 #define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                                                0x08000000U
9570
9571 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9572 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL
9573 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
9574 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK
9575 #define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                                             0x000077BB
9576 #define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                                              25
9577 #define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                                               0x06000000U
9578
9579 /*Termination adjustment*/
9580 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL
9581 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
9582 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK
9583 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
9584 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                                            22
9585 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                                             0x01C00000U
9586
9587 /*Pulldown drive strength adjustment*/
9588 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL
9589 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
9590 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK
9591 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
9592 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                                         19
9593 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
9594
9595 /*Pullup drive strength adjustment*/
9596 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL
9597 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
9598 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK
9599 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
9600 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                                         16
9601 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
9602
9603 /*DRAM Impedance Divide Ratio*/
9604 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL
9605 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
9606 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK
9607 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
9608 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                                        12
9609 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
9610
9611 /*HOST Impedance Divide Ratio*/
9612 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL
9613 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
9614 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK
9615 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
9616 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                                        8
9617 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
9618
9619 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9620 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9621 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
9622 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK
9623 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
9624 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
9625 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
9626
9627 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9628 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9629 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
9630 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK
9631 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
9632 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
9633 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
9634
9635 /*Reserved. Return zeros on reads.*/
9636 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL
9637 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
9638 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK
9639 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                                       0x00000000
9640 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                                        26
9641 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                                         0xFC000000U
9642
9643 /*Override value for the pull-up output impedance*/
9644 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL
9645 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
9646 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK
9647 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                                    0x00000000
9648 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                                     16
9649 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                                      0x03FF0000U
9650
9651 /*Reserved. Return zeros on reads.*/
9652 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL
9653 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
9654 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK
9655 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                                       0x00000000
9656 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                                        10
9657 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                                         0x0000FC00U
9658
9659 /*Override value for the pull-down output impedance*/
9660 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL
9661 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
9662 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK
9663 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                                    0x00000000
9664 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                                     0
9665 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                                      0x000003FFU
9666
9667 /*Reserved. Return zeros on reads.*/
9668 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL
9669 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
9670 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK
9671 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                                       0x00000000
9672 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                                        26
9673 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                                         0xFC000000U
9674
9675 /*Override value for the pull-up termination*/
9676 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL
9677 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
9678 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK
9679 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                                    0x00000000
9680 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                                     16
9681 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                                      0x03FF0000U
9682
9683 /*Reserved. Return zeros on reads.*/
9684 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL
9685 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
9686 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK
9687 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                                       0x00000000
9688 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                                        10
9689 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                                         0x0000FC00U
9690
9691 /*Override value for the pull-down termination*/
9692 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL
9693 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
9694 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK
9695 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                                    0x00000000
9696 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                                     0
9697 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                                      0x000003FFU
9698
9699 /*Pull-down drive strength ZCTRL over-ride enable*/
9700 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL
9701 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
9702 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK
9703 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
9704 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                                           31
9705 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
9706
9707 /*Pull-up drive strength ZCTRL over-ride enable*/
9708 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL
9709 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
9710 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK
9711 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
9712 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                                           30
9713 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
9714
9715 /*Pull-down termination ZCTRL over-ride enable*/
9716 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL
9717 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
9718 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK
9719 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
9720 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                                           29
9721 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
9722
9723 /*Pull-up termination ZCTRL over-ride enable*/
9724 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL
9725 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
9726 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK
9727 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
9728 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                                           28
9729 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
9730
9731 /*Calibration segment bypass*/
9732 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL
9733 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
9734 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK
9735 #define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                                              0x000077BB
9736 #define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                                               27
9737 #define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                                                0x08000000U
9738
9739 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9740 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL
9741 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
9742 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK
9743 #define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                                             0x000077BB
9744 #define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                                              25
9745 #define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                                               0x06000000U
9746
9747 /*Termination adjustment*/
9748 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL
9749 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
9750 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK
9751 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
9752 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                                            22
9753 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                                             0x01C00000U
9754
9755 /*Pulldown drive strength adjustment*/
9756 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL
9757 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
9758 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK
9759 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
9760 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                                         19
9761 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
9762
9763 /*Pullup drive strength adjustment*/
9764 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL
9765 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
9766 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK
9767 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
9768 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                                         16
9769 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
9770
9771 /*DRAM Impedance Divide Ratio*/
9772 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL
9773 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
9774 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK
9775 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
9776 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                                        12
9777 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
9778
9779 /*HOST Impedance Divide Ratio*/
9780 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL
9781 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
9782 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK
9783 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
9784 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                                        8
9785 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
9786
9787 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9788 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9789 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
9790 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK
9791 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
9792 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
9793 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
9794
9795 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9796 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9797 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
9798 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK
9799 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
9800 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
9801 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
9802
9803 /*Calibration Bypass*/
9804 #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL
9805 #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT
9806 #undef DDR_PHY_DX0GCR0_CALBYP_MASK
9807 #define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                                              0x40200204
9808 #define DDR_PHY_DX0GCR0_CALBYP_SHIFT                                               31
9809 #define DDR_PHY_DX0GCR0_CALBYP_MASK                                                0x80000000U
9810
9811 /*Master Delay Line Enable*/
9812 #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL
9813 #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT
9814 #undef DDR_PHY_DX0GCR0_MDLEN_MASK
9815 #define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                                               0x40200204
9816 #define DDR_PHY_DX0GCR0_MDLEN_SHIFT                                                30
9817 #define DDR_PHY_DX0GCR0_MDLEN_MASK                                                 0x40000000U
9818
9819 /*Configurable ODT(TE) Phase Shift*/
9820 #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL
9821 #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
9822 #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK
9823 #define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                                            0x40200204
9824 #define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                                             28
9825 #define DDR_PHY_DX0GCR0_CODTSHFT_MASK                                              0x30000000U
9826
9827 /*DQS Duty Cycle Correction*/
9828 #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL
9829 #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT
9830 #undef DDR_PHY_DX0GCR0_DQSDCC_MASK
9831 #define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                                              0x40200204
9832 #define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                                               24
9833 #define DDR_PHY_DX0GCR0_DQSDCC_MASK                                                0x0F000000U
9834
9835 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
9836 #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL
9837 #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT
9838 #undef DDR_PHY_DX0GCR0_RDDLY_MASK
9839 #define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                                               0x40200204
9840 #define DDR_PHY_DX0GCR0_RDDLY_SHIFT                                                20
9841 #define DDR_PHY_DX0GCR0_RDDLY_MASK                                                 0x00F00000U
9842
9843 /*Reserved. Return zeroes on reads.*/
9844 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL
9845 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
9846 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK
9847 #define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
9848 #define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                                       14
9849 #define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                                        0x000FC000U
9850
9851 /*DQSNSE Power Down Receiver*/
9852 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL
9853 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
9854 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK
9855 #define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
9856 #define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                                            13
9857 #define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                                             0x00002000U
9858
9859 /*DQSSE Power Down Receiver*/
9860 #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL
9861 #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
9862 #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK
9863 #define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                                            0x40200204
9864 #define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                                             12
9865 #define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                                              0x00001000U
9866
9867 /*RTT On Additive Latency*/
9868 #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL
9869 #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT
9870 #undef DDR_PHY_DX0GCR0_RTTOAL_MASK
9871 #define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                                              0x40200204
9872 #define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                                               11
9873 #define DDR_PHY_DX0GCR0_RTTOAL_MASK                                                0x00000800U
9874
9875 /*RTT Output Hold*/
9876 #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL
9877 #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT
9878 #undef DDR_PHY_DX0GCR0_RTTOH_MASK
9879 #define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                                               0x40200204
9880 #define DDR_PHY_DX0GCR0_RTTOH_SHIFT                                                9
9881 #define DDR_PHY_DX0GCR0_RTTOH_MASK                                                 0x00000600U
9882
9883 /*Configurable PDR Phase Shift*/
9884 #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL
9885 #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
9886 #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK
9887 #define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                                            0x40200204
9888 #define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                                             7
9889 #define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                                              0x00000180U
9890
9891 /*DQSR Power Down*/
9892 #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL
9893 #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT
9894 #undef DDR_PHY_DX0GCR0_DQSRPD_MASK
9895 #define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                                              0x40200204
9896 #define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                                               6
9897 #define DDR_PHY_DX0GCR0_DQSRPD_MASK                                                0x00000040U
9898
9899 /*DQSG Power Down Receiver*/
9900 #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL
9901 #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
9902 #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK
9903 #define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                                             0x40200204
9904 #define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                                              5
9905 #define DDR_PHY_DX0GCR0_DQSGPDR_MASK                                               0x00000020U
9906
9907 /*Reserved. Return zeroes on reads.*/
9908 #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL
9909 #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
9910 #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK
9911 #define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                                          0x40200204
9912 #define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                                           4
9913 #define DDR_PHY_DX0GCR0_RESERVED_4_MASK                                            0x00000010U
9914
9915 /*DQSG On-Die Termination*/
9916 #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL
9917 #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT
9918 #undef DDR_PHY_DX0GCR0_DQSGODT_MASK
9919 #define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                                             0x40200204
9920 #define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                                              3
9921 #define DDR_PHY_DX0GCR0_DQSGODT_MASK                                               0x00000008U
9922
9923 /*DQSG Output Enable*/
9924 #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL
9925 #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT
9926 #undef DDR_PHY_DX0GCR0_DQSGOE_MASK
9927 #define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                                              0x40200204
9928 #define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                                               2
9929 #define DDR_PHY_DX0GCR0_DQSGOE_MASK                                                0x00000004U
9930
9931 /*Reserved. Return zeroes on reads.*/
9932 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL
9933 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
9934 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK
9935 #define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
9936 #define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                                         0
9937 #define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                                          0x00000003U
9938
9939 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
9940 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL
9941 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
9942 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK
9943 #define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
9944 #define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                                       29
9945 #define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                                        0xE0000000U
9946
9947 /*Byte Lane VREF Pad Enable*/
9948 #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL
9949 #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
9950 #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK
9951 #define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
9952 #define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                                             28
9953 #define DDR_PHY_DX0GCR4_DXREFPEN_MASK                                              0x10000000U
9954
9955 /*Byte Lane Internal VREF Enable*/
9956 #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL
9957 #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
9958 #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK
9959 #define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
9960 #define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                                             26
9961 #define DDR_PHY_DX0GCR4_DXREFEEN_MASK                                              0x0C000000U
9962
9963 /*Byte Lane Single-End VREF Enable*/
9964 #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL
9965 #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
9966 #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK
9967 #define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
9968 #define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                                             25
9969 #define DDR_PHY_DX0GCR4_DXREFSEN_MASK                                              0x02000000U
9970
9971 /*Reserved. Returns zeros on reads.*/
9972 #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL
9973 #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
9974 #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK
9975 #define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
9976 #define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                                          24
9977 #define DDR_PHY_DX0GCR4_RESERVED_24_MASK                                           0x01000000U
9978
9979 /*External VREF generator REFSEL range select*/
9980 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL
9981 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
9982 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK
9983 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
9984 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                                       23
9985 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                                        0x00800000U
9986
9987 /*Byte Lane External VREF Select*/
9988 #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL
9989 #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
9990 #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK
9991 #define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
9992 #define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                                            16
9993 #define DDR_PHY_DX0GCR4_DXREFESEL_MASK                                             0x007F0000U
9994
9995 /*Single ended VREF generator REFSEL range select*/
9996 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL
9997 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
9998 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK
9999 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
10000 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                                       15
10001 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
10002
10003 /*Byte Lane Single-End VREF Select*/
10004 #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL
10005 #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
10006 #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK
10007 #define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
10008 #define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                                            8
10009 #define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                                             0x00007F00U
10010
10011 /*Reserved. Returns zeros on reads.*/
10012 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL
10013 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
10014 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK
10015 #define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
10016 #define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                                         6
10017 #define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                                          0x000000C0U
10018
10019 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10020 #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL
10021 #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
10022 #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK
10023 #define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
10024 #define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                                             2
10025 #define DDR_PHY_DX0GCR4_DXREFIEN_MASK                                              0x0000003CU
10026
10027 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10028 #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL
10029 #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
10030 #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK
10031 #define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
10032 #define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                                            0
10033 #define DDR_PHY_DX0GCR4_DXREFIMON_MASK                                             0x00000003U
10034
10035 /*Reserved. Returns zeros on reads.*/
10036 #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL
10037 #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
10038 #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK
10039 #define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                                         0x09090909
10040 #define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                                          31
10041 #define DDR_PHY_DX0GCR5_RESERVED_31_MASK                                           0x80000000U
10042
10043 /*Byte Lane internal VREF Select for Rank 3*/
10044 #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL
10045 #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
10046 #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK
10047 #define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                                         0x09090909
10048 #define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                                          24
10049 #define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                                           0x7F000000U
10050
10051 /*Reserved. Returns zeros on reads.*/
10052 #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL
10053 #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
10054 #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK
10055 #define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                                         0x09090909
10056 #define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                                          23
10057 #define DDR_PHY_DX0GCR5_RESERVED_23_MASK                                           0x00800000U
10058
10059 /*Byte Lane internal VREF Select for Rank 2*/
10060 #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL
10061 #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
10062 #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK
10063 #define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                                         0x09090909
10064 #define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                                          16
10065 #define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                                           0x007F0000U
10066
10067 /*Reserved. Returns zeros on reads.*/
10068 #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL
10069 #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
10070 #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK
10071 #define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                                         0x09090909
10072 #define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                                          15
10073 #define DDR_PHY_DX0GCR5_RESERVED_15_MASK                                           0x00008000U
10074
10075 /*Byte Lane internal VREF Select for Rank 1*/
10076 #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL
10077 #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
10078 #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK
10079 #define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                                         0x09090909
10080 #define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                                          8
10081 #define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                                           0x00007F00U
10082
10083 /*Reserved. Returns zeros on reads.*/
10084 #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL
10085 #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
10086 #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK
10087 #define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                                          0x09090909
10088 #define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                                           7
10089 #define DDR_PHY_DX0GCR5_RESERVED_7_MASK                                            0x00000080U
10090
10091 /*Byte Lane internal VREF Select for Rank 0*/
10092 #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL
10093 #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
10094 #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK
10095 #define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                                         0x09090909
10096 #define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                                          0
10097 #define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                                           0x0000007FU
10098
10099 /*Reserved. Returns zeros on reads.*/
10100 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL
10101 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
10102 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK
10103 #define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
10104 #define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                                       30
10105 #define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                                        0xC0000000U
10106
10107 /*DRAM DQ VREF Select for Rank3*/
10108 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL
10109 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
10110 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK
10111 #define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
10112 #define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                                           24
10113 #define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                                            0x3F000000U
10114
10115 /*Reserved. Returns zeros on reads.*/
10116 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL
10117 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
10118 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK
10119 #define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
10120 #define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                                       22
10121 #define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                                        0x00C00000U
10122
10123 /*DRAM DQ VREF Select for Rank2*/
10124 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL
10125 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
10126 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK
10127 #define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
10128 #define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                                           16
10129 #define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                                            0x003F0000U
10130
10131 /*Reserved. Returns zeros on reads.*/
10132 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL
10133 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
10134 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK
10135 #define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
10136 #define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                                       14
10137 #define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                                        0x0000C000U
10138
10139 /*DRAM DQ VREF Select for Rank1*/
10140 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL
10141 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
10142 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK
10143 #define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
10144 #define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                                           8
10145 #define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                                            0x00003F00U
10146
10147 /*Reserved. Returns zeros on reads.*/
10148 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL
10149 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
10150 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK
10151 #define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
10152 #define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                                         6
10153 #define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                                          0x000000C0U
10154
10155 /*DRAM DQ VREF Select for Rank0*/
10156 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL
10157 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
10158 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK
10159 #define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
10160 #define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                                           0
10161 #define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                                            0x0000003FU
10162
10163 /*Reserved. Return zeroes on reads.*/
10164 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL
10165 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
10166 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK
10167 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
10168 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT                                     25
10169 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
10170
10171 /*Reserved. Caution, do not write to this register field.*/
10172 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL
10173 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
10174 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK
10175 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
10176 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT                                     16
10177 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
10178
10179 /*Reserved. Return zeroes on reads.*/
10180 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL
10181 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
10182 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK
10183 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
10184 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT                                      9
10185 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
10186
10187 /*Read DQS Gating Delay*/
10188 #undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL
10189 #undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
10190 #undef DDR_PHY_DX0LCDLR2_DQSGD_MASK
10191 #define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL                                             0x00000000
10192 #define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT                                              0
10193 #define DDR_PHY_DX0LCDLR2_DQSGD_MASK                                               0x000001FFU
10194
10195 /*Reserved. Return zeroes on reads.*/
10196 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL
10197 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
10198 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK
10199 #define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
10200 #define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT                                       27
10201 #define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK                                        0xF8000000U
10202
10203 /*DQ Write Path Latency Pipeline*/
10204 #undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL
10205 #undef DDR_PHY_DX0GTR0_WDQSL_SHIFT
10206 #undef DDR_PHY_DX0GTR0_WDQSL_MASK
10207 #define DDR_PHY_DX0GTR0_WDQSL_DEFVAL                                               0x00020000
10208 #define DDR_PHY_DX0GTR0_WDQSL_SHIFT                                                24
10209 #define DDR_PHY_DX0GTR0_WDQSL_MASK                                                 0x07000000U
10210
10211 /*Reserved. Caution, do not write to this register field.*/
10212 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL
10213 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
10214 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK
10215 #define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
10216 #define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT                                       20
10217 #define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK                                        0x00F00000U
10218
10219 /*Write Leveling System Latency*/
10220 #undef DDR_PHY_DX0GTR0_WLSL_DEFVAL
10221 #undef DDR_PHY_DX0GTR0_WLSL_SHIFT
10222 #undef DDR_PHY_DX0GTR0_WLSL_MASK
10223 #define DDR_PHY_DX0GTR0_WLSL_DEFVAL                                                0x00020000
10224 #define DDR_PHY_DX0GTR0_WLSL_SHIFT                                                 16
10225 #define DDR_PHY_DX0GTR0_WLSL_MASK                                                  0x000F0000U
10226
10227 /*Reserved. Return zeroes on reads.*/
10228 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL
10229 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
10230 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK
10231 #define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
10232 #define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT                                       13
10233 #define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK                                        0x0000E000U
10234
10235 /*Reserved. Caution, do not write to this register field.*/
10236 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL
10237 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
10238 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK
10239 #define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
10240 #define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT                                        8
10241 #define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK                                         0x00001F00U
10242
10243 /*Reserved. Return zeroes on reads.*/
10244 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL
10245 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
10246 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK
10247 #define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
10248 #define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT                                         5
10249 #define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK                                          0x000000E0U
10250
10251 /*DQS Gating System Latency*/
10252 #undef DDR_PHY_DX0GTR0_DGSL_DEFVAL
10253 #undef DDR_PHY_DX0GTR0_DGSL_SHIFT
10254 #undef DDR_PHY_DX0GTR0_DGSL_MASK
10255 #define DDR_PHY_DX0GTR0_DGSL_DEFVAL                                                0x00020000
10256 #define DDR_PHY_DX0GTR0_DGSL_SHIFT                                                 0
10257 #define DDR_PHY_DX0GTR0_DGSL_MASK                                                  0x0000001FU
10258
10259 /*Calibration Bypass*/
10260 #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL
10261 #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT
10262 #undef DDR_PHY_DX1GCR0_CALBYP_MASK
10263 #define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                                              0x40200204
10264 #define DDR_PHY_DX1GCR0_CALBYP_SHIFT                                               31
10265 #define DDR_PHY_DX1GCR0_CALBYP_MASK                                                0x80000000U
10266
10267 /*Master Delay Line Enable*/
10268 #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL
10269 #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT
10270 #undef DDR_PHY_DX1GCR0_MDLEN_MASK
10271 #define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                                               0x40200204
10272 #define DDR_PHY_DX1GCR0_MDLEN_SHIFT                                                30
10273 #define DDR_PHY_DX1GCR0_MDLEN_MASK                                                 0x40000000U
10274
10275 /*Configurable ODT(TE) Phase Shift*/
10276 #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL
10277 #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
10278 #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK
10279 #define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                                            0x40200204
10280 #define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                                             28
10281 #define DDR_PHY_DX1GCR0_CODTSHFT_MASK                                              0x30000000U
10282
10283 /*DQS Duty Cycle Correction*/
10284 #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL
10285 #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT
10286 #undef DDR_PHY_DX1GCR0_DQSDCC_MASK
10287 #define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                                              0x40200204
10288 #define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                                               24
10289 #define DDR_PHY_DX1GCR0_DQSDCC_MASK                                                0x0F000000U
10290
10291 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10292 #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL
10293 #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT
10294 #undef DDR_PHY_DX1GCR0_RDDLY_MASK
10295 #define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                                               0x40200204
10296 #define DDR_PHY_DX1GCR0_RDDLY_SHIFT                                                20
10297 #define DDR_PHY_DX1GCR0_RDDLY_MASK                                                 0x00F00000U
10298
10299 /*Reserved. Return zeroes on reads.*/
10300 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL
10301 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
10302 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK
10303 #define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
10304 #define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                                       14
10305 #define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                                        0x000FC000U
10306
10307 /*DQSNSE Power Down Receiver*/
10308 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL
10309 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
10310 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK
10311 #define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
10312 #define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                                            13
10313 #define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                                             0x00002000U
10314
10315 /*DQSSE Power Down Receiver*/
10316 #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL
10317 #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
10318 #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK
10319 #define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                                            0x40200204
10320 #define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                                             12
10321 #define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                                              0x00001000U
10322
10323 /*RTT On Additive Latency*/
10324 #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL
10325 #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT
10326 #undef DDR_PHY_DX1GCR0_RTTOAL_MASK
10327 #define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                                              0x40200204
10328 #define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                                               11
10329 #define DDR_PHY_DX1GCR0_RTTOAL_MASK                                                0x00000800U
10330
10331 /*RTT Output Hold*/
10332 #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL
10333 #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT
10334 #undef DDR_PHY_DX1GCR0_RTTOH_MASK
10335 #define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                                               0x40200204
10336 #define DDR_PHY_DX1GCR0_RTTOH_SHIFT                                                9
10337 #define DDR_PHY_DX1GCR0_RTTOH_MASK                                                 0x00000600U
10338
10339 /*Configurable PDR Phase Shift*/
10340 #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL
10341 #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
10342 #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK
10343 #define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                                            0x40200204
10344 #define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                                             7
10345 #define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                                              0x00000180U
10346
10347 /*DQSR Power Down*/
10348 #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL
10349 #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT
10350 #undef DDR_PHY_DX1GCR0_DQSRPD_MASK
10351 #define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                                              0x40200204
10352 #define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                                               6
10353 #define DDR_PHY_DX1GCR0_DQSRPD_MASK                                                0x00000040U
10354
10355 /*DQSG Power Down Receiver*/
10356 #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL
10357 #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
10358 #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK
10359 #define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                                             0x40200204
10360 #define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                                              5
10361 #define DDR_PHY_DX1GCR0_DQSGPDR_MASK                                               0x00000020U
10362
10363 /*Reserved. Return zeroes on reads.*/
10364 #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL
10365 #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
10366 #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK
10367 #define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                                          0x40200204
10368 #define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                                           4
10369 #define DDR_PHY_DX1GCR0_RESERVED_4_MASK                                            0x00000010U
10370
10371 /*DQSG On-Die Termination*/
10372 #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL
10373 #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT
10374 #undef DDR_PHY_DX1GCR0_DQSGODT_MASK
10375 #define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                                             0x40200204
10376 #define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                                              3
10377 #define DDR_PHY_DX1GCR0_DQSGODT_MASK                                               0x00000008U
10378
10379 /*DQSG Output Enable*/
10380 #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL
10381 #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT
10382 #undef DDR_PHY_DX1GCR0_DQSGOE_MASK
10383 #define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                                              0x40200204
10384 #define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                                               2
10385 #define DDR_PHY_DX1GCR0_DQSGOE_MASK                                                0x00000004U
10386
10387 /*Reserved. Return zeroes on reads.*/
10388 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL
10389 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
10390 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK
10391 #define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
10392 #define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                                         0
10393 #define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                                          0x00000003U
10394
10395 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10396 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL
10397 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
10398 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK
10399 #define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
10400 #define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                                       29
10401 #define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                                        0xE0000000U
10402
10403 /*Byte Lane VREF Pad Enable*/
10404 #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL
10405 #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
10406 #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK
10407 #define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
10408 #define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                                             28
10409 #define DDR_PHY_DX1GCR4_DXREFPEN_MASK                                              0x10000000U
10410
10411 /*Byte Lane Internal VREF Enable*/
10412 #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL
10413 #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
10414 #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK
10415 #define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
10416 #define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                                             26
10417 #define DDR_PHY_DX1GCR4_DXREFEEN_MASK                                              0x0C000000U
10418
10419 /*Byte Lane Single-End VREF Enable*/
10420 #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL
10421 #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
10422 #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK
10423 #define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
10424 #define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                                             25
10425 #define DDR_PHY_DX1GCR4_DXREFSEN_MASK                                              0x02000000U
10426
10427 /*Reserved. Returns zeros on reads.*/
10428 #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL
10429 #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
10430 #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK
10431 #define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
10432 #define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                                          24
10433 #define DDR_PHY_DX1GCR4_RESERVED_24_MASK                                           0x01000000U
10434
10435 /*External VREF generator REFSEL range select*/
10436 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL
10437 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
10438 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK
10439 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
10440 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                                       23
10441 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                                        0x00800000U
10442
10443 /*Byte Lane External VREF Select*/
10444 #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL
10445 #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
10446 #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK
10447 #define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
10448 #define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                                            16
10449 #define DDR_PHY_DX1GCR4_DXREFESEL_MASK                                             0x007F0000U
10450
10451 /*Single ended VREF generator REFSEL range select*/
10452 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL
10453 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
10454 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK
10455 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
10456 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                                       15
10457 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
10458
10459 /*Byte Lane Single-End VREF Select*/
10460 #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL
10461 #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
10462 #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK
10463 #define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
10464 #define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                                            8
10465 #define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                                             0x00007F00U
10466
10467 /*Reserved. Returns zeros on reads.*/
10468 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL
10469 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
10470 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK
10471 #define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
10472 #define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                                         6
10473 #define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                                          0x000000C0U
10474
10475 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10476 #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL
10477 #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
10478 #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK
10479 #define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
10480 #define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                                             2
10481 #define DDR_PHY_DX1GCR4_DXREFIEN_MASK                                              0x0000003CU
10482
10483 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10484 #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL
10485 #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
10486 #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK
10487 #define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
10488 #define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                                            0
10489 #define DDR_PHY_DX1GCR4_DXREFIMON_MASK                                             0x00000003U
10490
10491 /*Reserved. Returns zeros on reads.*/
10492 #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL
10493 #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
10494 #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK
10495 #define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                                         0x09090909
10496 #define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                                          31
10497 #define DDR_PHY_DX1GCR5_RESERVED_31_MASK                                           0x80000000U
10498
10499 /*Byte Lane internal VREF Select for Rank 3*/
10500 #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL
10501 #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
10502 #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK
10503 #define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                                         0x09090909
10504 #define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                                          24
10505 #define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                                           0x7F000000U
10506
10507 /*Reserved. Returns zeros on reads.*/
10508 #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL
10509 #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
10510 #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK
10511 #define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                                         0x09090909
10512 #define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                                          23
10513 #define DDR_PHY_DX1GCR5_RESERVED_23_MASK                                           0x00800000U
10514
10515 /*Byte Lane internal VREF Select for Rank 2*/
10516 #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL
10517 #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
10518 #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK
10519 #define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                                         0x09090909
10520 #define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                                          16
10521 #define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                                           0x007F0000U
10522
10523 /*Reserved. Returns zeros on reads.*/
10524 #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL
10525 #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
10526 #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK
10527 #define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                                         0x09090909
10528 #define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                                          15
10529 #define DDR_PHY_DX1GCR5_RESERVED_15_MASK                                           0x00008000U
10530
10531 /*Byte Lane internal VREF Select for Rank 1*/
10532 #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL
10533 #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
10534 #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK
10535 #define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                                         0x09090909
10536 #define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                                          8
10537 #define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                                           0x00007F00U
10538
10539 /*Reserved. Returns zeros on reads.*/
10540 #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL
10541 #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
10542 #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK
10543 #define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                                          0x09090909
10544 #define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                                           7
10545 #define DDR_PHY_DX1GCR5_RESERVED_7_MASK                                            0x00000080U
10546
10547 /*Byte Lane internal VREF Select for Rank 0*/
10548 #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL
10549 #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
10550 #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK
10551 #define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                                         0x09090909
10552 #define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                                          0
10553 #define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                                           0x0000007FU
10554
10555 /*Reserved. Returns zeros on reads.*/
10556 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL
10557 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
10558 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK
10559 #define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
10560 #define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                                       30
10561 #define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                                        0xC0000000U
10562
10563 /*DRAM DQ VREF Select for Rank3*/
10564 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL
10565 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
10566 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK
10567 #define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
10568 #define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                                           24
10569 #define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                                            0x3F000000U
10570
10571 /*Reserved. Returns zeros on reads.*/
10572 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL
10573 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
10574 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK
10575 #define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
10576 #define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                                       22
10577 #define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                                        0x00C00000U
10578
10579 /*DRAM DQ VREF Select for Rank2*/
10580 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL
10581 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
10582 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK
10583 #define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
10584 #define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                                           16
10585 #define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                                            0x003F0000U
10586
10587 /*Reserved. Returns zeros on reads.*/
10588 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL
10589 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
10590 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK
10591 #define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
10592 #define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                                       14
10593 #define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                                        0x0000C000U
10594
10595 /*DRAM DQ VREF Select for Rank1*/
10596 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL
10597 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
10598 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK
10599 #define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
10600 #define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                                           8
10601 #define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                                            0x00003F00U
10602
10603 /*Reserved. Returns zeros on reads.*/
10604 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL
10605 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
10606 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK
10607 #define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
10608 #define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                                         6
10609 #define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                                          0x000000C0U
10610
10611 /*DRAM DQ VREF Select for Rank0*/
10612 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL
10613 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
10614 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK
10615 #define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
10616 #define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                                           0
10617 #define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                                            0x0000003FU
10618
10619 /*Reserved. Return zeroes on reads.*/
10620 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL
10621 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
10622 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK
10623 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
10624 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT                                     25
10625 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
10626
10627 /*Reserved. Caution, do not write to this register field.*/
10628 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL
10629 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
10630 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK
10631 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
10632 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT                                     16
10633 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
10634
10635 /*Reserved. Return zeroes on reads.*/
10636 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL
10637 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
10638 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK
10639 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
10640 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT                                      9
10641 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
10642
10643 /*Read DQS Gating Delay*/
10644 #undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL
10645 #undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
10646 #undef DDR_PHY_DX1LCDLR2_DQSGD_MASK
10647 #define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL                                             0x00000000
10648 #define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT                                              0
10649 #define DDR_PHY_DX1LCDLR2_DQSGD_MASK                                               0x000001FFU
10650
10651 /*Reserved. Return zeroes on reads.*/
10652 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL
10653 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
10654 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK
10655 #define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
10656 #define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT                                       27
10657 #define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK                                        0xF8000000U
10658
10659 /*DQ Write Path Latency Pipeline*/
10660 #undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL
10661 #undef DDR_PHY_DX1GTR0_WDQSL_SHIFT
10662 #undef DDR_PHY_DX1GTR0_WDQSL_MASK
10663 #define DDR_PHY_DX1GTR0_WDQSL_DEFVAL                                               0x00020000
10664 #define DDR_PHY_DX1GTR0_WDQSL_SHIFT                                                24
10665 #define DDR_PHY_DX1GTR0_WDQSL_MASK                                                 0x07000000U
10666
10667 /*Reserved. Caution, do not write to this register field.*/
10668 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL
10669 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
10670 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK
10671 #define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
10672 #define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT                                       20
10673 #define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK                                        0x00F00000U
10674
10675 /*Write Leveling System Latency*/
10676 #undef DDR_PHY_DX1GTR0_WLSL_DEFVAL
10677 #undef DDR_PHY_DX1GTR0_WLSL_SHIFT
10678 #undef DDR_PHY_DX1GTR0_WLSL_MASK
10679 #define DDR_PHY_DX1GTR0_WLSL_DEFVAL                                                0x00020000
10680 #define DDR_PHY_DX1GTR0_WLSL_SHIFT                                                 16
10681 #define DDR_PHY_DX1GTR0_WLSL_MASK                                                  0x000F0000U
10682
10683 /*Reserved. Return zeroes on reads.*/
10684 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL
10685 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
10686 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK
10687 #define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
10688 #define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT                                       13
10689 #define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK                                        0x0000E000U
10690
10691 /*Reserved. Caution, do not write to this register field.*/
10692 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL
10693 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
10694 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK
10695 #define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
10696 #define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT                                        8
10697 #define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK                                         0x00001F00U
10698
10699 /*Reserved. Return zeroes on reads.*/
10700 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL
10701 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
10702 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK
10703 #define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
10704 #define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT                                         5
10705 #define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK                                          0x000000E0U
10706
10707 /*DQS Gating System Latency*/
10708 #undef DDR_PHY_DX1GTR0_DGSL_DEFVAL
10709 #undef DDR_PHY_DX1GTR0_DGSL_SHIFT
10710 #undef DDR_PHY_DX1GTR0_DGSL_MASK
10711 #define DDR_PHY_DX1GTR0_DGSL_DEFVAL                                                0x00020000
10712 #define DDR_PHY_DX1GTR0_DGSL_SHIFT                                                 0
10713 #define DDR_PHY_DX1GTR0_DGSL_MASK                                                  0x0000001FU
10714
10715 /*Calibration Bypass*/
10716 #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL
10717 #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT
10718 #undef DDR_PHY_DX2GCR0_CALBYP_MASK
10719 #define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                                              0x40200204
10720 #define DDR_PHY_DX2GCR0_CALBYP_SHIFT                                               31
10721 #define DDR_PHY_DX2GCR0_CALBYP_MASK                                                0x80000000U
10722
10723 /*Master Delay Line Enable*/
10724 #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL
10725 #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT
10726 #undef DDR_PHY_DX2GCR0_MDLEN_MASK
10727 #define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                                               0x40200204
10728 #define DDR_PHY_DX2GCR0_MDLEN_SHIFT                                                30
10729 #define DDR_PHY_DX2GCR0_MDLEN_MASK                                                 0x40000000U
10730
10731 /*Configurable ODT(TE) Phase Shift*/
10732 #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL
10733 #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
10734 #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK
10735 #define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                                            0x40200204
10736 #define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                                             28
10737 #define DDR_PHY_DX2GCR0_CODTSHFT_MASK                                              0x30000000U
10738
10739 /*DQS Duty Cycle Correction*/
10740 #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL
10741 #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT
10742 #undef DDR_PHY_DX2GCR0_DQSDCC_MASK
10743 #define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                                              0x40200204
10744 #define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                                               24
10745 #define DDR_PHY_DX2GCR0_DQSDCC_MASK                                                0x0F000000U
10746
10747 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10748 #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL
10749 #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT
10750 #undef DDR_PHY_DX2GCR0_RDDLY_MASK
10751 #define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                                               0x40200204
10752 #define DDR_PHY_DX2GCR0_RDDLY_SHIFT                                                20
10753 #define DDR_PHY_DX2GCR0_RDDLY_MASK                                                 0x00F00000U
10754
10755 /*Reserved. Return zeroes on reads.*/
10756 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL
10757 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
10758 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK
10759 #define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
10760 #define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                                       14
10761 #define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                                        0x000FC000U
10762
10763 /*DQSNSE Power Down Receiver*/
10764 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL
10765 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
10766 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK
10767 #define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
10768 #define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                                            13
10769 #define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                                             0x00002000U
10770
10771 /*DQSSE Power Down Receiver*/
10772 #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL
10773 #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
10774 #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK
10775 #define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                                            0x40200204
10776 #define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                                             12
10777 #define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                                              0x00001000U
10778
10779 /*RTT On Additive Latency*/
10780 #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL
10781 #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT
10782 #undef DDR_PHY_DX2GCR0_RTTOAL_MASK
10783 #define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                                              0x40200204
10784 #define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                                               11
10785 #define DDR_PHY_DX2GCR0_RTTOAL_MASK                                                0x00000800U
10786
10787 /*RTT Output Hold*/
10788 #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL
10789 #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT
10790 #undef DDR_PHY_DX2GCR0_RTTOH_MASK
10791 #define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                                               0x40200204
10792 #define DDR_PHY_DX2GCR0_RTTOH_SHIFT                                                9
10793 #define DDR_PHY_DX2GCR0_RTTOH_MASK                                                 0x00000600U
10794
10795 /*Configurable PDR Phase Shift*/
10796 #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL
10797 #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
10798 #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK
10799 #define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                                            0x40200204
10800 #define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                                             7
10801 #define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                                              0x00000180U
10802
10803 /*DQSR Power Down*/
10804 #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL
10805 #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT
10806 #undef DDR_PHY_DX2GCR0_DQSRPD_MASK
10807 #define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                                              0x40200204
10808 #define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                                               6
10809 #define DDR_PHY_DX2GCR0_DQSRPD_MASK                                                0x00000040U
10810
10811 /*DQSG Power Down Receiver*/
10812 #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL
10813 #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
10814 #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK
10815 #define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                                             0x40200204
10816 #define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                                              5
10817 #define DDR_PHY_DX2GCR0_DQSGPDR_MASK                                               0x00000020U
10818
10819 /*Reserved. Return zeroes on reads.*/
10820 #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL
10821 #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
10822 #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK
10823 #define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                                          0x40200204
10824 #define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                                           4
10825 #define DDR_PHY_DX2GCR0_RESERVED_4_MASK                                            0x00000010U
10826
10827 /*DQSG On-Die Termination*/
10828 #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL
10829 #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT
10830 #undef DDR_PHY_DX2GCR0_DQSGODT_MASK
10831 #define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                                             0x40200204
10832 #define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                                              3
10833 #define DDR_PHY_DX2GCR0_DQSGODT_MASK                                               0x00000008U
10834
10835 /*DQSG Output Enable*/
10836 #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL
10837 #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT
10838 #undef DDR_PHY_DX2GCR0_DQSGOE_MASK
10839 #define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                                              0x40200204
10840 #define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                                               2
10841 #define DDR_PHY_DX2GCR0_DQSGOE_MASK                                                0x00000004U
10842
10843 /*Reserved. Return zeroes on reads.*/
10844 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL
10845 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
10846 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK
10847 #define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
10848 #define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                                         0
10849 #define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                                          0x00000003U
10850
10851 /*Enables the PDR mode for DQ[7:0]*/
10852 #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL
10853 #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
10854 #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK
10855 #define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
10856 #define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                                            16
10857 #define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
10858
10859 /*Reserved. Returns zeroes on reads.*/
10860 #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL
10861 #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
10862 #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK
10863 #define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
10864 #define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                                          15
10865 #define DDR_PHY_DX2GCR1_RESERVED_15_MASK                                           0x00008000U
10866
10867 /*Select the delayed or non-delayed read data strobe #*/
10868 #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL
10869 #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT
10870 #undef DDR_PHY_DX2GCR1_QSNSEL_MASK
10871 #define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                                              0x00007FFF
10872 #define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                                               14
10873 #define DDR_PHY_DX2GCR1_QSNSEL_MASK                                                0x00004000U
10874
10875 /*Select the delayed or non-delayed read data strobe*/
10876 #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL
10877 #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT
10878 #undef DDR_PHY_DX2GCR1_QSSEL_MASK
10879 #define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                                               0x00007FFF
10880 #define DDR_PHY_DX2GCR1_QSSEL_SHIFT                                                13
10881 #define DDR_PHY_DX2GCR1_QSSEL_MASK                                                 0x00002000U
10882
10883 /*Enables Read Data Strobe in a byte lane*/
10884 #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL
10885 #undef DDR_PHY_DX2GCR1_OEEN_SHIFT
10886 #undef DDR_PHY_DX2GCR1_OEEN_MASK
10887 #define DDR_PHY_DX2GCR1_OEEN_DEFVAL                                                0x00007FFF
10888 #define DDR_PHY_DX2GCR1_OEEN_SHIFT                                                 12
10889 #define DDR_PHY_DX2GCR1_OEEN_MASK                                                  0x00001000U
10890
10891 /*Enables PDR in a byte lane*/
10892 #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL
10893 #undef DDR_PHY_DX2GCR1_PDREN_SHIFT
10894 #undef DDR_PHY_DX2GCR1_PDREN_MASK
10895 #define DDR_PHY_DX2GCR1_PDREN_DEFVAL                                               0x00007FFF
10896 #define DDR_PHY_DX2GCR1_PDREN_SHIFT                                                11
10897 #define DDR_PHY_DX2GCR1_PDREN_MASK                                                 0x00000800U
10898
10899 /*Enables ODT/TE in a byte lane*/
10900 #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL
10901 #undef DDR_PHY_DX2GCR1_TEEN_SHIFT
10902 #undef DDR_PHY_DX2GCR1_TEEN_MASK
10903 #define DDR_PHY_DX2GCR1_TEEN_DEFVAL                                                0x00007FFF
10904 #define DDR_PHY_DX2GCR1_TEEN_SHIFT                                                 10
10905 #define DDR_PHY_DX2GCR1_TEEN_MASK                                                  0x00000400U
10906
10907 /*Enables Write Data strobe in a byte lane*/
10908 #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL
10909 #undef DDR_PHY_DX2GCR1_DSEN_SHIFT
10910 #undef DDR_PHY_DX2GCR1_DSEN_MASK
10911 #define DDR_PHY_DX2GCR1_DSEN_DEFVAL                                                0x00007FFF
10912 #define DDR_PHY_DX2GCR1_DSEN_SHIFT                                                 9
10913 #define DDR_PHY_DX2GCR1_DSEN_MASK                                                  0x00000200U
10914
10915 /*Enables DM pin in a byte lane*/
10916 #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL
10917 #undef DDR_PHY_DX2GCR1_DMEN_SHIFT
10918 #undef DDR_PHY_DX2GCR1_DMEN_MASK
10919 #define DDR_PHY_DX2GCR1_DMEN_DEFVAL                                                0x00007FFF
10920 #define DDR_PHY_DX2GCR1_DMEN_SHIFT                                                 8
10921 #define DDR_PHY_DX2GCR1_DMEN_MASK                                                  0x00000100U
10922
10923 /*Enables DQ corresponding to each bit in a byte*/
10924 #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL
10925 #undef DDR_PHY_DX2GCR1_DQEN_SHIFT
10926 #undef DDR_PHY_DX2GCR1_DQEN_MASK
10927 #define DDR_PHY_DX2GCR1_DQEN_DEFVAL                                                0x00007FFF
10928 #define DDR_PHY_DX2GCR1_DQEN_SHIFT                                                 0
10929 #define DDR_PHY_DX2GCR1_DQEN_MASK                                                  0x000000FFU
10930
10931 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10932 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL
10933 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
10934 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK
10935 #define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
10936 #define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                                       29
10937 #define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                                        0xE0000000U
10938
10939 /*Byte Lane VREF Pad Enable*/
10940 #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL
10941 #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
10942 #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK
10943 #define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
10944 #define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                                             28
10945 #define DDR_PHY_DX2GCR4_DXREFPEN_MASK                                              0x10000000U
10946
10947 /*Byte Lane Internal VREF Enable*/
10948 #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL
10949 #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
10950 #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK
10951 #define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
10952 #define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                                             26
10953 #define DDR_PHY_DX2GCR4_DXREFEEN_MASK                                              0x0C000000U
10954
10955 /*Byte Lane Single-End VREF Enable*/
10956 #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL
10957 #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
10958 #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK
10959 #define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
10960 #define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                                             25
10961 #define DDR_PHY_DX2GCR4_DXREFSEN_MASK                                              0x02000000U
10962
10963 /*Reserved. Returns zeros on reads.*/
10964 #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL
10965 #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
10966 #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK
10967 #define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
10968 #define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                                          24
10969 #define DDR_PHY_DX2GCR4_RESERVED_24_MASK                                           0x01000000U
10970
10971 /*External VREF generator REFSEL range select*/
10972 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL
10973 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
10974 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK
10975 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
10976 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                                       23
10977 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                                        0x00800000U
10978
10979 /*Byte Lane External VREF Select*/
10980 #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL
10981 #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
10982 #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK
10983 #define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
10984 #define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                                            16
10985 #define DDR_PHY_DX2GCR4_DXREFESEL_MASK                                             0x007F0000U
10986
10987 /*Single ended VREF generator REFSEL range select*/
10988 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL
10989 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
10990 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK
10991 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
10992 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                                       15
10993 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
10994
10995 /*Byte Lane Single-End VREF Select*/
10996 #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL
10997 #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
10998 #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK
10999 #define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
11000 #define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                                            8
11001 #define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                                             0x00007F00U
11002
11003 /*Reserved. Returns zeros on reads.*/
11004 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL
11005 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
11006 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK
11007 #define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
11008 #define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                                         6
11009 #define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                                          0x000000C0U
11010
11011 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
11012 #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL
11013 #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
11014 #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK
11015 #define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
11016 #define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                                             2
11017 #define DDR_PHY_DX2GCR4_DXREFIEN_MASK                                              0x0000003CU
11018
11019 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
11020 #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL
11021 #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
11022 #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK
11023 #define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
11024 #define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                                            0
11025 #define DDR_PHY_DX2GCR4_DXREFIMON_MASK                                             0x00000003U
11026
11027 /*Reserved. Returns zeros on reads.*/
11028 #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL
11029 #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
11030 #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK
11031 #define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                                         0x09090909
11032 #define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                                          31
11033 #define DDR_PHY_DX2GCR5_RESERVED_31_MASK                                           0x80000000U
11034
11035 /*Byte Lane internal VREF Select for Rank 3*/
11036 #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL
11037 #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
11038 #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK
11039 #define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                                         0x09090909
11040 #define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                                          24
11041 #define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                                           0x7F000000U
11042
11043 /*Reserved. Returns zeros on reads.*/
11044 #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL
11045 #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
11046 #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK
11047 #define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                                         0x09090909
11048 #define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                                          23
11049 #define DDR_PHY_DX2GCR5_RESERVED_23_MASK                                           0x00800000U
11050
11051 /*Byte Lane internal VREF Select for Rank 2*/
11052 #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL
11053 #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
11054 #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK
11055 #define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                                         0x09090909
11056 #define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                                          16
11057 #define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                                           0x007F0000U
11058
11059 /*Reserved. Returns zeros on reads.*/
11060 #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL
11061 #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
11062 #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK
11063 #define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                                         0x09090909
11064 #define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                                          15
11065 #define DDR_PHY_DX2GCR5_RESERVED_15_MASK                                           0x00008000U
11066
11067 /*Byte Lane internal VREF Select for Rank 1*/
11068 #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL
11069 #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
11070 #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK
11071 #define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                                         0x09090909
11072 #define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                                          8
11073 #define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                                           0x00007F00U
11074
11075 /*Reserved. Returns zeros on reads.*/
11076 #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL
11077 #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
11078 #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK
11079 #define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                                          0x09090909
11080 #define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                                           7
11081 #define DDR_PHY_DX2GCR5_RESERVED_7_MASK                                            0x00000080U
11082
11083 /*Byte Lane internal VREF Select for Rank 0*/
11084 #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL
11085 #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
11086 #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK
11087 #define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                                         0x09090909
11088 #define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                                          0
11089 #define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                                           0x0000007FU
11090
11091 /*Reserved. Returns zeros on reads.*/
11092 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL
11093 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
11094 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK
11095 #define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
11096 #define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                                       30
11097 #define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                                        0xC0000000U
11098
11099 /*DRAM DQ VREF Select for Rank3*/
11100 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL
11101 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
11102 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK
11103 #define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
11104 #define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                                           24
11105 #define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                                            0x3F000000U
11106
11107 /*Reserved. Returns zeros on reads.*/
11108 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL
11109 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
11110 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK
11111 #define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
11112 #define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                                       22
11113 #define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                                        0x00C00000U
11114
11115 /*DRAM DQ VREF Select for Rank2*/
11116 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL
11117 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
11118 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK
11119 #define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
11120 #define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                                           16
11121 #define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                                            0x003F0000U
11122
11123 /*Reserved. Returns zeros on reads.*/
11124 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL
11125 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
11126 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK
11127 #define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
11128 #define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                                       14
11129 #define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                                        0x0000C000U
11130
11131 /*DRAM DQ VREF Select for Rank1*/
11132 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL
11133 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
11134 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK
11135 #define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
11136 #define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                                           8
11137 #define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                                            0x00003F00U
11138
11139 /*Reserved. Returns zeros on reads.*/
11140 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL
11141 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
11142 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK
11143 #define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
11144 #define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                                         6
11145 #define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                                          0x000000C0U
11146
11147 /*DRAM DQ VREF Select for Rank0*/
11148 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL
11149 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
11150 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK
11151 #define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
11152 #define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                                           0
11153 #define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                                            0x0000003FU
11154
11155 /*Reserved. Return zeroes on reads.*/
11156 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL
11157 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
11158 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK
11159 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
11160 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT                                     25
11161 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
11162
11163 /*Reserved. Caution, do not write to this register field.*/
11164 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL
11165 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
11166 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK
11167 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
11168 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT                                     16
11169 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
11170
11171 /*Reserved. Return zeroes on reads.*/
11172 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL
11173 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
11174 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK
11175 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
11176 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT                                      9
11177 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
11178
11179 /*Read DQS Gating Delay*/
11180 #undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL
11181 #undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
11182 #undef DDR_PHY_DX2LCDLR2_DQSGD_MASK
11183 #define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL                                             0x00000000
11184 #define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT                                              0
11185 #define DDR_PHY_DX2LCDLR2_DQSGD_MASK                                               0x000001FFU
11186
11187 /*Reserved. Return zeroes on reads.*/
11188 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL
11189 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
11190 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK
11191 #define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
11192 #define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT                                       27
11193 #define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK                                        0xF8000000U
11194
11195 /*DQ Write Path Latency Pipeline*/
11196 #undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL
11197 #undef DDR_PHY_DX2GTR0_WDQSL_SHIFT
11198 #undef DDR_PHY_DX2GTR0_WDQSL_MASK
11199 #define DDR_PHY_DX2GTR0_WDQSL_DEFVAL                                               0x00020000
11200 #define DDR_PHY_DX2GTR0_WDQSL_SHIFT                                                24
11201 #define DDR_PHY_DX2GTR0_WDQSL_MASK                                                 0x07000000U
11202
11203 /*Reserved. Caution, do not write to this register field.*/
11204 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL
11205 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
11206 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK
11207 #define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
11208 #define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT                                       20
11209 #define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK                                        0x00F00000U
11210
11211 /*Write Leveling System Latency*/
11212 #undef DDR_PHY_DX2GTR0_WLSL_DEFVAL
11213 #undef DDR_PHY_DX2GTR0_WLSL_SHIFT
11214 #undef DDR_PHY_DX2GTR0_WLSL_MASK
11215 #define DDR_PHY_DX2GTR0_WLSL_DEFVAL                                                0x00020000
11216 #define DDR_PHY_DX2GTR0_WLSL_SHIFT                                                 16
11217 #define DDR_PHY_DX2GTR0_WLSL_MASK                                                  0x000F0000U
11218
11219 /*Reserved. Return zeroes on reads.*/
11220 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL
11221 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
11222 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK
11223 #define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
11224 #define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT                                       13
11225 #define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK                                        0x0000E000U
11226
11227 /*Reserved. Caution, do not write to this register field.*/
11228 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL
11229 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
11230 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK
11231 #define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
11232 #define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT                                        8
11233 #define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK                                         0x00001F00U
11234
11235 /*Reserved. Return zeroes on reads.*/
11236 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL
11237 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
11238 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK
11239 #define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
11240 #define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT                                         5
11241 #define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK                                          0x000000E0U
11242
11243 /*DQS Gating System Latency*/
11244 #undef DDR_PHY_DX2GTR0_DGSL_DEFVAL
11245 #undef DDR_PHY_DX2GTR0_DGSL_SHIFT
11246 #undef DDR_PHY_DX2GTR0_DGSL_MASK
11247 #define DDR_PHY_DX2GTR0_DGSL_DEFVAL                                                0x00020000
11248 #define DDR_PHY_DX2GTR0_DGSL_SHIFT                                                 0
11249 #define DDR_PHY_DX2GTR0_DGSL_MASK                                                  0x0000001FU
11250
11251 /*Calibration Bypass*/
11252 #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL
11253 #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT
11254 #undef DDR_PHY_DX3GCR0_CALBYP_MASK
11255 #define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                                              0x40200204
11256 #define DDR_PHY_DX3GCR0_CALBYP_SHIFT                                               31
11257 #define DDR_PHY_DX3GCR0_CALBYP_MASK                                                0x80000000U
11258
11259 /*Master Delay Line Enable*/
11260 #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL
11261 #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT
11262 #undef DDR_PHY_DX3GCR0_MDLEN_MASK
11263 #define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                                               0x40200204
11264 #define DDR_PHY_DX3GCR0_MDLEN_SHIFT                                                30
11265 #define DDR_PHY_DX3GCR0_MDLEN_MASK                                                 0x40000000U
11266
11267 /*Configurable ODT(TE) Phase Shift*/
11268 #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL
11269 #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
11270 #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK
11271 #define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                                            0x40200204
11272 #define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                                             28
11273 #define DDR_PHY_DX3GCR0_CODTSHFT_MASK                                              0x30000000U
11274
11275 /*DQS Duty Cycle Correction*/
11276 #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL
11277 #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT
11278 #undef DDR_PHY_DX3GCR0_DQSDCC_MASK
11279 #define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                                              0x40200204
11280 #define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                                               24
11281 #define DDR_PHY_DX3GCR0_DQSDCC_MASK                                                0x0F000000U
11282
11283 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11284 #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL
11285 #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT
11286 #undef DDR_PHY_DX3GCR0_RDDLY_MASK
11287 #define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                                               0x40200204
11288 #define DDR_PHY_DX3GCR0_RDDLY_SHIFT                                                20
11289 #define DDR_PHY_DX3GCR0_RDDLY_MASK                                                 0x00F00000U
11290
11291 /*Reserved. Return zeroes on reads.*/
11292 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL
11293 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
11294 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK
11295 #define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
11296 #define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                                       14
11297 #define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                                        0x000FC000U
11298
11299 /*DQSNSE Power Down Receiver*/
11300 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL
11301 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
11302 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK
11303 #define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
11304 #define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                                            13
11305 #define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                                             0x00002000U
11306
11307 /*DQSSE Power Down Receiver*/
11308 #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL
11309 #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
11310 #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK
11311 #define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                                            0x40200204
11312 #define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                                             12
11313 #define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                                              0x00001000U
11314
11315 /*RTT On Additive Latency*/
11316 #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL
11317 #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT
11318 #undef DDR_PHY_DX3GCR0_RTTOAL_MASK
11319 #define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                                              0x40200204
11320 #define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                                               11
11321 #define DDR_PHY_DX3GCR0_RTTOAL_MASK                                                0x00000800U
11322
11323 /*RTT Output Hold*/
11324 #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL
11325 #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT
11326 #undef DDR_PHY_DX3GCR0_RTTOH_MASK
11327 #define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                                               0x40200204
11328 #define DDR_PHY_DX3GCR0_RTTOH_SHIFT                                                9
11329 #define DDR_PHY_DX3GCR0_RTTOH_MASK                                                 0x00000600U
11330
11331 /*Configurable PDR Phase Shift*/
11332 #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL
11333 #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
11334 #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK
11335 #define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                                            0x40200204
11336 #define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                                             7
11337 #define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                                              0x00000180U
11338
11339 /*DQSR Power Down*/
11340 #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL
11341 #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT
11342 #undef DDR_PHY_DX3GCR0_DQSRPD_MASK
11343 #define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                                              0x40200204
11344 #define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                                               6
11345 #define DDR_PHY_DX3GCR0_DQSRPD_MASK                                                0x00000040U
11346
11347 /*DQSG Power Down Receiver*/
11348 #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL
11349 #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
11350 #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK
11351 #define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                                             0x40200204
11352 #define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                                              5
11353 #define DDR_PHY_DX3GCR0_DQSGPDR_MASK                                               0x00000020U
11354
11355 /*Reserved. Return zeroes on reads.*/
11356 #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL
11357 #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
11358 #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK
11359 #define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                                          0x40200204
11360 #define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                                           4
11361 #define DDR_PHY_DX3GCR0_RESERVED_4_MASK                                            0x00000010U
11362
11363 /*DQSG On-Die Termination*/
11364 #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL
11365 #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT
11366 #undef DDR_PHY_DX3GCR0_DQSGODT_MASK
11367 #define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                                             0x40200204
11368 #define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                                              3
11369 #define DDR_PHY_DX3GCR0_DQSGODT_MASK                                               0x00000008U
11370
11371 /*DQSG Output Enable*/
11372 #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL
11373 #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT
11374 #undef DDR_PHY_DX3GCR0_DQSGOE_MASK
11375 #define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                                              0x40200204
11376 #define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                                               2
11377 #define DDR_PHY_DX3GCR0_DQSGOE_MASK                                                0x00000004U
11378
11379 /*Reserved. Return zeroes on reads.*/
11380 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL
11381 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
11382 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK
11383 #define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
11384 #define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                                         0
11385 #define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                                          0x00000003U
11386
11387 /*Enables the PDR mode for DQ[7:0]*/
11388 #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL
11389 #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
11390 #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK
11391 #define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
11392 #define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                                            16
11393 #define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
11394
11395 /*Reserved. Returns zeroes on reads.*/
11396 #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL
11397 #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
11398 #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK
11399 #define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
11400 #define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                                          15
11401 #define DDR_PHY_DX3GCR1_RESERVED_15_MASK                                           0x00008000U
11402
11403 /*Select the delayed or non-delayed read data strobe #*/
11404 #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL
11405 #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT
11406 #undef DDR_PHY_DX3GCR1_QSNSEL_MASK
11407 #define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                                              0x00007FFF
11408 #define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                                               14
11409 #define DDR_PHY_DX3GCR1_QSNSEL_MASK                                                0x00004000U
11410
11411 /*Select the delayed or non-delayed read data strobe*/
11412 #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL
11413 #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT
11414 #undef DDR_PHY_DX3GCR1_QSSEL_MASK
11415 #define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                                               0x00007FFF
11416 #define DDR_PHY_DX3GCR1_QSSEL_SHIFT                                                13
11417 #define DDR_PHY_DX3GCR1_QSSEL_MASK                                                 0x00002000U
11418
11419 /*Enables Read Data Strobe in a byte lane*/
11420 #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL
11421 #undef DDR_PHY_DX3GCR1_OEEN_SHIFT
11422 #undef DDR_PHY_DX3GCR1_OEEN_MASK
11423 #define DDR_PHY_DX3GCR1_OEEN_DEFVAL                                                0x00007FFF
11424 #define DDR_PHY_DX3GCR1_OEEN_SHIFT                                                 12
11425 #define DDR_PHY_DX3GCR1_OEEN_MASK                                                  0x00001000U
11426
11427 /*Enables PDR in a byte lane*/
11428 #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL
11429 #undef DDR_PHY_DX3GCR1_PDREN_SHIFT
11430 #undef DDR_PHY_DX3GCR1_PDREN_MASK
11431 #define DDR_PHY_DX3GCR1_PDREN_DEFVAL                                               0x00007FFF
11432 #define DDR_PHY_DX3GCR1_PDREN_SHIFT                                                11
11433 #define DDR_PHY_DX3GCR1_PDREN_MASK                                                 0x00000800U
11434
11435 /*Enables ODT/TE in a byte lane*/
11436 #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL
11437 #undef DDR_PHY_DX3GCR1_TEEN_SHIFT
11438 #undef DDR_PHY_DX3GCR1_TEEN_MASK
11439 #define DDR_PHY_DX3GCR1_TEEN_DEFVAL                                                0x00007FFF
11440 #define DDR_PHY_DX3GCR1_TEEN_SHIFT                                                 10
11441 #define DDR_PHY_DX3GCR1_TEEN_MASK                                                  0x00000400U
11442
11443 /*Enables Write Data strobe in a byte lane*/
11444 #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL
11445 #undef DDR_PHY_DX3GCR1_DSEN_SHIFT
11446 #undef DDR_PHY_DX3GCR1_DSEN_MASK
11447 #define DDR_PHY_DX3GCR1_DSEN_DEFVAL                                                0x00007FFF
11448 #define DDR_PHY_DX3GCR1_DSEN_SHIFT                                                 9
11449 #define DDR_PHY_DX3GCR1_DSEN_MASK                                                  0x00000200U
11450
11451 /*Enables DM pin in a byte lane*/
11452 #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL
11453 #undef DDR_PHY_DX3GCR1_DMEN_SHIFT
11454 #undef DDR_PHY_DX3GCR1_DMEN_MASK
11455 #define DDR_PHY_DX3GCR1_DMEN_DEFVAL                                                0x00007FFF
11456 #define DDR_PHY_DX3GCR1_DMEN_SHIFT                                                 8
11457 #define DDR_PHY_DX3GCR1_DMEN_MASK                                                  0x00000100U
11458
11459 /*Enables DQ corresponding to each bit in a byte*/
11460 #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL
11461 #undef DDR_PHY_DX3GCR1_DQEN_SHIFT
11462 #undef DDR_PHY_DX3GCR1_DQEN_MASK
11463 #define DDR_PHY_DX3GCR1_DQEN_DEFVAL                                                0x00007FFF
11464 #define DDR_PHY_DX3GCR1_DQEN_SHIFT                                                 0
11465 #define DDR_PHY_DX3GCR1_DQEN_MASK                                                  0x000000FFU
11466
11467 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
11468 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL
11469 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
11470 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK
11471 #define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
11472 #define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                                       29
11473 #define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                                        0xE0000000U
11474
11475 /*Byte Lane VREF Pad Enable*/
11476 #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL
11477 #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
11478 #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK
11479 #define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
11480 #define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                                             28
11481 #define DDR_PHY_DX3GCR4_DXREFPEN_MASK                                              0x10000000U
11482
11483 /*Byte Lane Internal VREF Enable*/
11484 #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL
11485 #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
11486 #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK
11487 #define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
11488 #define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                                             26
11489 #define DDR_PHY_DX3GCR4_DXREFEEN_MASK                                              0x0C000000U
11490
11491 /*Byte Lane Single-End VREF Enable*/
11492 #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL
11493 #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
11494 #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK
11495 #define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
11496 #define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                                             25
11497 #define DDR_PHY_DX3GCR4_DXREFSEN_MASK                                              0x02000000U
11498
11499 /*Reserved. Returns zeros on reads.*/
11500 #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL
11501 #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
11502 #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK
11503 #define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
11504 #define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                                          24
11505 #define DDR_PHY_DX3GCR4_RESERVED_24_MASK                                           0x01000000U
11506
11507 /*External VREF generator REFSEL range select*/
11508 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL
11509 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
11510 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK
11511 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
11512 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                                       23
11513 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                                        0x00800000U
11514
11515 /*Byte Lane External VREF Select*/
11516 #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL
11517 #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
11518 #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK
11519 #define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
11520 #define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                                            16
11521 #define DDR_PHY_DX3GCR4_DXREFESEL_MASK                                             0x007F0000U
11522
11523 /*Single ended VREF generator REFSEL range select*/
11524 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL
11525 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
11526 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK
11527 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
11528 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                                       15
11529 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
11530
11531 /*Byte Lane Single-End VREF Select*/
11532 #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL
11533 #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
11534 #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK
11535 #define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
11536 #define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                                            8
11537 #define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                                             0x00007F00U
11538
11539 /*Reserved. Returns zeros on reads.*/
11540 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL
11541 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
11542 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK
11543 #define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
11544 #define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                                         6
11545 #define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                                          0x000000C0U
11546
11547 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
11548 #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL
11549 #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
11550 #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK
11551 #define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
11552 #define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                                             2
11553 #define DDR_PHY_DX3GCR4_DXREFIEN_MASK                                              0x0000003CU
11554
11555 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
11556 #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL
11557 #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
11558 #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK
11559 #define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
11560 #define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                                            0
11561 #define DDR_PHY_DX3GCR4_DXREFIMON_MASK                                             0x00000003U
11562
11563 /*Reserved. Returns zeros on reads.*/
11564 #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL
11565 #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
11566 #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK
11567 #define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                                         0x09090909
11568 #define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                                          31
11569 #define DDR_PHY_DX3GCR5_RESERVED_31_MASK                                           0x80000000U
11570
11571 /*Byte Lane internal VREF Select for Rank 3*/
11572 #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL
11573 #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
11574 #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK
11575 #define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                                         0x09090909
11576 #define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                                          24
11577 #define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                                           0x7F000000U
11578
11579 /*Reserved. Returns zeros on reads.*/
11580 #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL
11581 #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
11582 #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK
11583 #define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                                         0x09090909
11584 #define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                                          23
11585 #define DDR_PHY_DX3GCR5_RESERVED_23_MASK                                           0x00800000U
11586
11587 /*Byte Lane internal VREF Select for Rank 2*/
11588 #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL
11589 #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
11590 #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK
11591 #define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                                         0x09090909
11592 #define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                                          16
11593 #define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                                           0x007F0000U
11594
11595 /*Reserved. Returns zeros on reads.*/
11596 #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL
11597 #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
11598 #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK
11599 #define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                                         0x09090909
11600 #define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                                          15
11601 #define DDR_PHY_DX3GCR5_RESERVED_15_MASK                                           0x00008000U
11602
11603 /*Byte Lane internal VREF Select for Rank 1*/
11604 #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL
11605 #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
11606 #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK
11607 #define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                                         0x09090909
11608 #define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                                          8
11609 #define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                                           0x00007F00U
11610
11611 /*Reserved. Returns zeros on reads.*/
11612 #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL
11613 #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
11614 #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK
11615 #define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                                          0x09090909
11616 #define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                                           7
11617 #define DDR_PHY_DX3GCR5_RESERVED_7_MASK                                            0x00000080U
11618
11619 /*Byte Lane internal VREF Select for Rank 0*/
11620 #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL
11621 #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
11622 #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK
11623 #define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                                         0x09090909
11624 #define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                                          0
11625 #define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                                           0x0000007FU
11626
11627 /*Reserved. Returns zeros on reads.*/
11628 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL
11629 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
11630 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK
11631 #define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
11632 #define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                                       30
11633 #define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                                        0xC0000000U
11634
11635 /*DRAM DQ VREF Select for Rank3*/
11636 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL
11637 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
11638 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK
11639 #define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
11640 #define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                                           24
11641 #define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                                            0x3F000000U
11642
11643 /*Reserved. Returns zeros on reads.*/
11644 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL
11645 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
11646 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK
11647 #define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
11648 #define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                                       22
11649 #define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                                        0x00C00000U
11650
11651 /*DRAM DQ VREF Select for Rank2*/
11652 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL
11653 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
11654 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK
11655 #define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
11656 #define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                                           16
11657 #define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                                            0x003F0000U
11658
11659 /*Reserved. Returns zeros on reads.*/
11660 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL
11661 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
11662 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK
11663 #define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
11664 #define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                                       14
11665 #define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                                        0x0000C000U
11666
11667 /*DRAM DQ VREF Select for Rank1*/
11668 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL
11669 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
11670 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK
11671 #define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
11672 #define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                                           8
11673 #define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                                            0x00003F00U
11674
11675 /*Reserved. Returns zeros on reads.*/
11676 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL
11677 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
11678 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK
11679 #define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
11680 #define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                                         6
11681 #define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                                          0x000000C0U
11682
11683 /*DRAM DQ VREF Select for Rank0*/
11684 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL
11685 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
11686 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK
11687 #define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
11688 #define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                                           0
11689 #define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                                            0x0000003FU
11690
11691 /*Reserved. Return zeroes on reads.*/
11692 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL
11693 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
11694 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK
11695 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
11696 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT                                     25
11697 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
11698
11699 /*Reserved. Caution, do not write to this register field.*/
11700 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL
11701 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
11702 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK
11703 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
11704 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT                                     16
11705 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
11706
11707 /*Reserved. Return zeroes on reads.*/
11708 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL
11709 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
11710 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK
11711 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
11712 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT                                      9
11713 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
11714
11715 /*Read DQS Gating Delay*/
11716 #undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL
11717 #undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
11718 #undef DDR_PHY_DX3LCDLR2_DQSGD_MASK
11719 #define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL                                             0x00000000
11720 #define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT                                              0
11721 #define DDR_PHY_DX3LCDLR2_DQSGD_MASK                                               0x000001FFU
11722
11723 /*Reserved. Return zeroes on reads.*/
11724 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL
11725 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
11726 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK
11727 #define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
11728 #define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT                                       27
11729 #define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK                                        0xF8000000U
11730
11731 /*DQ Write Path Latency Pipeline*/
11732 #undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL
11733 #undef DDR_PHY_DX3GTR0_WDQSL_SHIFT
11734 #undef DDR_PHY_DX3GTR0_WDQSL_MASK
11735 #define DDR_PHY_DX3GTR0_WDQSL_DEFVAL                                               0x00020000
11736 #define DDR_PHY_DX3GTR0_WDQSL_SHIFT                                                24
11737 #define DDR_PHY_DX3GTR0_WDQSL_MASK                                                 0x07000000U
11738
11739 /*Reserved. Caution, do not write to this register field.*/
11740 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL
11741 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
11742 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK
11743 #define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
11744 #define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT                                       20
11745 #define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK                                        0x00F00000U
11746
11747 /*Write Leveling System Latency*/
11748 #undef DDR_PHY_DX3GTR0_WLSL_DEFVAL
11749 #undef DDR_PHY_DX3GTR0_WLSL_SHIFT
11750 #undef DDR_PHY_DX3GTR0_WLSL_MASK
11751 #define DDR_PHY_DX3GTR0_WLSL_DEFVAL                                                0x00020000
11752 #define DDR_PHY_DX3GTR0_WLSL_SHIFT                                                 16
11753 #define DDR_PHY_DX3GTR0_WLSL_MASK                                                  0x000F0000U
11754
11755 /*Reserved. Return zeroes on reads.*/
11756 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL
11757 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
11758 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK
11759 #define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
11760 #define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT                                       13
11761 #define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK                                        0x0000E000U
11762
11763 /*Reserved. Caution, do not write to this register field.*/
11764 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL
11765 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
11766 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK
11767 #define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
11768 #define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT                                        8
11769 #define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK                                         0x00001F00U
11770
11771 /*Reserved. Return zeroes on reads.*/
11772 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL
11773 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
11774 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK
11775 #define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
11776 #define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT                                         5
11777 #define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK                                          0x000000E0U
11778
11779 /*DQS Gating System Latency*/
11780 #undef DDR_PHY_DX3GTR0_DGSL_DEFVAL
11781 #undef DDR_PHY_DX3GTR0_DGSL_SHIFT
11782 #undef DDR_PHY_DX3GTR0_DGSL_MASK
11783 #define DDR_PHY_DX3GTR0_DGSL_DEFVAL                                                0x00020000
11784 #define DDR_PHY_DX3GTR0_DGSL_SHIFT                                                 0
11785 #define DDR_PHY_DX3GTR0_DGSL_MASK                                                  0x0000001FU
11786
11787 /*Calibration Bypass*/
11788 #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL
11789 #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT
11790 #undef DDR_PHY_DX4GCR0_CALBYP_MASK
11791 #define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                                              0x40200204
11792 #define DDR_PHY_DX4GCR0_CALBYP_SHIFT                                               31
11793 #define DDR_PHY_DX4GCR0_CALBYP_MASK                                                0x80000000U
11794
11795 /*Master Delay Line Enable*/
11796 #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL
11797 #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT
11798 #undef DDR_PHY_DX4GCR0_MDLEN_MASK
11799 #define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                                               0x40200204
11800 #define DDR_PHY_DX4GCR0_MDLEN_SHIFT                                                30
11801 #define DDR_PHY_DX4GCR0_MDLEN_MASK                                                 0x40000000U
11802
11803 /*Configurable ODT(TE) Phase Shift*/
11804 #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL
11805 #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
11806 #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK
11807 #define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                                            0x40200204
11808 #define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                                             28
11809 #define DDR_PHY_DX4GCR0_CODTSHFT_MASK                                              0x30000000U
11810
11811 /*DQS Duty Cycle Correction*/
11812 #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL
11813 #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT
11814 #undef DDR_PHY_DX4GCR0_DQSDCC_MASK
11815 #define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                                              0x40200204
11816 #define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                                               24
11817 #define DDR_PHY_DX4GCR0_DQSDCC_MASK                                                0x0F000000U
11818
11819 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11820 #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL
11821 #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT
11822 #undef DDR_PHY_DX4GCR0_RDDLY_MASK
11823 #define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                                               0x40200204
11824 #define DDR_PHY_DX4GCR0_RDDLY_SHIFT                                                20
11825 #define DDR_PHY_DX4GCR0_RDDLY_MASK                                                 0x00F00000U
11826
11827 /*Reserved. Return zeroes on reads.*/
11828 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL
11829 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
11830 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK
11831 #define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
11832 #define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                                       14
11833 #define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                                        0x000FC000U
11834
11835 /*DQSNSE Power Down Receiver*/
11836 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL
11837 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
11838 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK
11839 #define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
11840 #define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                                            13
11841 #define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                                             0x00002000U
11842
11843 /*DQSSE Power Down Receiver*/
11844 #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL
11845 #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
11846 #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK
11847 #define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                                            0x40200204
11848 #define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                                             12
11849 #define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                                              0x00001000U
11850
11851 /*RTT On Additive Latency*/
11852 #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL
11853 #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT
11854 #undef DDR_PHY_DX4GCR0_RTTOAL_MASK
11855 #define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                                              0x40200204
11856 #define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                                               11
11857 #define DDR_PHY_DX4GCR0_RTTOAL_MASK                                                0x00000800U
11858
11859 /*RTT Output Hold*/
11860 #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL
11861 #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT
11862 #undef DDR_PHY_DX4GCR0_RTTOH_MASK
11863 #define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                                               0x40200204
11864 #define DDR_PHY_DX4GCR0_RTTOH_SHIFT                                                9
11865 #define DDR_PHY_DX4GCR0_RTTOH_MASK                                                 0x00000600U
11866
11867 /*Configurable PDR Phase Shift*/
11868 #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL
11869 #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
11870 #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK
11871 #define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                                            0x40200204
11872 #define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                                             7
11873 #define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                                              0x00000180U
11874
11875 /*DQSR Power Down*/
11876 #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL
11877 #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT
11878 #undef DDR_PHY_DX4GCR0_DQSRPD_MASK
11879 #define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                                              0x40200204
11880 #define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                                               6
11881 #define DDR_PHY_DX4GCR0_DQSRPD_MASK                                                0x00000040U
11882
11883 /*DQSG Power Down Receiver*/
11884 #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL
11885 #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
11886 #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK
11887 #define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                                             0x40200204
11888 #define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                                              5
11889 #define DDR_PHY_DX4GCR0_DQSGPDR_MASK                                               0x00000020U
11890
11891 /*Reserved. Return zeroes on reads.*/
11892 #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL
11893 #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
11894 #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK
11895 #define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                                          0x40200204
11896 #define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                                           4
11897 #define DDR_PHY_DX4GCR0_RESERVED_4_MASK                                            0x00000010U
11898
11899 /*DQSG On-Die Termination*/
11900 #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL
11901 #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT
11902 #undef DDR_PHY_DX4GCR0_DQSGODT_MASK
11903 #define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                                             0x40200204
11904 #define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                                              3
11905 #define DDR_PHY_DX4GCR0_DQSGODT_MASK                                               0x00000008U
11906
11907 /*DQSG Output Enable*/
11908 #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL
11909 #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT
11910 #undef DDR_PHY_DX4GCR0_DQSGOE_MASK
11911 #define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                                              0x40200204
11912 #define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                                               2
11913 #define DDR_PHY_DX4GCR0_DQSGOE_MASK                                                0x00000004U
11914
11915 /*Reserved. Return zeroes on reads.*/
11916 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL
11917 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
11918 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK
11919 #define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
11920 #define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                                         0
11921 #define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                                          0x00000003U
11922
11923 /*Enables the PDR mode for DQ[7:0]*/
11924 #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL
11925 #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
11926 #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK
11927 #define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
11928 #define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                                            16
11929 #define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
11930
11931 /*Reserved. Returns zeroes on reads.*/
11932 #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL
11933 #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
11934 #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK
11935 #define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
11936 #define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                                          15
11937 #define DDR_PHY_DX4GCR1_RESERVED_15_MASK                                           0x00008000U
11938
11939 /*Select the delayed or non-delayed read data strobe #*/
11940 #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL
11941 #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT
11942 #undef DDR_PHY_DX4GCR1_QSNSEL_MASK
11943 #define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                                              0x00007FFF
11944 #define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                                               14
11945 #define DDR_PHY_DX4GCR1_QSNSEL_MASK                                                0x00004000U
11946
11947 /*Select the delayed or non-delayed read data strobe*/
11948 #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL
11949 #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT
11950 #undef DDR_PHY_DX4GCR1_QSSEL_MASK
11951 #define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                                               0x00007FFF
11952 #define DDR_PHY_DX4GCR1_QSSEL_SHIFT                                                13
11953 #define DDR_PHY_DX4GCR1_QSSEL_MASK                                                 0x00002000U
11954
11955 /*Enables Read Data Strobe in a byte lane*/
11956 #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL
11957 #undef DDR_PHY_DX4GCR1_OEEN_SHIFT
11958 #undef DDR_PHY_DX4GCR1_OEEN_MASK
11959 #define DDR_PHY_DX4GCR1_OEEN_DEFVAL                                                0x00007FFF
11960 #define DDR_PHY_DX4GCR1_OEEN_SHIFT                                                 12
11961 #define DDR_PHY_DX4GCR1_OEEN_MASK                                                  0x00001000U
11962
11963 /*Enables PDR in a byte lane*/
11964 #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL
11965 #undef DDR_PHY_DX4GCR1_PDREN_SHIFT
11966 #undef DDR_PHY_DX4GCR1_PDREN_MASK
11967 #define DDR_PHY_DX4GCR1_PDREN_DEFVAL                                               0x00007FFF
11968 #define DDR_PHY_DX4GCR1_PDREN_SHIFT                                                11
11969 #define DDR_PHY_DX4GCR1_PDREN_MASK                                                 0x00000800U
11970
11971 /*Enables ODT/TE in a byte lane*/
11972 #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL
11973 #undef DDR_PHY_DX4GCR1_TEEN_SHIFT
11974 #undef DDR_PHY_DX4GCR1_TEEN_MASK
11975 #define DDR_PHY_DX4GCR1_TEEN_DEFVAL                                                0x00007FFF
11976 #define DDR_PHY_DX4GCR1_TEEN_SHIFT                                                 10
11977 #define DDR_PHY_DX4GCR1_TEEN_MASK                                                  0x00000400U
11978
11979 /*Enables Write Data strobe in a byte lane*/
11980 #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL
11981 #undef DDR_PHY_DX4GCR1_DSEN_SHIFT
11982 #undef DDR_PHY_DX4GCR1_DSEN_MASK
11983 #define DDR_PHY_DX4GCR1_DSEN_DEFVAL                                                0x00007FFF
11984 #define DDR_PHY_DX4GCR1_DSEN_SHIFT                                                 9
11985 #define DDR_PHY_DX4GCR1_DSEN_MASK                                                  0x00000200U
11986
11987 /*Enables DM pin in a byte lane*/
11988 #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL
11989 #undef DDR_PHY_DX4GCR1_DMEN_SHIFT
11990 #undef DDR_PHY_DX4GCR1_DMEN_MASK
11991 #define DDR_PHY_DX4GCR1_DMEN_DEFVAL                                                0x00007FFF
11992 #define DDR_PHY_DX4GCR1_DMEN_SHIFT                                                 8
11993 #define DDR_PHY_DX4GCR1_DMEN_MASK                                                  0x00000100U
11994
11995 /*Enables DQ corresponding to each bit in a byte*/
11996 #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL
11997 #undef DDR_PHY_DX4GCR1_DQEN_SHIFT
11998 #undef DDR_PHY_DX4GCR1_DQEN_MASK
11999 #define DDR_PHY_DX4GCR1_DQEN_DEFVAL                                                0x00007FFF
12000 #define DDR_PHY_DX4GCR1_DQEN_SHIFT                                                 0
12001 #define DDR_PHY_DX4GCR1_DQEN_MASK                                                  0x000000FFU
12002
12003 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
12004 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL
12005 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
12006 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK
12007 #define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
12008 #define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                                       29
12009 #define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                                        0xE0000000U
12010
12011 /*Byte Lane VREF Pad Enable*/
12012 #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL
12013 #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
12014 #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK
12015 #define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
12016 #define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                                             28
12017 #define DDR_PHY_DX4GCR4_DXREFPEN_MASK                                              0x10000000U
12018
12019 /*Byte Lane Internal VREF Enable*/
12020 #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL
12021 #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
12022 #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK
12023 #define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
12024 #define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                                             26
12025 #define DDR_PHY_DX4GCR4_DXREFEEN_MASK                                              0x0C000000U
12026
12027 /*Byte Lane Single-End VREF Enable*/
12028 #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL
12029 #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
12030 #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK
12031 #define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
12032 #define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                                             25
12033 #define DDR_PHY_DX4GCR4_DXREFSEN_MASK                                              0x02000000U
12034
12035 /*Reserved. Returns zeros on reads.*/
12036 #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL
12037 #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
12038 #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK
12039 #define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
12040 #define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                                          24
12041 #define DDR_PHY_DX4GCR4_RESERVED_24_MASK                                           0x01000000U
12042
12043 /*External VREF generator REFSEL range select*/
12044 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL
12045 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
12046 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK
12047 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
12048 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                                       23
12049 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                                        0x00800000U
12050
12051 /*Byte Lane External VREF Select*/
12052 #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL
12053 #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
12054 #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK
12055 #define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
12056 #define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                                            16
12057 #define DDR_PHY_DX4GCR4_DXREFESEL_MASK                                             0x007F0000U
12058
12059 /*Single ended VREF generator REFSEL range select*/
12060 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL
12061 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
12062 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK
12063 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
12064 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                                       15
12065 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
12066
12067 /*Byte Lane Single-End VREF Select*/
12068 #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL
12069 #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
12070 #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK
12071 #define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
12072 #define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                                            8
12073 #define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                                             0x00007F00U
12074
12075 /*Reserved. Returns zeros on reads.*/
12076 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL
12077 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
12078 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK
12079 #define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
12080 #define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                                         6
12081 #define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                                          0x000000C0U
12082
12083 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12084 #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL
12085 #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
12086 #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK
12087 #define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
12088 #define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                                             2
12089 #define DDR_PHY_DX4GCR4_DXREFIEN_MASK                                              0x0000003CU
12090
12091 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12092 #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL
12093 #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
12094 #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK
12095 #define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
12096 #define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                                            0
12097 #define DDR_PHY_DX4GCR4_DXREFIMON_MASK                                             0x00000003U
12098
12099 /*Reserved. Returns zeros on reads.*/
12100 #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL
12101 #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
12102 #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK
12103 #define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                                         0x09090909
12104 #define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                                          31
12105 #define DDR_PHY_DX4GCR5_RESERVED_31_MASK                                           0x80000000U
12106
12107 /*Byte Lane internal VREF Select for Rank 3*/
12108 #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL
12109 #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
12110 #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK
12111 #define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                                         0x09090909
12112 #define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                                          24
12113 #define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                                           0x7F000000U
12114
12115 /*Reserved. Returns zeros on reads.*/
12116 #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL
12117 #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
12118 #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK
12119 #define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                                         0x09090909
12120 #define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                                          23
12121 #define DDR_PHY_DX4GCR5_RESERVED_23_MASK                                           0x00800000U
12122
12123 /*Byte Lane internal VREF Select for Rank 2*/
12124 #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL
12125 #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
12126 #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK
12127 #define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                                         0x09090909
12128 #define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                                          16
12129 #define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                                           0x007F0000U
12130
12131 /*Reserved. Returns zeros on reads.*/
12132 #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL
12133 #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
12134 #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK
12135 #define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                                         0x09090909
12136 #define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                                          15
12137 #define DDR_PHY_DX4GCR5_RESERVED_15_MASK                                           0x00008000U
12138
12139 /*Byte Lane internal VREF Select for Rank 1*/
12140 #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL
12141 #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
12142 #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK
12143 #define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                                         0x09090909
12144 #define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                                          8
12145 #define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                                           0x00007F00U
12146
12147 /*Reserved. Returns zeros on reads.*/
12148 #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL
12149 #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
12150 #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK
12151 #define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                                          0x09090909
12152 #define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                                           7
12153 #define DDR_PHY_DX4GCR5_RESERVED_7_MASK                                            0x00000080U
12154
12155 /*Byte Lane internal VREF Select for Rank 0*/
12156 #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL
12157 #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
12158 #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK
12159 #define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                                         0x09090909
12160 #define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                                          0
12161 #define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                                           0x0000007FU
12162
12163 /*Reserved. Returns zeros on reads.*/
12164 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL
12165 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
12166 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK
12167 #define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
12168 #define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                                       30
12169 #define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                                        0xC0000000U
12170
12171 /*DRAM DQ VREF Select for Rank3*/
12172 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL
12173 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
12174 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK
12175 #define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
12176 #define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                                           24
12177 #define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                                            0x3F000000U
12178
12179 /*Reserved. Returns zeros on reads.*/
12180 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL
12181 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
12182 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK
12183 #define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
12184 #define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                                       22
12185 #define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                                        0x00C00000U
12186
12187 /*DRAM DQ VREF Select for Rank2*/
12188 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL
12189 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
12190 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK
12191 #define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
12192 #define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                                           16
12193 #define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                                            0x003F0000U
12194
12195 /*Reserved. Returns zeros on reads.*/
12196 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL
12197 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
12198 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK
12199 #define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
12200 #define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                                       14
12201 #define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                                        0x0000C000U
12202
12203 /*DRAM DQ VREF Select for Rank1*/
12204 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL
12205 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
12206 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK
12207 #define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
12208 #define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                                           8
12209 #define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                                            0x00003F00U
12210
12211 /*Reserved. Returns zeros on reads.*/
12212 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL
12213 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
12214 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK
12215 #define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
12216 #define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                                         6
12217 #define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                                          0x000000C0U
12218
12219 /*DRAM DQ VREF Select for Rank0*/
12220 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL
12221 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
12222 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK
12223 #define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
12224 #define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                                           0
12225 #define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                                            0x0000003FU
12226
12227 /*Reserved. Return zeroes on reads.*/
12228 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL
12229 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
12230 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK
12231 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
12232 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT                                     25
12233 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
12234
12235 /*Reserved. Caution, do not write to this register field.*/
12236 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL
12237 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
12238 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK
12239 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
12240 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT                                     16
12241 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
12242
12243 /*Reserved. Return zeroes on reads.*/
12244 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL
12245 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
12246 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK
12247 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
12248 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT                                      9
12249 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
12250
12251 /*Read DQS Gating Delay*/
12252 #undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL
12253 #undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
12254 #undef DDR_PHY_DX4LCDLR2_DQSGD_MASK
12255 #define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL                                             0x00000000
12256 #define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT                                              0
12257 #define DDR_PHY_DX4LCDLR2_DQSGD_MASK                                               0x000001FFU
12258
12259 /*Reserved. Return zeroes on reads.*/
12260 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL
12261 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
12262 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK
12263 #define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
12264 #define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT                                       27
12265 #define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK                                        0xF8000000U
12266
12267 /*DQ Write Path Latency Pipeline*/
12268 #undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL
12269 #undef DDR_PHY_DX4GTR0_WDQSL_SHIFT
12270 #undef DDR_PHY_DX4GTR0_WDQSL_MASK
12271 #define DDR_PHY_DX4GTR0_WDQSL_DEFVAL                                               0x00020000
12272 #define DDR_PHY_DX4GTR0_WDQSL_SHIFT                                                24
12273 #define DDR_PHY_DX4GTR0_WDQSL_MASK                                                 0x07000000U
12274
12275 /*Reserved. Caution, do not write to this register field.*/
12276 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL
12277 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
12278 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK
12279 #define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
12280 #define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT                                       20
12281 #define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK                                        0x00F00000U
12282
12283 /*Write Leveling System Latency*/
12284 #undef DDR_PHY_DX4GTR0_WLSL_DEFVAL
12285 #undef DDR_PHY_DX4GTR0_WLSL_SHIFT
12286 #undef DDR_PHY_DX4GTR0_WLSL_MASK
12287 #define DDR_PHY_DX4GTR0_WLSL_DEFVAL                                                0x00020000
12288 #define DDR_PHY_DX4GTR0_WLSL_SHIFT                                                 16
12289 #define DDR_PHY_DX4GTR0_WLSL_MASK                                                  0x000F0000U
12290
12291 /*Reserved. Return zeroes on reads.*/
12292 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL
12293 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
12294 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK
12295 #define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
12296 #define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT                                       13
12297 #define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK                                        0x0000E000U
12298
12299 /*Reserved. Caution, do not write to this register field.*/
12300 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL
12301 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
12302 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK
12303 #define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
12304 #define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT                                        8
12305 #define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK                                         0x00001F00U
12306
12307 /*Reserved. Return zeroes on reads.*/
12308 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL
12309 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
12310 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK
12311 #define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
12312 #define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT                                         5
12313 #define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK                                          0x000000E0U
12314
12315 /*DQS Gating System Latency*/
12316 #undef DDR_PHY_DX4GTR0_DGSL_DEFVAL
12317 #undef DDR_PHY_DX4GTR0_DGSL_SHIFT
12318 #undef DDR_PHY_DX4GTR0_DGSL_MASK
12319 #define DDR_PHY_DX4GTR0_DGSL_DEFVAL                                                0x00020000
12320 #define DDR_PHY_DX4GTR0_DGSL_SHIFT                                                 0
12321 #define DDR_PHY_DX4GTR0_DGSL_MASK                                                  0x0000001FU
12322
12323 /*Calibration Bypass*/
12324 #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL
12325 #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT
12326 #undef DDR_PHY_DX5GCR0_CALBYP_MASK
12327 #define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                                              0x40200204
12328 #define DDR_PHY_DX5GCR0_CALBYP_SHIFT                                               31
12329 #define DDR_PHY_DX5GCR0_CALBYP_MASK                                                0x80000000U
12330
12331 /*Master Delay Line Enable*/
12332 #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL
12333 #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT
12334 #undef DDR_PHY_DX5GCR0_MDLEN_MASK
12335 #define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                                               0x40200204
12336 #define DDR_PHY_DX5GCR0_MDLEN_SHIFT                                                30
12337 #define DDR_PHY_DX5GCR0_MDLEN_MASK                                                 0x40000000U
12338
12339 /*Configurable ODT(TE) Phase Shift*/
12340 #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL
12341 #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
12342 #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK
12343 #define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                                            0x40200204
12344 #define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                                             28
12345 #define DDR_PHY_DX5GCR0_CODTSHFT_MASK                                              0x30000000U
12346
12347 /*DQS Duty Cycle Correction*/
12348 #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL
12349 #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT
12350 #undef DDR_PHY_DX5GCR0_DQSDCC_MASK
12351 #define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                                              0x40200204
12352 #define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                                               24
12353 #define DDR_PHY_DX5GCR0_DQSDCC_MASK                                                0x0F000000U
12354
12355 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12356 #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL
12357 #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT
12358 #undef DDR_PHY_DX5GCR0_RDDLY_MASK
12359 #define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                                               0x40200204
12360 #define DDR_PHY_DX5GCR0_RDDLY_SHIFT                                                20
12361 #define DDR_PHY_DX5GCR0_RDDLY_MASK                                                 0x00F00000U
12362
12363 /*Reserved. Return zeroes on reads.*/
12364 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL
12365 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
12366 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK
12367 #define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
12368 #define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                                       14
12369 #define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                                        0x000FC000U
12370
12371 /*DQSNSE Power Down Receiver*/
12372 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL
12373 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
12374 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK
12375 #define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
12376 #define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                                            13
12377 #define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                                             0x00002000U
12378
12379 /*DQSSE Power Down Receiver*/
12380 #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL
12381 #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
12382 #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK
12383 #define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                                            0x40200204
12384 #define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                                             12
12385 #define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                                              0x00001000U
12386
12387 /*RTT On Additive Latency*/
12388 #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL
12389 #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT
12390 #undef DDR_PHY_DX5GCR0_RTTOAL_MASK
12391 #define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                                              0x40200204
12392 #define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                                               11
12393 #define DDR_PHY_DX5GCR0_RTTOAL_MASK                                                0x00000800U
12394
12395 /*RTT Output Hold*/
12396 #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL
12397 #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT
12398 #undef DDR_PHY_DX5GCR0_RTTOH_MASK
12399 #define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                                               0x40200204
12400 #define DDR_PHY_DX5GCR0_RTTOH_SHIFT                                                9
12401 #define DDR_PHY_DX5GCR0_RTTOH_MASK                                                 0x00000600U
12402
12403 /*Configurable PDR Phase Shift*/
12404 #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL
12405 #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
12406 #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK
12407 #define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                                            0x40200204
12408 #define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                                             7
12409 #define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                                              0x00000180U
12410
12411 /*DQSR Power Down*/
12412 #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL
12413 #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT
12414 #undef DDR_PHY_DX5GCR0_DQSRPD_MASK
12415 #define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                                              0x40200204
12416 #define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                                               6
12417 #define DDR_PHY_DX5GCR0_DQSRPD_MASK                                                0x00000040U
12418
12419 /*DQSG Power Down Receiver*/
12420 #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL
12421 #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
12422 #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK
12423 #define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                                             0x40200204
12424 #define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                                              5
12425 #define DDR_PHY_DX5GCR0_DQSGPDR_MASK                                               0x00000020U
12426
12427 /*Reserved. Return zeroes on reads.*/
12428 #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL
12429 #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
12430 #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK
12431 #define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                                          0x40200204
12432 #define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                                           4
12433 #define DDR_PHY_DX5GCR0_RESERVED_4_MASK                                            0x00000010U
12434
12435 /*DQSG On-Die Termination*/
12436 #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL
12437 #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT
12438 #undef DDR_PHY_DX5GCR0_DQSGODT_MASK
12439 #define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                                             0x40200204
12440 #define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                                              3
12441 #define DDR_PHY_DX5GCR0_DQSGODT_MASK                                               0x00000008U
12442
12443 /*DQSG Output Enable*/
12444 #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL
12445 #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT
12446 #undef DDR_PHY_DX5GCR0_DQSGOE_MASK
12447 #define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                                              0x40200204
12448 #define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                                               2
12449 #define DDR_PHY_DX5GCR0_DQSGOE_MASK                                                0x00000004U
12450
12451 /*Reserved. Return zeroes on reads.*/
12452 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL
12453 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
12454 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK
12455 #define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
12456 #define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                                         0
12457 #define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                                          0x00000003U
12458
12459 /*Enables the PDR mode for DQ[7:0]*/
12460 #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL
12461 #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
12462 #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK
12463 #define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
12464 #define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                                            16
12465 #define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
12466
12467 /*Reserved. Returns zeroes on reads.*/
12468 #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL
12469 #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
12470 #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK
12471 #define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
12472 #define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                                          15
12473 #define DDR_PHY_DX5GCR1_RESERVED_15_MASK                                           0x00008000U
12474
12475 /*Select the delayed or non-delayed read data strobe #*/
12476 #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL
12477 #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT
12478 #undef DDR_PHY_DX5GCR1_QSNSEL_MASK
12479 #define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                                              0x00007FFF
12480 #define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                                               14
12481 #define DDR_PHY_DX5GCR1_QSNSEL_MASK                                                0x00004000U
12482
12483 /*Select the delayed or non-delayed read data strobe*/
12484 #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL
12485 #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT
12486 #undef DDR_PHY_DX5GCR1_QSSEL_MASK
12487 #define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                                               0x00007FFF
12488 #define DDR_PHY_DX5GCR1_QSSEL_SHIFT                                                13
12489 #define DDR_PHY_DX5GCR1_QSSEL_MASK                                                 0x00002000U
12490
12491 /*Enables Read Data Strobe in a byte lane*/
12492 #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL
12493 #undef DDR_PHY_DX5GCR1_OEEN_SHIFT
12494 #undef DDR_PHY_DX5GCR1_OEEN_MASK
12495 #define DDR_PHY_DX5GCR1_OEEN_DEFVAL                                                0x00007FFF
12496 #define DDR_PHY_DX5GCR1_OEEN_SHIFT                                                 12
12497 #define DDR_PHY_DX5GCR1_OEEN_MASK                                                  0x00001000U
12498
12499 /*Enables PDR in a byte lane*/
12500 #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL
12501 #undef DDR_PHY_DX5GCR1_PDREN_SHIFT
12502 #undef DDR_PHY_DX5GCR1_PDREN_MASK
12503 #define DDR_PHY_DX5GCR1_PDREN_DEFVAL                                               0x00007FFF
12504 #define DDR_PHY_DX5GCR1_PDREN_SHIFT                                                11
12505 #define DDR_PHY_DX5GCR1_PDREN_MASK                                                 0x00000800U
12506
12507 /*Enables ODT/TE in a byte lane*/
12508 #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL
12509 #undef DDR_PHY_DX5GCR1_TEEN_SHIFT
12510 #undef DDR_PHY_DX5GCR1_TEEN_MASK
12511 #define DDR_PHY_DX5GCR1_TEEN_DEFVAL                                                0x00007FFF
12512 #define DDR_PHY_DX5GCR1_TEEN_SHIFT                                                 10
12513 #define DDR_PHY_DX5GCR1_TEEN_MASK                                                  0x00000400U
12514
12515 /*Enables Write Data strobe in a byte lane*/
12516 #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL
12517 #undef DDR_PHY_DX5GCR1_DSEN_SHIFT
12518 #undef DDR_PHY_DX5GCR1_DSEN_MASK
12519 #define DDR_PHY_DX5GCR1_DSEN_DEFVAL                                                0x00007FFF
12520 #define DDR_PHY_DX5GCR1_DSEN_SHIFT                                                 9
12521 #define DDR_PHY_DX5GCR1_DSEN_MASK                                                  0x00000200U
12522
12523 /*Enables DM pin in a byte lane*/
12524 #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL
12525 #undef DDR_PHY_DX5GCR1_DMEN_SHIFT
12526 #undef DDR_PHY_DX5GCR1_DMEN_MASK
12527 #define DDR_PHY_DX5GCR1_DMEN_DEFVAL                                                0x00007FFF
12528 #define DDR_PHY_DX5GCR1_DMEN_SHIFT                                                 8
12529 #define DDR_PHY_DX5GCR1_DMEN_MASK                                                  0x00000100U
12530
12531 /*Enables DQ corresponding to each bit in a byte*/
12532 #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL
12533 #undef DDR_PHY_DX5GCR1_DQEN_SHIFT
12534 #undef DDR_PHY_DX5GCR1_DQEN_MASK
12535 #define DDR_PHY_DX5GCR1_DQEN_DEFVAL                                                0x00007FFF
12536 #define DDR_PHY_DX5GCR1_DQEN_SHIFT                                                 0
12537 #define DDR_PHY_DX5GCR1_DQEN_MASK                                                  0x000000FFU
12538
12539 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
12540 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL
12541 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
12542 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK
12543 #define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
12544 #define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                                       29
12545 #define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                                        0xE0000000U
12546
12547 /*Byte Lane VREF Pad Enable*/
12548 #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL
12549 #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
12550 #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK
12551 #define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
12552 #define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                                             28
12553 #define DDR_PHY_DX5GCR4_DXREFPEN_MASK                                              0x10000000U
12554
12555 /*Byte Lane Internal VREF Enable*/
12556 #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL
12557 #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
12558 #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK
12559 #define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
12560 #define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                                             26
12561 #define DDR_PHY_DX5GCR4_DXREFEEN_MASK                                              0x0C000000U
12562
12563 /*Byte Lane Single-End VREF Enable*/
12564 #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL
12565 #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
12566 #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK
12567 #define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
12568 #define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                                             25
12569 #define DDR_PHY_DX5GCR4_DXREFSEN_MASK                                              0x02000000U
12570
12571 /*Reserved. Returns zeros on reads.*/
12572 #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL
12573 #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
12574 #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK
12575 #define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
12576 #define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                                          24
12577 #define DDR_PHY_DX5GCR4_RESERVED_24_MASK                                           0x01000000U
12578
12579 /*External VREF generator REFSEL range select*/
12580 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL
12581 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
12582 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK
12583 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
12584 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                                       23
12585 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                                        0x00800000U
12586
12587 /*Byte Lane External VREF Select*/
12588 #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL
12589 #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
12590 #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK
12591 #define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
12592 #define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                                            16
12593 #define DDR_PHY_DX5GCR4_DXREFESEL_MASK                                             0x007F0000U
12594
12595 /*Single ended VREF generator REFSEL range select*/
12596 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL
12597 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
12598 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK
12599 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
12600 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                                       15
12601 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
12602
12603 /*Byte Lane Single-End VREF Select*/
12604 #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL
12605 #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
12606 #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK
12607 #define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
12608 #define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                                            8
12609 #define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                                             0x00007F00U
12610
12611 /*Reserved. Returns zeros on reads.*/
12612 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL
12613 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
12614 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK
12615 #define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
12616 #define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                                         6
12617 #define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                                          0x000000C0U
12618
12619 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12620 #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL
12621 #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
12622 #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK
12623 #define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
12624 #define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                                             2
12625 #define DDR_PHY_DX5GCR4_DXREFIEN_MASK                                              0x0000003CU
12626
12627 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12628 #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL
12629 #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
12630 #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK
12631 #define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
12632 #define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                                            0
12633 #define DDR_PHY_DX5GCR4_DXREFIMON_MASK                                             0x00000003U
12634
12635 /*Reserved. Returns zeros on reads.*/
12636 #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL
12637 #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
12638 #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK
12639 #define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                                         0x09090909
12640 #define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                                          31
12641 #define DDR_PHY_DX5GCR5_RESERVED_31_MASK                                           0x80000000U
12642
12643 /*Byte Lane internal VREF Select for Rank 3*/
12644 #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL
12645 #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
12646 #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK
12647 #define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                                         0x09090909
12648 #define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                                          24
12649 #define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                                           0x7F000000U
12650
12651 /*Reserved. Returns zeros on reads.*/
12652 #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL
12653 #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
12654 #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK
12655 #define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                                         0x09090909
12656 #define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                                          23
12657 #define DDR_PHY_DX5GCR5_RESERVED_23_MASK                                           0x00800000U
12658
12659 /*Byte Lane internal VREF Select for Rank 2*/
12660 #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL
12661 #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
12662 #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK
12663 #define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                                         0x09090909
12664 #define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                                          16
12665 #define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                                           0x007F0000U
12666
12667 /*Reserved. Returns zeros on reads.*/
12668 #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL
12669 #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
12670 #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK
12671 #define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                                         0x09090909
12672 #define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                                          15
12673 #define DDR_PHY_DX5GCR5_RESERVED_15_MASK                                           0x00008000U
12674
12675 /*Byte Lane internal VREF Select for Rank 1*/
12676 #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL
12677 #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
12678 #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK
12679 #define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                                         0x09090909
12680 #define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                                          8
12681 #define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                                           0x00007F00U
12682
12683 /*Reserved. Returns zeros on reads.*/
12684 #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL
12685 #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
12686 #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK
12687 #define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                                          0x09090909
12688 #define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                                           7
12689 #define DDR_PHY_DX5GCR5_RESERVED_7_MASK                                            0x00000080U
12690
12691 /*Byte Lane internal VREF Select for Rank 0*/
12692 #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL
12693 #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
12694 #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK
12695 #define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                                         0x09090909
12696 #define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                                          0
12697 #define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                                           0x0000007FU
12698
12699 /*Reserved. Returns zeros on reads.*/
12700 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL
12701 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
12702 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK
12703 #define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
12704 #define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                                       30
12705 #define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                                        0xC0000000U
12706
12707 /*DRAM DQ VREF Select for Rank3*/
12708 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL
12709 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
12710 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK
12711 #define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
12712 #define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                                           24
12713 #define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                                            0x3F000000U
12714
12715 /*Reserved. Returns zeros on reads.*/
12716 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL
12717 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
12718 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK
12719 #define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
12720 #define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                                       22
12721 #define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                                        0x00C00000U
12722
12723 /*DRAM DQ VREF Select for Rank2*/
12724 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL
12725 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
12726 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK
12727 #define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
12728 #define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                                           16
12729 #define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                                            0x003F0000U
12730
12731 /*Reserved. Returns zeros on reads.*/
12732 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL
12733 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
12734 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK
12735 #define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
12736 #define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                                       14
12737 #define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                                        0x0000C000U
12738
12739 /*DRAM DQ VREF Select for Rank1*/
12740 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL
12741 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
12742 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK
12743 #define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
12744 #define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                                           8
12745 #define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                                            0x00003F00U
12746
12747 /*Reserved. Returns zeros on reads.*/
12748 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL
12749 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
12750 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK
12751 #define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
12752 #define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                                         6
12753 #define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                                          0x000000C0U
12754
12755 /*DRAM DQ VREF Select for Rank0*/
12756 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL
12757 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
12758 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK
12759 #define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
12760 #define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                                           0
12761 #define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                                            0x0000003FU
12762
12763 /*Reserved. Return zeroes on reads.*/
12764 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL
12765 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
12766 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK
12767 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
12768 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT                                     25
12769 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
12770
12771 /*Reserved. Caution, do not write to this register field.*/
12772 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL
12773 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
12774 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK
12775 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
12776 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT                                     16
12777 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
12778
12779 /*Reserved. Return zeroes on reads.*/
12780 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL
12781 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
12782 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK
12783 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
12784 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT                                      9
12785 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
12786
12787 /*Read DQS Gating Delay*/
12788 #undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL
12789 #undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
12790 #undef DDR_PHY_DX5LCDLR2_DQSGD_MASK
12791 #define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL                                             0x00000000
12792 #define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT                                              0
12793 #define DDR_PHY_DX5LCDLR2_DQSGD_MASK                                               0x000001FFU
12794
12795 /*Reserved. Return zeroes on reads.*/
12796 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL
12797 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
12798 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK
12799 #define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
12800 #define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT                                       27
12801 #define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK                                        0xF8000000U
12802
12803 /*DQ Write Path Latency Pipeline*/
12804 #undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL
12805 #undef DDR_PHY_DX5GTR0_WDQSL_SHIFT
12806 #undef DDR_PHY_DX5GTR0_WDQSL_MASK
12807 #define DDR_PHY_DX5GTR0_WDQSL_DEFVAL                                               0x00020000
12808 #define DDR_PHY_DX5GTR0_WDQSL_SHIFT                                                24
12809 #define DDR_PHY_DX5GTR0_WDQSL_MASK                                                 0x07000000U
12810
12811 /*Reserved. Caution, do not write to this register field.*/
12812 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL
12813 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
12814 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK
12815 #define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
12816 #define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT                                       20
12817 #define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK                                        0x00F00000U
12818
12819 /*Write Leveling System Latency*/
12820 #undef DDR_PHY_DX5GTR0_WLSL_DEFVAL
12821 #undef DDR_PHY_DX5GTR0_WLSL_SHIFT
12822 #undef DDR_PHY_DX5GTR0_WLSL_MASK
12823 #define DDR_PHY_DX5GTR0_WLSL_DEFVAL                                                0x00020000
12824 #define DDR_PHY_DX5GTR0_WLSL_SHIFT                                                 16
12825 #define DDR_PHY_DX5GTR0_WLSL_MASK                                                  0x000F0000U
12826
12827 /*Reserved. Return zeroes on reads.*/
12828 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL
12829 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
12830 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK
12831 #define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
12832 #define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT                                       13
12833 #define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK                                        0x0000E000U
12834
12835 /*Reserved. Caution, do not write to this register field.*/
12836 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL
12837 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
12838 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK
12839 #define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
12840 #define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT                                        8
12841 #define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK                                         0x00001F00U
12842
12843 /*Reserved. Return zeroes on reads.*/
12844 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL
12845 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
12846 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK
12847 #define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
12848 #define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT                                         5
12849 #define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK                                          0x000000E0U
12850
12851 /*DQS Gating System Latency*/
12852 #undef DDR_PHY_DX5GTR0_DGSL_DEFVAL
12853 #undef DDR_PHY_DX5GTR0_DGSL_SHIFT
12854 #undef DDR_PHY_DX5GTR0_DGSL_MASK
12855 #define DDR_PHY_DX5GTR0_DGSL_DEFVAL                                                0x00020000
12856 #define DDR_PHY_DX5GTR0_DGSL_SHIFT                                                 0
12857 #define DDR_PHY_DX5GTR0_DGSL_MASK                                                  0x0000001FU
12858
12859 /*Calibration Bypass*/
12860 #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL
12861 #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT
12862 #undef DDR_PHY_DX6GCR0_CALBYP_MASK
12863 #define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                                              0x40200204
12864 #define DDR_PHY_DX6GCR0_CALBYP_SHIFT                                               31
12865 #define DDR_PHY_DX6GCR0_CALBYP_MASK                                                0x80000000U
12866
12867 /*Master Delay Line Enable*/
12868 #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL
12869 #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT
12870 #undef DDR_PHY_DX6GCR0_MDLEN_MASK
12871 #define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                                               0x40200204
12872 #define DDR_PHY_DX6GCR0_MDLEN_SHIFT                                                30
12873 #define DDR_PHY_DX6GCR0_MDLEN_MASK                                                 0x40000000U
12874
12875 /*Configurable ODT(TE) Phase Shift*/
12876 #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL
12877 #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
12878 #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK
12879 #define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                                            0x40200204
12880 #define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                                             28
12881 #define DDR_PHY_DX6GCR0_CODTSHFT_MASK                                              0x30000000U
12882
12883 /*DQS Duty Cycle Correction*/
12884 #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL
12885 #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT
12886 #undef DDR_PHY_DX6GCR0_DQSDCC_MASK
12887 #define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                                              0x40200204
12888 #define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                                               24
12889 #define DDR_PHY_DX6GCR0_DQSDCC_MASK                                                0x0F000000U
12890
12891 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12892 #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL
12893 #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT
12894 #undef DDR_PHY_DX6GCR0_RDDLY_MASK
12895 #define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                                               0x40200204
12896 #define DDR_PHY_DX6GCR0_RDDLY_SHIFT                                                20
12897 #define DDR_PHY_DX6GCR0_RDDLY_MASK                                                 0x00F00000U
12898
12899 /*Reserved. Return zeroes on reads.*/
12900 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL
12901 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
12902 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK
12903 #define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
12904 #define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                                       14
12905 #define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                                        0x000FC000U
12906
12907 /*DQSNSE Power Down Receiver*/
12908 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL
12909 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
12910 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK
12911 #define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
12912 #define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                                            13
12913 #define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                                             0x00002000U
12914
12915 /*DQSSE Power Down Receiver*/
12916 #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL
12917 #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
12918 #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK
12919 #define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                                            0x40200204
12920 #define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                                             12
12921 #define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                                              0x00001000U
12922
12923 /*RTT On Additive Latency*/
12924 #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL
12925 #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT
12926 #undef DDR_PHY_DX6GCR0_RTTOAL_MASK
12927 #define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                                              0x40200204
12928 #define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                                               11
12929 #define DDR_PHY_DX6GCR0_RTTOAL_MASK                                                0x00000800U
12930
12931 /*RTT Output Hold*/
12932 #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL
12933 #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT
12934 #undef DDR_PHY_DX6GCR0_RTTOH_MASK
12935 #define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                                               0x40200204
12936 #define DDR_PHY_DX6GCR0_RTTOH_SHIFT                                                9
12937 #define DDR_PHY_DX6GCR0_RTTOH_MASK                                                 0x00000600U
12938
12939 /*Configurable PDR Phase Shift*/
12940 #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL
12941 #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
12942 #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK
12943 #define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                                            0x40200204
12944 #define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                                             7
12945 #define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                                              0x00000180U
12946
12947 /*DQSR Power Down*/
12948 #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL
12949 #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT
12950 #undef DDR_PHY_DX6GCR0_DQSRPD_MASK
12951 #define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                                              0x40200204
12952 #define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                                               6
12953 #define DDR_PHY_DX6GCR0_DQSRPD_MASK                                                0x00000040U
12954
12955 /*DQSG Power Down Receiver*/
12956 #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL
12957 #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
12958 #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK
12959 #define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                                             0x40200204
12960 #define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                                              5
12961 #define DDR_PHY_DX6GCR0_DQSGPDR_MASK                                               0x00000020U
12962
12963 /*Reserved. Return zeroes on reads.*/
12964 #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL
12965 #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
12966 #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK
12967 #define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                                          0x40200204
12968 #define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                                           4
12969 #define DDR_PHY_DX6GCR0_RESERVED_4_MASK                                            0x00000010U
12970
12971 /*DQSG On-Die Termination*/
12972 #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL
12973 #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT
12974 #undef DDR_PHY_DX6GCR0_DQSGODT_MASK
12975 #define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                                             0x40200204
12976 #define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                                              3
12977 #define DDR_PHY_DX6GCR0_DQSGODT_MASK                                               0x00000008U
12978
12979 /*DQSG Output Enable*/
12980 #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL
12981 #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT
12982 #undef DDR_PHY_DX6GCR0_DQSGOE_MASK
12983 #define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                                              0x40200204
12984 #define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                                               2
12985 #define DDR_PHY_DX6GCR0_DQSGOE_MASK                                                0x00000004U
12986
12987 /*Reserved. Return zeroes on reads.*/
12988 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL
12989 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
12990 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK
12991 #define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
12992 #define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                                         0
12993 #define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                                          0x00000003U
12994
12995 /*Enables the PDR mode for DQ[7:0]*/
12996 #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL
12997 #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
12998 #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK
12999 #define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
13000 #define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                                            16
13001 #define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
13002
13003 /*Reserved. Returns zeroes on reads.*/
13004 #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL
13005 #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
13006 #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK
13007 #define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
13008 #define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                                          15
13009 #define DDR_PHY_DX6GCR1_RESERVED_15_MASK                                           0x00008000U
13010
13011 /*Select the delayed or non-delayed read data strobe #*/
13012 #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL
13013 #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT
13014 #undef DDR_PHY_DX6GCR1_QSNSEL_MASK
13015 #define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                                              0x00007FFF
13016 #define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                                               14
13017 #define DDR_PHY_DX6GCR1_QSNSEL_MASK                                                0x00004000U
13018
13019 /*Select the delayed or non-delayed read data strobe*/
13020 #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL
13021 #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT
13022 #undef DDR_PHY_DX6GCR1_QSSEL_MASK
13023 #define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                                               0x00007FFF
13024 #define DDR_PHY_DX6GCR1_QSSEL_SHIFT                                                13
13025 #define DDR_PHY_DX6GCR1_QSSEL_MASK                                                 0x00002000U
13026
13027 /*Enables Read Data Strobe in a byte lane*/
13028 #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL
13029 #undef DDR_PHY_DX6GCR1_OEEN_SHIFT
13030 #undef DDR_PHY_DX6GCR1_OEEN_MASK
13031 #define DDR_PHY_DX6GCR1_OEEN_DEFVAL                                                0x00007FFF
13032 #define DDR_PHY_DX6GCR1_OEEN_SHIFT                                                 12
13033 #define DDR_PHY_DX6GCR1_OEEN_MASK                                                  0x00001000U
13034
13035 /*Enables PDR in a byte lane*/
13036 #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL
13037 #undef DDR_PHY_DX6GCR1_PDREN_SHIFT
13038 #undef DDR_PHY_DX6GCR1_PDREN_MASK
13039 #define DDR_PHY_DX6GCR1_PDREN_DEFVAL                                               0x00007FFF
13040 #define DDR_PHY_DX6GCR1_PDREN_SHIFT                                                11
13041 #define DDR_PHY_DX6GCR1_PDREN_MASK                                                 0x00000800U
13042
13043 /*Enables ODT/TE in a byte lane*/
13044 #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL
13045 #undef DDR_PHY_DX6GCR1_TEEN_SHIFT
13046 #undef DDR_PHY_DX6GCR1_TEEN_MASK
13047 #define DDR_PHY_DX6GCR1_TEEN_DEFVAL                                                0x00007FFF
13048 #define DDR_PHY_DX6GCR1_TEEN_SHIFT                                                 10
13049 #define DDR_PHY_DX6GCR1_TEEN_MASK                                                  0x00000400U
13050
13051 /*Enables Write Data strobe in a byte lane*/
13052 #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL
13053 #undef DDR_PHY_DX6GCR1_DSEN_SHIFT
13054 #undef DDR_PHY_DX6GCR1_DSEN_MASK
13055 #define DDR_PHY_DX6GCR1_DSEN_DEFVAL                                                0x00007FFF
13056 #define DDR_PHY_DX6GCR1_DSEN_SHIFT                                                 9
13057 #define DDR_PHY_DX6GCR1_DSEN_MASK                                                  0x00000200U
13058
13059 /*Enables DM pin in a byte lane*/
13060 #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL
13061 #undef DDR_PHY_DX6GCR1_DMEN_SHIFT
13062 #undef DDR_PHY_DX6GCR1_DMEN_MASK
13063 #define DDR_PHY_DX6GCR1_DMEN_DEFVAL                                                0x00007FFF
13064 #define DDR_PHY_DX6GCR1_DMEN_SHIFT                                                 8
13065 #define DDR_PHY_DX6GCR1_DMEN_MASK                                                  0x00000100U
13066
13067 /*Enables DQ corresponding to each bit in a byte*/
13068 #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL
13069 #undef DDR_PHY_DX6GCR1_DQEN_SHIFT
13070 #undef DDR_PHY_DX6GCR1_DQEN_MASK
13071 #define DDR_PHY_DX6GCR1_DQEN_DEFVAL                                                0x00007FFF
13072 #define DDR_PHY_DX6GCR1_DQEN_SHIFT                                                 0
13073 #define DDR_PHY_DX6GCR1_DQEN_MASK                                                  0x000000FFU
13074
13075 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
13076 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL
13077 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
13078 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK
13079 #define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
13080 #define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                                       29
13081 #define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                                        0xE0000000U
13082
13083 /*Byte Lane VREF Pad Enable*/
13084 #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL
13085 #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
13086 #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK
13087 #define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
13088 #define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                                             28
13089 #define DDR_PHY_DX6GCR4_DXREFPEN_MASK                                              0x10000000U
13090
13091 /*Byte Lane Internal VREF Enable*/
13092 #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL
13093 #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
13094 #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK
13095 #define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
13096 #define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                                             26
13097 #define DDR_PHY_DX6GCR4_DXREFEEN_MASK                                              0x0C000000U
13098
13099 /*Byte Lane Single-End VREF Enable*/
13100 #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL
13101 #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
13102 #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK
13103 #define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
13104 #define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                                             25
13105 #define DDR_PHY_DX6GCR4_DXREFSEN_MASK                                              0x02000000U
13106
13107 /*Reserved. Returns zeros on reads.*/
13108 #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL
13109 #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
13110 #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK
13111 #define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
13112 #define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                                          24
13113 #define DDR_PHY_DX6GCR4_RESERVED_24_MASK                                           0x01000000U
13114
13115 /*External VREF generator REFSEL range select*/
13116 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL
13117 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
13118 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK
13119 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
13120 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                                       23
13121 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                                        0x00800000U
13122
13123 /*Byte Lane External VREF Select*/
13124 #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL
13125 #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
13126 #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK
13127 #define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
13128 #define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                                            16
13129 #define DDR_PHY_DX6GCR4_DXREFESEL_MASK                                             0x007F0000U
13130
13131 /*Single ended VREF generator REFSEL range select*/
13132 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL
13133 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
13134 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK
13135 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
13136 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                                       15
13137 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
13138
13139 /*Byte Lane Single-End VREF Select*/
13140 #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL
13141 #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
13142 #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK
13143 #define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
13144 #define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                                            8
13145 #define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                                             0x00007F00U
13146
13147 /*Reserved. Returns zeros on reads.*/
13148 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL
13149 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
13150 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK
13151 #define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
13152 #define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                                         6
13153 #define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                                          0x000000C0U
13154
13155 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13156 #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL
13157 #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
13158 #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK
13159 #define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
13160 #define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                                             2
13161 #define DDR_PHY_DX6GCR4_DXREFIEN_MASK                                              0x0000003CU
13162
13163 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13164 #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL
13165 #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
13166 #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK
13167 #define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
13168 #define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                                            0
13169 #define DDR_PHY_DX6GCR4_DXREFIMON_MASK                                             0x00000003U
13170
13171 /*Reserved. Returns zeros on reads.*/
13172 #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL
13173 #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
13174 #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK
13175 #define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                                         0x09090909
13176 #define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                                          31
13177 #define DDR_PHY_DX6GCR5_RESERVED_31_MASK                                           0x80000000U
13178
13179 /*Byte Lane internal VREF Select for Rank 3*/
13180 #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL
13181 #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
13182 #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK
13183 #define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                                         0x09090909
13184 #define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                                          24
13185 #define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                                           0x7F000000U
13186
13187 /*Reserved. Returns zeros on reads.*/
13188 #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL
13189 #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
13190 #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK
13191 #define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                                         0x09090909
13192 #define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                                          23
13193 #define DDR_PHY_DX6GCR5_RESERVED_23_MASK                                           0x00800000U
13194
13195 /*Byte Lane internal VREF Select for Rank 2*/
13196 #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL
13197 #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
13198 #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK
13199 #define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                                         0x09090909
13200 #define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                                          16
13201 #define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                                           0x007F0000U
13202
13203 /*Reserved. Returns zeros on reads.*/
13204 #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL
13205 #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
13206 #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK
13207 #define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                                         0x09090909
13208 #define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                                          15
13209 #define DDR_PHY_DX6GCR5_RESERVED_15_MASK                                           0x00008000U
13210
13211 /*Byte Lane internal VREF Select for Rank 1*/
13212 #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL
13213 #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
13214 #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK
13215 #define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                                         0x09090909
13216 #define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                                          8
13217 #define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                                           0x00007F00U
13218
13219 /*Reserved. Returns zeros on reads.*/
13220 #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL
13221 #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
13222 #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK
13223 #define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                                          0x09090909
13224 #define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                                           7
13225 #define DDR_PHY_DX6GCR5_RESERVED_7_MASK                                            0x00000080U
13226
13227 /*Byte Lane internal VREF Select for Rank 0*/
13228 #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL
13229 #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
13230 #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK
13231 #define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                                         0x09090909
13232 #define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                                          0
13233 #define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                                           0x0000007FU
13234
13235 /*Reserved. Returns zeros on reads.*/
13236 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL
13237 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
13238 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK
13239 #define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
13240 #define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                                       30
13241 #define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                                        0xC0000000U
13242
13243 /*DRAM DQ VREF Select for Rank3*/
13244 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL
13245 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
13246 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK
13247 #define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
13248 #define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                                           24
13249 #define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                                            0x3F000000U
13250
13251 /*Reserved. Returns zeros on reads.*/
13252 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL
13253 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
13254 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK
13255 #define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
13256 #define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                                       22
13257 #define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                                        0x00C00000U
13258
13259 /*DRAM DQ VREF Select for Rank2*/
13260 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL
13261 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
13262 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK
13263 #define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
13264 #define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                                           16
13265 #define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                                            0x003F0000U
13266
13267 /*Reserved. Returns zeros on reads.*/
13268 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL
13269 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
13270 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK
13271 #define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
13272 #define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                                       14
13273 #define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                                        0x0000C000U
13274
13275 /*DRAM DQ VREF Select for Rank1*/
13276 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL
13277 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
13278 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK
13279 #define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
13280 #define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                                           8
13281 #define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                                            0x00003F00U
13282
13283 /*Reserved. Returns zeros on reads.*/
13284 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL
13285 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
13286 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK
13287 #define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
13288 #define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                                         6
13289 #define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                                          0x000000C0U
13290
13291 /*DRAM DQ VREF Select for Rank0*/
13292 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL
13293 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
13294 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK
13295 #define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
13296 #define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                                           0
13297 #define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                                            0x0000003FU
13298
13299 /*Reserved. Return zeroes on reads.*/
13300 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL
13301 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
13302 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK
13303 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
13304 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT                                     25
13305 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
13306
13307 /*Reserved. Caution, do not write to this register field.*/
13308 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL
13309 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
13310 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK
13311 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
13312 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT                                     16
13313 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
13314
13315 /*Reserved. Return zeroes on reads.*/
13316 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL
13317 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
13318 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK
13319 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
13320 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT                                      9
13321 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
13322
13323 /*Read DQS Gating Delay*/
13324 #undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL
13325 #undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
13326 #undef DDR_PHY_DX6LCDLR2_DQSGD_MASK
13327 #define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL                                             0x00000000
13328 #define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT                                              0
13329 #define DDR_PHY_DX6LCDLR2_DQSGD_MASK                                               0x000001FFU
13330
13331 /*Reserved. Return zeroes on reads.*/
13332 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL
13333 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
13334 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK
13335 #define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
13336 #define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT                                       27
13337 #define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK                                        0xF8000000U
13338
13339 /*DQ Write Path Latency Pipeline*/
13340 #undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL
13341 #undef DDR_PHY_DX6GTR0_WDQSL_SHIFT
13342 #undef DDR_PHY_DX6GTR0_WDQSL_MASK
13343 #define DDR_PHY_DX6GTR0_WDQSL_DEFVAL                                               0x00020000
13344 #define DDR_PHY_DX6GTR0_WDQSL_SHIFT                                                24
13345 #define DDR_PHY_DX6GTR0_WDQSL_MASK                                                 0x07000000U
13346
13347 /*Reserved. Caution, do not write to this register field.*/
13348 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL
13349 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
13350 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK
13351 #define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
13352 #define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT                                       20
13353 #define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK                                        0x00F00000U
13354
13355 /*Write Leveling System Latency*/
13356 #undef DDR_PHY_DX6GTR0_WLSL_DEFVAL
13357 #undef DDR_PHY_DX6GTR0_WLSL_SHIFT
13358 #undef DDR_PHY_DX6GTR0_WLSL_MASK
13359 #define DDR_PHY_DX6GTR0_WLSL_DEFVAL                                                0x00020000
13360 #define DDR_PHY_DX6GTR0_WLSL_SHIFT                                                 16
13361 #define DDR_PHY_DX6GTR0_WLSL_MASK                                                  0x000F0000U
13362
13363 /*Reserved. Return zeroes on reads.*/
13364 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL
13365 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
13366 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK
13367 #define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
13368 #define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT                                       13
13369 #define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK                                        0x0000E000U
13370
13371 /*Reserved. Caution, do not write to this register field.*/
13372 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL
13373 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
13374 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK
13375 #define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
13376 #define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT                                        8
13377 #define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK                                         0x00001F00U
13378
13379 /*Reserved. Return zeroes on reads.*/
13380 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL
13381 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
13382 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK
13383 #define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
13384 #define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT                                         5
13385 #define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK                                          0x000000E0U
13386
13387 /*DQS Gating System Latency*/
13388 #undef DDR_PHY_DX6GTR0_DGSL_DEFVAL
13389 #undef DDR_PHY_DX6GTR0_DGSL_SHIFT
13390 #undef DDR_PHY_DX6GTR0_DGSL_MASK
13391 #define DDR_PHY_DX6GTR0_DGSL_DEFVAL                                                0x00020000
13392 #define DDR_PHY_DX6GTR0_DGSL_SHIFT                                                 0
13393 #define DDR_PHY_DX6GTR0_DGSL_MASK                                                  0x0000001FU
13394
13395 /*Calibration Bypass*/
13396 #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL
13397 #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT
13398 #undef DDR_PHY_DX7GCR0_CALBYP_MASK
13399 #define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                                              0x40200204
13400 #define DDR_PHY_DX7GCR0_CALBYP_SHIFT                                               31
13401 #define DDR_PHY_DX7GCR0_CALBYP_MASK                                                0x80000000U
13402
13403 /*Master Delay Line Enable*/
13404 #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL
13405 #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT
13406 #undef DDR_PHY_DX7GCR0_MDLEN_MASK
13407 #define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                                               0x40200204
13408 #define DDR_PHY_DX7GCR0_MDLEN_SHIFT                                                30
13409 #define DDR_PHY_DX7GCR0_MDLEN_MASK                                                 0x40000000U
13410
13411 /*Configurable ODT(TE) Phase Shift*/
13412 #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL
13413 #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
13414 #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK
13415 #define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                                            0x40200204
13416 #define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                                             28
13417 #define DDR_PHY_DX7GCR0_CODTSHFT_MASK                                              0x30000000U
13418
13419 /*DQS Duty Cycle Correction*/
13420 #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL
13421 #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT
13422 #undef DDR_PHY_DX7GCR0_DQSDCC_MASK
13423 #define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                                              0x40200204
13424 #define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                                               24
13425 #define DDR_PHY_DX7GCR0_DQSDCC_MASK                                                0x0F000000U
13426
13427 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13428 #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL
13429 #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT
13430 #undef DDR_PHY_DX7GCR0_RDDLY_MASK
13431 #define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                                               0x40200204
13432 #define DDR_PHY_DX7GCR0_RDDLY_SHIFT                                                20
13433 #define DDR_PHY_DX7GCR0_RDDLY_MASK                                                 0x00F00000U
13434
13435 /*Reserved. Return zeroes on reads.*/
13436 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL
13437 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
13438 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK
13439 #define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
13440 #define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                                       14
13441 #define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                                        0x000FC000U
13442
13443 /*DQSNSE Power Down Receiver*/
13444 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL
13445 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
13446 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK
13447 #define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
13448 #define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                                            13
13449 #define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                                             0x00002000U
13450
13451 /*DQSSE Power Down Receiver*/
13452 #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL
13453 #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
13454 #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK
13455 #define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                                            0x40200204
13456 #define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                                             12
13457 #define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                                              0x00001000U
13458
13459 /*RTT On Additive Latency*/
13460 #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL
13461 #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT
13462 #undef DDR_PHY_DX7GCR0_RTTOAL_MASK
13463 #define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                                              0x40200204
13464 #define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                                               11
13465 #define DDR_PHY_DX7GCR0_RTTOAL_MASK                                                0x00000800U
13466
13467 /*RTT Output Hold*/
13468 #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL
13469 #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT
13470 #undef DDR_PHY_DX7GCR0_RTTOH_MASK
13471 #define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                                               0x40200204
13472 #define DDR_PHY_DX7GCR0_RTTOH_SHIFT                                                9
13473 #define DDR_PHY_DX7GCR0_RTTOH_MASK                                                 0x00000600U
13474
13475 /*Configurable PDR Phase Shift*/
13476 #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL
13477 #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
13478 #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK
13479 #define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                                            0x40200204
13480 #define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                                             7
13481 #define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                                              0x00000180U
13482
13483 /*DQSR Power Down*/
13484 #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL
13485 #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT
13486 #undef DDR_PHY_DX7GCR0_DQSRPD_MASK
13487 #define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                                              0x40200204
13488 #define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                                               6
13489 #define DDR_PHY_DX7GCR0_DQSRPD_MASK                                                0x00000040U
13490
13491 /*DQSG Power Down Receiver*/
13492 #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL
13493 #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
13494 #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK
13495 #define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                                             0x40200204
13496 #define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                                              5
13497 #define DDR_PHY_DX7GCR0_DQSGPDR_MASK                                               0x00000020U
13498
13499 /*Reserved. Return zeroes on reads.*/
13500 #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL
13501 #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
13502 #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK
13503 #define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                                          0x40200204
13504 #define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                                           4
13505 #define DDR_PHY_DX7GCR0_RESERVED_4_MASK                                            0x00000010U
13506
13507 /*DQSG On-Die Termination*/
13508 #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL
13509 #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT
13510 #undef DDR_PHY_DX7GCR0_DQSGODT_MASK
13511 #define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                                             0x40200204
13512 #define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                                              3
13513 #define DDR_PHY_DX7GCR0_DQSGODT_MASK                                               0x00000008U
13514
13515 /*DQSG Output Enable*/
13516 #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL
13517 #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT
13518 #undef DDR_PHY_DX7GCR0_DQSGOE_MASK
13519 #define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                                              0x40200204
13520 #define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                                               2
13521 #define DDR_PHY_DX7GCR0_DQSGOE_MASK                                                0x00000004U
13522
13523 /*Reserved. Return zeroes on reads.*/
13524 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL
13525 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
13526 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK
13527 #define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
13528 #define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                                         0
13529 #define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                                          0x00000003U
13530
13531 /*Enables the PDR mode for DQ[7:0]*/
13532 #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL
13533 #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
13534 #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK
13535 #define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
13536 #define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                                            16
13537 #define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
13538
13539 /*Reserved. Returns zeroes on reads.*/
13540 #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL
13541 #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
13542 #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK
13543 #define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
13544 #define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                                          15
13545 #define DDR_PHY_DX7GCR1_RESERVED_15_MASK                                           0x00008000U
13546
13547 /*Select the delayed or non-delayed read data strobe #*/
13548 #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL
13549 #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT
13550 #undef DDR_PHY_DX7GCR1_QSNSEL_MASK
13551 #define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                                              0x00007FFF
13552 #define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                                               14
13553 #define DDR_PHY_DX7GCR1_QSNSEL_MASK                                                0x00004000U
13554
13555 /*Select the delayed or non-delayed read data strobe*/
13556 #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL
13557 #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT
13558 #undef DDR_PHY_DX7GCR1_QSSEL_MASK
13559 #define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                                               0x00007FFF
13560 #define DDR_PHY_DX7GCR1_QSSEL_SHIFT                                                13
13561 #define DDR_PHY_DX7GCR1_QSSEL_MASK                                                 0x00002000U
13562
13563 /*Enables Read Data Strobe in a byte lane*/
13564 #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL
13565 #undef DDR_PHY_DX7GCR1_OEEN_SHIFT
13566 #undef DDR_PHY_DX7GCR1_OEEN_MASK
13567 #define DDR_PHY_DX7GCR1_OEEN_DEFVAL                                                0x00007FFF
13568 #define DDR_PHY_DX7GCR1_OEEN_SHIFT                                                 12
13569 #define DDR_PHY_DX7GCR1_OEEN_MASK                                                  0x00001000U
13570
13571 /*Enables PDR in a byte lane*/
13572 #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL
13573 #undef DDR_PHY_DX7GCR1_PDREN_SHIFT
13574 #undef DDR_PHY_DX7GCR1_PDREN_MASK
13575 #define DDR_PHY_DX7GCR1_PDREN_DEFVAL                                               0x00007FFF
13576 #define DDR_PHY_DX7GCR1_PDREN_SHIFT                                                11
13577 #define DDR_PHY_DX7GCR1_PDREN_MASK                                                 0x00000800U
13578
13579 /*Enables ODT/TE in a byte lane*/
13580 #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL
13581 #undef DDR_PHY_DX7GCR1_TEEN_SHIFT
13582 #undef DDR_PHY_DX7GCR1_TEEN_MASK
13583 #define DDR_PHY_DX7GCR1_TEEN_DEFVAL                                                0x00007FFF
13584 #define DDR_PHY_DX7GCR1_TEEN_SHIFT                                                 10
13585 #define DDR_PHY_DX7GCR1_TEEN_MASK                                                  0x00000400U
13586
13587 /*Enables Write Data strobe in a byte lane*/
13588 #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL
13589 #undef DDR_PHY_DX7GCR1_DSEN_SHIFT
13590 #undef DDR_PHY_DX7GCR1_DSEN_MASK
13591 #define DDR_PHY_DX7GCR1_DSEN_DEFVAL                                                0x00007FFF
13592 #define DDR_PHY_DX7GCR1_DSEN_SHIFT                                                 9
13593 #define DDR_PHY_DX7GCR1_DSEN_MASK                                                  0x00000200U
13594
13595 /*Enables DM pin in a byte lane*/
13596 #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL
13597 #undef DDR_PHY_DX7GCR1_DMEN_SHIFT
13598 #undef DDR_PHY_DX7GCR1_DMEN_MASK
13599 #define DDR_PHY_DX7GCR1_DMEN_DEFVAL                                                0x00007FFF
13600 #define DDR_PHY_DX7GCR1_DMEN_SHIFT                                                 8
13601 #define DDR_PHY_DX7GCR1_DMEN_MASK                                                  0x00000100U
13602
13603 /*Enables DQ corresponding to each bit in a byte*/
13604 #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL
13605 #undef DDR_PHY_DX7GCR1_DQEN_SHIFT
13606 #undef DDR_PHY_DX7GCR1_DQEN_MASK
13607 #define DDR_PHY_DX7GCR1_DQEN_DEFVAL                                                0x00007FFF
13608 #define DDR_PHY_DX7GCR1_DQEN_SHIFT                                                 0
13609 #define DDR_PHY_DX7GCR1_DQEN_MASK                                                  0x000000FFU
13610
13611 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
13612 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL
13613 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
13614 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK
13615 #define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
13616 #define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                                       29
13617 #define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                                        0xE0000000U
13618
13619 /*Byte Lane VREF Pad Enable*/
13620 #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL
13621 #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
13622 #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK
13623 #define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
13624 #define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                                             28
13625 #define DDR_PHY_DX7GCR4_DXREFPEN_MASK                                              0x10000000U
13626
13627 /*Byte Lane Internal VREF Enable*/
13628 #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL
13629 #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
13630 #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK
13631 #define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
13632 #define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                                             26
13633 #define DDR_PHY_DX7GCR4_DXREFEEN_MASK                                              0x0C000000U
13634
13635 /*Byte Lane Single-End VREF Enable*/
13636 #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL
13637 #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
13638 #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK
13639 #define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
13640 #define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                                             25
13641 #define DDR_PHY_DX7GCR4_DXREFSEN_MASK                                              0x02000000U
13642
13643 /*Reserved. Returns zeros on reads.*/
13644 #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL
13645 #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
13646 #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK
13647 #define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
13648 #define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                                          24
13649 #define DDR_PHY_DX7GCR4_RESERVED_24_MASK                                           0x01000000U
13650
13651 /*External VREF generator REFSEL range select*/
13652 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL
13653 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
13654 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK
13655 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
13656 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                                       23
13657 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                                        0x00800000U
13658
13659 /*Byte Lane External VREF Select*/
13660 #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL
13661 #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
13662 #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK
13663 #define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
13664 #define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                                            16
13665 #define DDR_PHY_DX7GCR4_DXREFESEL_MASK                                             0x007F0000U
13666
13667 /*Single ended VREF generator REFSEL range select*/
13668 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL
13669 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
13670 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK
13671 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
13672 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                                       15
13673 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
13674
13675 /*Byte Lane Single-End VREF Select*/
13676 #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL
13677 #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
13678 #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK
13679 #define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
13680 #define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                                            8
13681 #define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                                             0x00007F00U
13682
13683 /*Reserved. Returns zeros on reads.*/
13684 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL
13685 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
13686 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK
13687 #define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
13688 #define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                                         6
13689 #define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                                          0x000000C0U
13690
13691 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13692 #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL
13693 #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
13694 #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK
13695 #define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
13696 #define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                                             2
13697 #define DDR_PHY_DX7GCR4_DXREFIEN_MASK                                              0x0000003CU
13698
13699 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13700 #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL
13701 #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
13702 #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK
13703 #define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
13704 #define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                                            0
13705 #define DDR_PHY_DX7GCR4_DXREFIMON_MASK                                             0x00000003U
13706
13707 /*Reserved. Returns zeros on reads.*/
13708 #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL
13709 #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
13710 #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK
13711 #define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                                         0x09090909
13712 #define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                                          31
13713 #define DDR_PHY_DX7GCR5_RESERVED_31_MASK                                           0x80000000U
13714
13715 /*Byte Lane internal VREF Select for Rank 3*/
13716 #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL
13717 #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
13718 #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK
13719 #define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                                         0x09090909
13720 #define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                                          24
13721 #define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                                           0x7F000000U
13722
13723 /*Reserved. Returns zeros on reads.*/
13724 #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL
13725 #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
13726 #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK
13727 #define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                                         0x09090909
13728 #define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                                          23
13729 #define DDR_PHY_DX7GCR5_RESERVED_23_MASK                                           0x00800000U
13730
13731 /*Byte Lane internal VREF Select for Rank 2*/
13732 #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL
13733 #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
13734 #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK
13735 #define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                                         0x09090909
13736 #define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                                          16
13737 #define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                                           0x007F0000U
13738
13739 /*Reserved. Returns zeros on reads.*/
13740 #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL
13741 #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
13742 #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK
13743 #define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                                         0x09090909
13744 #define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                                          15
13745 #define DDR_PHY_DX7GCR5_RESERVED_15_MASK                                           0x00008000U
13746
13747 /*Byte Lane internal VREF Select for Rank 1*/
13748 #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL
13749 #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
13750 #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK
13751 #define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                                         0x09090909
13752 #define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                                          8
13753 #define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                                           0x00007F00U
13754
13755 /*Reserved. Returns zeros on reads.*/
13756 #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL
13757 #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
13758 #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK
13759 #define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                                          0x09090909
13760 #define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                                           7
13761 #define DDR_PHY_DX7GCR5_RESERVED_7_MASK                                            0x00000080U
13762
13763 /*Byte Lane internal VREF Select for Rank 0*/
13764 #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL
13765 #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
13766 #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK
13767 #define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                                         0x09090909
13768 #define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                                          0
13769 #define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                                           0x0000007FU
13770
13771 /*Reserved. Returns zeros on reads.*/
13772 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL
13773 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
13774 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK
13775 #define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
13776 #define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                                       30
13777 #define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                                        0xC0000000U
13778
13779 /*DRAM DQ VREF Select for Rank3*/
13780 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL
13781 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
13782 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK
13783 #define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
13784 #define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                                           24
13785 #define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                                            0x3F000000U
13786
13787 /*Reserved. Returns zeros on reads.*/
13788 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL
13789 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
13790 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK
13791 #define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
13792 #define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                                       22
13793 #define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                                        0x00C00000U
13794
13795 /*DRAM DQ VREF Select for Rank2*/
13796 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL
13797 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
13798 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK
13799 #define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
13800 #define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                                           16
13801 #define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                                            0x003F0000U
13802
13803 /*Reserved. Returns zeros on reads.*/
13804 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL
13805 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
13806 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK
13807 #define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
13808 #define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                                       14
13809 #define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                                        0x0000C000U
13810
13811 /*DRAM DQ VREF Select for Rank1*/
13812 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL
13813 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
13814 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK
13815 #define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
13816 #define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                                           8
13817 #define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                                            0x00003F00U
13818
13819 /*Reserved. Returns zeros on reads.*/
13820 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL
13821 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
13822 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK
13823 #define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
13824 #define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                                         6
13825 #define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                                          0x000000C0U
13826
13827 /*DRAM DQ VREF Select for Rank0*/
13828 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL
13829 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
13830 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK
13831 #define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
13832 #define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                                           0
13833 #define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                                            0x0000003FU
13834
13835 /*Reserved. Return zeroes on reads.*/
13836 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL
13837 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
13838 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK
13839 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
13840 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT                                     25
13841 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
13842
13843 /*Reserved. Caution, do not write to this register field.*/
13844 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL
13845 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
13846 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK
13847 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
13848 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT                                     16
13849 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
13850
13851 /*Reserved. Return zeroes on reads.*/
13852 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL
13853 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
13854 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK
13855 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
13856 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT                                      9
13857 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
13858
13859 /*Read DQS Gating Delay*/
13860 #undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL
13861 #undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
13862 #undef DDR_PHY_DX7LCDLR2_DQSGD_MASK
13863 #define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL                                             0x00000000
13864 #define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT                                              0
13865 #define DDR_PHY_DX7LCDLR2_DQSGD_MASK                                               0x000001FFU
13866
13867 /*Reserved. Return zeroes on reads.*/
13868 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL
13869 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
13870 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK
13871 #define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
13872 #define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT                                       27
13873 #define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK                                        0xF8000000U
13874
13875 /*DQ Write Path Latency Pipeline*/
13876 #undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL
13877 #undef DDR_PHY_DX7GTR0_WDQSL_SHIFT
13878 #undef DDR_PHY_DX7GTR0_WDQSL_MASK
13879 #define DDR_PHY_DX7GTR0_WDQSL_DEFVAL                                               0x00020000
13880 #define DDR_PHY_DX7GTR0_WDQSL_SHIFT                                                24
13881 #define DDR_PHY_DX7GTR0_WDQSL_MASK                                                 0x07000000U
13882
13883 /*Reserved. Caution, do not write to this register field.*/
13884 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL
13885 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
13886 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK
13887 #define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
13888 #define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT                                       20
13889 #define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK                                        0x00F00000U
13890
13891 /*Write Leveling System Latency*/
13892 #undef DDR_PHY_DX7GTR0_WLSL_DEFVAL
13893 #undef DDR_PHY_DX7GTR0_WLSL_SHIFT
13894 #undef DDR_PHY_DX7GTR0_WLSL_MASK
13895 #define DDR_PHY_DX7GTR0_WLSL_DEFVAL                                                0x00020000
13896 #define DDR_PHY_DX7GTR0_WLSL_SHIFT                                                 16
13897 #define DDR_PHY_DX7GTR0_WLSL_MASK                                                  0x000F0000U
13898
13899 /*Reserved. Return zeroes on reads.*/
13900 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL
13901 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
13902 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK
13903 #define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
13904 #define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT                                       13
13905 #define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK                                        0x0000E000U
13906
13907 /*Reserved. Caution, do not write to this register field.*/
13908 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL
13909 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
13910 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK
13911 #define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
13912 #define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT                                        8
13913 #define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK                                         0x00001F00U
13914
13915 /*Reserved. Return zeroes on reads.*/
13916 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL
13917 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
13918 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK
13919 #define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
13920 #define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT                                         5
13921 #define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK                                          0x000000E0U
13922
13923 /*DQS Gating System Latency*/
13924 #undef DDR_PHY_DX7GTR0_DGSL_DEFVAL
13925 #undef DDR_PHY_DX7GTR0_DGSL_SHIFT
13926 #undef DDR_PHY_DX7GTR0_DGSL_MASK
13927 #define DDR_PHY_DX7GTR0_DGSL_DEFVAL                                                0x00020000
13928 #define DDR_PHY_DX7GTR0_DGSL_SHIFT                                                 0
13929 #define DDR_PHY_DX7GTR0_DGSL_MASK                                                  0x0000001FU
13930
13931 /*Calibration Bypass*/
13932 #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL
13933 #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT
13934 #undef DDR_PHY_DX8GCR0_CALBYP_MASK
13935 #define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                                              0x40200204
13936 #define DDR_PHY_DX8GCR0_CALBYP_SHIFT                                               31
13937 #define DDR_PHY_DX8GCR0_CALBYP_MASK                                                0x80000000U
13938
13939 /*Master Delay Line Enable*/
13940 #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL
13941 #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT
13942 #undef DDR_PHY_DX8GCR0_MDLEN_MASK
13943 #define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                                               0x40200204
13944 #define DDR_PHY_DX8GCR0_MDLEN_SHIFT                                                30
13945 #define DDR_PHY_DX8GCR0_MDLEN_MASK                                                 0x40000000U
13946
13947 /*Configurable ODT(TE) Phase Shift*/
13948 #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL
13949 #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
13950 #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK
13951 #define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                                            0x40200204
13952 #define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                                             28
13953 #define DDR_PHY_DX8GCR0_CODTSHFT_MASK                                              0x30000000U
13954
13955 /*DQS Duty Cycle Correction*/
13956 #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL
13957 #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT
13958 #undef DDR_PHY_DX8GCR0_DQSDCC_MASK
13959 #define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                                              0x40200204
13960 #define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                                               24
13961 #define DDR_PHY_DX8GCR0_DQSDCC_MASK                                                0x0F000000U
13962
13963 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13964 #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL
13965 #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT
13966 #undef DDR_PHY_DX8GCR0_RDDLY_MASK
13967 #define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                                               0x40200204
13968 #define DDR_PHY_DX8GCR0_RDDLY_SHIFT                                                20
13969 #define DDR_PHY_DX8GCR0_RDDLY_MASK                                                 0x00F00000U
13970
13971 /*Reserved. Return zeroes on reads.*/
13972 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL
13973 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
13974 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK
13975 #define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
13976 #define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                                       14
13977 #define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                                        0x000FC000U
13978
13979 /*DQSNSE Power Down Receiver*/
13980 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL
13981 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
13982 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK
13983 #define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
13984 #define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                                            13
13985 #define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                                             0x00002000U
13986
13987 /*DQSSE Power Down Receiver*/
13988 #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL
13989 #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
13990 #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK
13991 #define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                                            0x40200204
13992 #define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                                             12
13993 #define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                                              0x00001000U
13994
13995 /*RTT On Additive Latency*/
13996 #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL
13997 #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT
13998 #undef DDR_PHY_DX8GCR0_RTTOAL_MASK
13999 #define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                                              0x40200204
14000 #define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                                               11
14001 #define DDR_PHY_DX8GCR0_RTTOAL_MASK                                                0x00000800U
14002
14003 /*RTT Output Hold*/
14004 #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL
14005 #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT
14006 #undef DDR_PHY_DX8GCR0_RTTOH_MASK
14007 #define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                                               0x40200204
14008 #define DDR_PHY_DX8GCR0_RTTOH_SHIFT                                                9
14009 #define DDR_PHY_DX8GCR0_RTTOH_MASK                                                 0x00000600U
14010
14011 /*Configurable PDR Phase Shift*/
14012 #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL
14013 #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
14014 #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK
14015 #define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                                            0x40200204
14016 #define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                                             7
14017 #define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                                              0x00000180U
14018
14019 /*DQSR Power Down*/
14020 #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL
14021 #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT
14022 #undef DDR_PHY_DX8GCR0_DQSRPD_MASK
14023 #define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                                              0x40200204
14024 #define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                                               6
14025 #define DDR_PHY_DX8GCR0_DQSRPD_MASK                                                0x00000040U
14026
14027 /*DQSG Power Down Receiver*/
14028 #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL
14029 #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
14030 #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK
14031 #define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                                             0x40200204
14032 #define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                                              5
14033 #define DDR_PHY_DX8GCR0_DQSGPDR_MASK                                               0x00000020U
14034
14035 /*Reserved. Return zeroes on reads.*/
14036 #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL
14037 #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
14038 #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK
14039 #define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                                          0x40200204
14040 #define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                                           4
14041 #define DDR_PHY_DX8GCR0_RESERVED_4_MASK                                            0x00000010U
14042
14043 /*DQSG On-Die Termination*/
14044 #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL
14045 #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT
14046 #undef DDR_PHY_DX8GCR0_DQSGODT_MASK
14047 #define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                                             0x40200204
14048 #define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                                              3
14049 #define DDR_PHY_DX8GCR0_DQSGODT_MASK                                               0x00000008U
14050
14051 /*DQSG Output Enable*/
14052 #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL
14053 #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT
14054 #undef DDR_PHY_DX8GCR0_DQSGOE_MASK
14055 #define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                                              0x40200204
14056 #define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                                               2
14057 #define DDR_PHY_DX8GCR0_DQSGOE_MASK                                                0x00000004U
14058
14059 /*Reserved. Return zeroes on reads.*/
14060 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL
14061 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
14062 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK
14063 #define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
14064 #define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                                         0
14065 #define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                                          0x00000003U
14066
14067 /*Enables the PDR mode for DQ[7:0]*/
14068 #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL
14069 #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
14070 #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK
14071 #define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
14072 #define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                                            16
14073 #define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
14074
14075 /*Reserved. Returns zeroes on reads.*/
14076 #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL
14077 #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
14078 #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK
14079 #define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
14080 #define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                                          15
14081 #define DDR_PHY_DX8GCR1_RESERVED_15_MASK                                           0x00008000U
14082
14083 /*Select the delayed or non-delayed read data strobe #*/
14084 #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL
14085 #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT
14086 #undef DDR_PHY_DX8GCR1_QSNSEL_MASK
14087 #define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                                              0x00007FFF
14088 #define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                                               14
14089 #define DDR_PHY_DX8GCR1_QSNSEL_MASK                                                0x00004000U
14090
14091 /*Select the delayed or non-delayed read data strobe*/
14092 #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL
14093 #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT
14094 #undef DDR_PHY_DX8GCR1_QSSEL_MASK
14095 #define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                                               0x00007FFF
14096 #define DDR_PHY_DX8GCR1_QSSEL_SHIFT                                                13
14097 #define DDR_PHY_DX8GCR1_QSSEL_MASK                                                 0x00002000U
14098
14099 /*Enables Read Data Strobe in a byte lane*/
14100 #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL
14101 #undef DDR_PHY_DX8GCR1_OEEN_SHIFT
14102 #undef DDR_PHY_DX8GCR1_OEEN_MASK
14103 #define DDR_PHY_DX8GCR1_OEEN_DEFVAL                                                0x00007FFF
14104 #define DDR_PHY_DX8GCR1_OEEN_SHIFT                                                 12
14105 #define DDR_PHY_DX8GCR1_OEEN_MASK                                                  0x00001000U
14106
14107 /*Enables PDR in a byte lane*/
14108 #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL
14109 #undef DDR_PHY_DX8GCR1_PDREN_SHIFT
14110 #undef DDR_PHY_DX8GCR1_PDREN_MASK
14111 #define DDR_PHY_DX8GCR1_PDREN_DEFVAL                                               0x00007FFF
14112 #define DDR_PHY_DX8GCR1_PDREN_SHIFT                                                11
14113 #define DDR_PHY_DX8GCR1_PDREN_MASK                                                 0x00000800U
14114
14115 /*Enables ODT/TE in a byte lane*/
14116 #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL
14117 #undef DDR_PHY_DX8GCR1_TEEN_SHIFT
14118 #undef DDR_PHY_DX8GCR1_TEEN_MASK
14119 #define DDR_PHY_DX8GCR1_TEEN_DEFVAL                                                0x00007FFF
14120 #define DDR_PHY_DX8GCR1_TEEN_SHIFT                                                 10
14121 #define DDR_PHY_DX8GCR1_TEEN_MASK                                                  0x00000400U
14122
14123 /*Enables Write Data strobe in a byte lane*/
14124 #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL
14125 #undef DDR_PHY_DX8GCR1_DSEN_SHIFT
14126 #undef DDR_PHY_DX8GCR1_DSEN_MASK
14127 #define DDR_PHY_DX8GCR1_DSEN_DEFVAL                                                0x00007FFF
14128 #define DDR_PHY_DX8GCR1_DSEN_SHIFT                                                 9
14129 #define DDR_PHY_DX8GCR1_DSEN_MASK                                                  0x00000200U
14130
14131 /*Enables DM pin in a byte lane*/
14132 #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL
14133 #undef DDR_PHY_DX8GCR1_DMEN_SHIFT
14134 #undef DDR_PHY_DX8GCR1_DMEN_MASK
14135 #define DDR_PHY_DX8GCR1_DMEN_DEFVAL                                                0x00007FFF
14136 #define DDR_PHY_DX8GCR1_DMEN_SHIFT                                                 8
14137 #define DDR_PHY_DX8GCR1_DMEN_MASK                                                  0x00000100U
14138
14139 /*Enables DQ corresponding to each bit in a byte*/
14140 #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL
14141 #undef DDR_PHY_DX8GCR1_DQEN_SHIFT
14142 #undef DDR_PHY_DX8GCR1_DQEN_MASK
14143 #define DDR_PHY_DX8GCR1_DQEN_DEFVAL                                                0x00007FFF
14144 #define DDR_PHY_DX8GCR1_DQEN_SHIFT                                                 0
14145 #define DDR_PHY_DX8GCR1_DQEN_MASK                                                  0x000000FFU
14146
14147 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
14148 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL
14149 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
14150 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK
14151 #define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
14152 #define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                                       29
14153 #define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                                        0xE0000000U
14154
14155 /*Byte Lane VREF Pad Enable*/
14156 #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL
14157 #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
14158 #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK
14159 #define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
14160 #define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                                             28
14161 #define DDR_PHY_DX8GCR4_DXREFPEN_MASK                                              0x10000000U
14162
14163 /*Byte Lane Internal VREF Enable*/
14164 #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL
14165 #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
14166 #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK
14167 #define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
14168 #define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                                             26
14169 #define DDR_PHY_DX8GCR4_DXREFEEN_MASK                                              0x0C000000U
14170
14171 /*Byte Lane Single-End VREF Enable*/
14172 #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL
14173 #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
14174 #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK
14175 #define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
14176 #define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                                             25
14177 #define DDR_PHY_DX8GCR4_DXREFSEN_MASK                                              0x02000000U
14178
14179 /*Reserved. Returns zeros on reads.*/
14180 #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL
14181 #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
14182 #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK
14183 #define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
14184 #define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                                          24
14185 #define DDR_PHY_DX8GCR4_RESERVED_24_MASK                                           0x01000000U
14186
14187 /*External VREF generator REFSEL range select*/
14188 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL
14189 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
14190 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK
14191 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
14192 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                                       23
14193 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                                        0x00800000U
14194
14195 /*Byte Lane External VREF Select*/
14196 #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL
14197 #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
14198 #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK
14199 #define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
14200 #define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                                            16
14201 #define DDR_PHY_DX8GCR4_DXREFESEL_MASK                                             0x007F0000U
14202
14203 /*Single ended VREF generator REFSEL range select*/
14204 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL
14205 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
14206 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK
14207 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
14208 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                                       15
14209 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
14210
14211 /*Byte Lane Single-End VREF Select*/
14212 #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL
14213 #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
14214 #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK
14215 #define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
14216 #define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                                            8
14217 #define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                                             0x00007F00U
14218
14219 /*Reserved. Returns zeros on reads.*/
14220 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL
14221 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
14222 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK
14223 #define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
14224 #define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                                         6
14225 #define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                                          0x000000C0U
14226
14227 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
14228 #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL
14229 #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
14230 #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK
14231 #define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
14232 #define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                                             2
14233 #define DDR_PHY_DX8GCR4_DXREFIEN_MASK                                              0x0000003CU
14234
14235 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
14236 #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL
14237 #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
14238 #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK
14239 #define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
14240 #define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                                            0
14241 #define DDR_PHY_DX8GCR4_DXREFIMON_MASK                                             0x00000003U
14242
14243 /*Reserved. Returns zeros on reads.*/
14244 #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL
14245 #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
14246 #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK
14247 #define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                                         0x09090909
14248 #define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                                          31
14249 #define DDR_PHY_DX8GCR5_RESERVED_31_MASK                                           0x80000000U
14250
14251 /*Byte Lane internal VREF Select for Rank 3*/
14252 #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL
14253 #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
14254 #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK
14255 #define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                                         0x09090909
14256 #define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                                          24
14257 #define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                                           0x7F000000U
14258
14259 /*Reserved. Returns zeros on reads.*/
14260 #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL
14261 #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
14262 #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK
14263 #define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                                         0x09090909
14264 #define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                                          23
14265 #define DDR_PHY_DX8GCR5_RESERVED_23_MASK                                           0x00800000U
14266
14267 /*Byte Lane internal VREF Select for Rank 2*/
14268 #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL
14269 #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
14270 #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK
14271 #define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                                         0x09090909
14272 #define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                                          16
14273 #define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                                           0x007F0000U
14274
14275 /*Reserved. Returns zeros on reads.*/
14276 #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL
14277 #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
14278 #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK
14279 #define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                                         0x09090909
14280 #define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                                          15
14281 #define DDR_PHY_DX8GCR5_RESERVED_15_MASK                                           0x00008000U
14282
14283 /*Byte Lane internal VREF Select for Rank 1*/
14284 #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL
14285 #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
14286 #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK
14287 #define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                                         0x09090909
14288 #define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                                          8
14289 #define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                                           0x00007F00U
14290
14291 /*Reserved. Returns zeros on reads.*/
14292 #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL
14293 #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
14294 #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK
14295 #define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                                          0x09090909
14296 #define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                                           7
14297 #define DDR_PHY_DX8GCR5_RESERVED_7_MASK                                            0x00000080U
14298
14299 /*Byte Lane internal VREF Select for Rank 0*/
14300 #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL
14301 #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
14302 #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK
14303 #define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                                         0x09090909
14304 #define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                                          0
14305 #define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                                           0x0000007FU
14306
14307 /*Reserved. Returns zeros on reads.*/
14308 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL
14309 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
14310 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK
14311 #define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
14312 #define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                                       30
14313 #define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                                        0xC0000000U
14314
14315 /*DRAM DQ VREF Select for Rank3*/
14316 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL
14317 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
14318 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK
14319 #define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
14320 #define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                                           24
14321 #define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                                            0x3F000000U
14322
14323 /*Reserved. Returns zeros on reads.*/
14324 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL
14325 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
14326 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK
14327 #define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
14328 #define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                                       22
14329 #define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                                        0x00C00000U
14330
14331 /*DRAM DQ VREF Select for Rank2*/
14332 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL
14333 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
14334 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK
14335 #define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
14336 #define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                                           16
14337 #define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                                            0x003F0000U
14338
14339 /*Reserved. Returns zeros on reads.*/
14340 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL
14341 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
14342 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK
14343 #define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
14344 #define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                                       14
14345 #define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                                        0x0000C000U
14346
14347 /*DRAM DQ VREF Select for Rank1*/
14348 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL
14349 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
14350 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK
14351 #define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
14352 #define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                                           8
14353 #define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                                            0x00003F00U
14354
14355 /*Reserved. Returns zeros on reads.*/
14356 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL
14357 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
14358 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK
14359 #define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
14360 #define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                                         6
14361 #define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                                          0x000000C0U
14362
14363 /*DRAM DQ VREF Select for Rank0*/
14364 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL
14365 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
14366 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK
14367 #define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
14368 #define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                                           0
14369 #define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                                            0x0000003FU
14370
14371 /*Reserved. Return zeroes on reads.*/
14372 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL
14373 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
14374 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK
14375 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
14376 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT                                     25
14377 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
14378
14379 /*Reserved. Caution, do not write to this register field.*/
14380 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL
14381 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
14382 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK
14383 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
14384 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT                                     16
14385 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
14386
14387 /*Reserved. Return zeroes on reads.*/
14388 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL
14389 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
14390 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK
14391 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
14392 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT                                      9
14393 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
14394
14395 /*Read DQS Gating Delay*/
14396 #undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL
14397 #undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
14398 #undef DDR_PHY_DX8LCDLR2_DQSGD_MASK
14399 #define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL                                             0x00000000
14400 #define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT                                              0
14401 #define DDR_PHY_DX8LCDLR2_DQSGD_MASK                                               0x000001FFU
14402
14403 /*Reserved. Return zeroes on reads.*/
14404 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL
14405 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
14406 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK
14407 #define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
14408 #define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT                                       27
14409 #define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK                                        0xF8000000U
14410
14411 /*DQ Write Path Latency Pipeline*/
14412 #undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL
14413 #undef DDR_PHY_DX8GTR0_WDQSL_SHIFT
14414 #undef DDR_PHY_DX8GTR0_WDQSL_MASK
14415 #define DDR_PHY_DX8GTR0_WDQSL_DEFVAL                                               0x00020000
14416 #define DDR_PHY_DX8GTR0_WDQSL_SHIFT                                                24
14417 #define DDR_PHY_DX8GTR0_WDQSL_MASK                                                 0x07000000U
14418
14419 /*Reserved. Caution, do not write to this register field.*/
14420 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL
14421 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
14422 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK
14423 #define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
14424 #define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT                                       20
14425 #define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK                                        0x00F00000U
14426
14427 /*Write Leveling System Latency*/
14428 #undef DDR_PHY_DX8GTR0_WLSL_DEFVAL
14429 #undef DDR_PHY_DX8GTR0_WLSL_SHIFT
14430 #undef DDR_PHY_DX8GTR0_WLSL_MASK
14431 #define DDR_PHY_DX8GTR0_WLSL_DEFVAL                                                0x00020000
14432 #define DDR_PHY_DX8GTR0_WLSL_SHIFT                                                 16
14433 #define DDR_PHY_DX8GTR0_WLSL_MASK                                                  0x000F0000U
14434
14435 /*Reserved. Return zeroes on reads.*/
14436 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL
14437 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
14438 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK
14439 #define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
14440 #define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT                                       13
14441 #define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK                                        0x0000E000U
14442
14443 /*Reserved. Caution, do not write to this register field.*/
14444 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL
14445 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
14446 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK
14447 #define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
14448 #define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT                                        8
14449 #define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK                                         0x00001F00U
14450
14451 /*Reserved. Return zeroes on reads.*/
14452 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL
14453 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
14454 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK
14455 #define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
14456 #define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT                                         5
14457 #define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK                                          0x000000E0U
14458
14459 /*DQS Gating System Latency*/
14460 #undef DDR_PHY_DX8GTR0_DGSL_DEFVAL
14461 #undef DDR_PHY_DX8GTR0_DGSL_SHIFT
14462 #undef DDR_PHY_DX8GTR0_DGSL_MASK
14463 #define DDR_PHY_DX8GTR0_DGSL_DEFVAL                                                0x00020000
14464 #define DDR_PHY_DX8GTR0_DGSL_SHIFT                                                 0
14465 #define DDR_PHY_DX8GTR0_DGSL_MASK                                                  0x0000001FU
14466
14467 /*Reserved. Return zeroes on reads.*/
14468 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
14469 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
14470 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK
14471 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
14472 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT                                  25
14473 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
14474
14475 /*Read Path Rise-to-Rise Mode*/
14476 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL
14477 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
14478 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK
14479 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                                        0x01264000
14480 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                                         24
14481 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                                          0x01000000U
14482
14483 /*Reserved. Return zeroes on reads.*/
14484 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL
14485 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
14486 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK
14487 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
14488 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT                                  22
14489 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
14490
14491 /*Write Path Rise-to-Rise Mode*/
14492 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL
14493 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
14494 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK
14495 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                                        0x01264000
14496 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                                         21
14497 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                                          0x00200000U
14498
14499 /*DQS Gate Extension*/
14500 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL
14501 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
14502 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK
14503 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                                          0x01264000
14504 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                                           19
14505 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                                            0x00180000U
14506
14507 /*Low Power PLL Power Down*/
14508 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL
14509 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
14510 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK
14511 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
14512 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                                         18
14513 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                                          0x00040000U
14514
14515 /*Low Power I/O Power Down*/
14516 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL
14517 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
14518 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK
14519 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                                         0x01264000
14520 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                                          17
14521 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                                           0x00020000U
14522
14523 /*Reserved. Return zeroes on reads.*/
14524 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL
14525 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
14526 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK
14527 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
14528 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT                                  15
14529 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
14530
14531 /*QS Counter Enable*/
14532 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL
14533 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
14534 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK
14535 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
14536 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                                         14
14537 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                                          0x00004000U
14538
14539 /*Unused DQ I/O Mode*/
14540 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL
14541 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
14542 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK
14543 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                                         0x01264000
14544 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                                          13
14545 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                                           0x00002000U
14546
14547 /*Reserved. Return zeroes on reads.*/
14548 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL
14549 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
14550 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK
14551 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
14552 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT                                  10
14553 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
14554
14555 /*Data Slew Rate*/
14556 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL
14557 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
14558 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK
14559 #define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                                           0x01264000
14560 #define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                                            8
14561 #define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                                             0x00000300U
14562
14563 /*DQS_N Resistor*/
14564 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL
14565 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
14566 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK
14567 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                                        0x01264000
14568 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                                         4
14569 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                                          0x000000F0U
14570
14571 /*DQS Resistor*/
14572 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL
14573 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
14574 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK
14575 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                                         0x01264000
14576 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                                          0
14577 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                                           0x0000000FU
14578
14579 /*Reserved. Return zeroes on reads.*/
14580 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL
14581 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
14582 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK
14583 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
14584 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT                                  24
14585 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
14586
14587 /*Configurable Read Data Enable*/
14588 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL
14589 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
14590 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK
14591 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                                          0x00141800
14592 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                                           23
14593 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                                            0x00800000U
14594
14595 /*OX Extension during Post-amble*/
14596 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL
14597 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
14598 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK
14599 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                                         0x00141800
14600 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                                          20
14601 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                                           0x00700000U
14602
14603 /*OE Extension during Pre-amble*/
14604 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL
14605 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
14606 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK
14607 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                                         0x00141800
14608 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                                          18
14609 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                                           0x000C0000U
14610
14611 /*Reserved. Return zeroes on reads.*/
14612 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL
14613 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
14614 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK
14615 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
14616 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                                     17
14617 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                                      0x00020000U
14618
14619 /*I/O Assisted Gate Select*/
14620 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL
14621 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
14622 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK
14623 #define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                                           0x00141800
14624 #define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                                            16
14625 #define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                                             0x00010000U
14626
14627 /*I/O Loopback Select*/
14628 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL
14629 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
14630 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK
14631 #define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                                           0x00141800
14632 #define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                                            15
14633 #define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                                             0x00008000U
14634
14635 /*Reserved. Return zeroes on reads.*/
14636 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL
14637 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
14638 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK
14639 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
14640 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT                                  13
14641 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
14642
14643 /*Low Power Wakeup Threshold*/
14644 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL
14645 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
14646 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK
14647 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
14648 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
14649 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
14650
14651 /*Read Data Bus Inversion Enable*/
14652 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL
14653 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
14654 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK
14655 #define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                                           0x00141800
14656 #define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                                            8
14657 #define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                                             0x00000100U
14658
14659 /*Write Data Bus Inversion Enable*/
14660 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL
14661 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
14662 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK
14663 #define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                                           0x00141800
14664 #define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                                            7
14665 #define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                                             0x00000080U
14666
14667 /*PUB Read FIFO Bypass*/
14668 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL
14669 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
14670 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK
14671 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                                         0x00141800
14672 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                                          6
14673 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                                           0x00000040U
14674
14675 /*DATX8 Receive FIFO Read Mode*/
14676 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL
14677 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
14678 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK
14679 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                                         0x00141800
14680 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                                          4
14681 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                                           0x00000030U
14682
14683 /*Disables the Read FIFO Reset*/
14684 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL
14685 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
14686 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK
14687 #define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                                         0x00141800
14688 #define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                                          3
14689 #define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                                           0x00000008U
14690
14691 /*Read DQS Gate I/O Loopback*/
14692 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL
14693 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
14694 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK
14695 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                                         0x00141800
14696 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                                          1
14697 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                                           0x00000006U
14698
14699 /*Reserved. Return zeroes on reads.*/
14700 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL
14701 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
14702 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK
14703 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
14704 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                                      0
14705 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                                       0x00000001U
14706
14707 /*Reserved. Return zeroes on reads.*/
14708 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL
14709 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
14710 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK
14711 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                                      0x00000000
14712 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                                       31
14713 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                                        0x80000000U
14714
14715 /*PVREF_DAC REFSEL range select*/
14716 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL
14717 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
14718 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK
14719 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                                       0x00000000
14720 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                                        28
14721 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                                         0x70000000U
14722
14723 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
14724 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL
14725 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
14726 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK
14727 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                                        0x00000000
14728 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                                         25
14729 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                                          0x0E000000U
14730
14731 /*DX IO Mode*/
14732 #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL
14733 #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
14734 #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK
14735 #define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                                            0x00000000
14736 #define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                                             22
14737 #define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                                              0x01C00000U
14738
14739 /*DX IO Transmitter Mode*/
14740 #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL
14741 #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
14742 #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK
14743 #define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                                            0x00000000
14744 #define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                                             11
14745 #define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                                              0x003FF800U
14746
14747 /*DX IO Receiver Mode*/
14748 #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL
14749 #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
14750 #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK
14751 #define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                                            0x00000000
14752 #define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                                             0
14753 #define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                                              0x000007FFU
14754
14755 /*Reserved. Return zeroes on reads.*/
14756 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
14757 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
14758 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK
14759 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
14760 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT                                  25
14761 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
14762
14763 /*Read Path Rise-to-Rise Mode*/
14764 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL
14765 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
14766 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK
14767 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                                        0x01264000
14768 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                                         24
14769 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                                          0x01000000U
14770
14771 /*Reserved. Return zeroes on reads.*/
14772 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL
14773 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
14774 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK
14775 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
14776 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT                                  22
14777 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
14778
14779 /*Write Path Rise-to-Rise Mode*/
14780 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL
14781 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
14782 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK
14783 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                                        0x01264000
14784 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                                         21
14785 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                                          0x00200000U
14786
14787 /*DQS Gate Extension*/
14788 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL
14789 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
14790 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK
14791 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                                          0x01264000
14792 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                                           19
14793 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                                            0x00180000U
14794
14795 /*Low Power PLL Power Down*/
14796 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL
14797 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
14798 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK
14799 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
14800 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                                         18
14801 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                                          0x00040000U
14802
14803 /*Low Power I/O Power Down*/
14804 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL
14805 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
14806 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK
14807 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                                         0x01264000
14808 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                                          17
14809 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                                           0x00020000U
14810
14811 /*Reserved. Return zeroes on reads.*/
14812 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL
14813 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
14814 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK
14815 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
14816 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT                                  15
14817 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
14818
14819 /*QS Counter Enable*/
14820 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL
14821 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
14822 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK
14823 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
14824 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                                         14
14825 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                                          0x00004000U
14826
14827 /*Unused DQ I/O Mode*/
14828 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL
14829 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
14830 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK
14831 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                                         0x01264000
14832 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                                          13
14833 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                                           0x00002000U
14834
14835 /*Reserved. Return zeroes on reads.*/
14836 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL
14837 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
14838 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK
14839 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
14840 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT                                  10
14841 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
14842
14843 /*Data Slew Rate*/
14844 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL
14845 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
14846 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK
14847 #define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                                           0x01264000
14848 #define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                                            8
14849 #define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                                             0x00000300U
14850
14851 /*DQS_N Resistor*/
14852 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL
14853 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
14854 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK
14855 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                                        0x01264000
14856 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                                         4
14857 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                                          0x000000F0U
14858
14859 /*DQS Resistor*/
14860 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL
14861 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
14862 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK
14863 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                                         0x01264000
14864 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                                          0
14865 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                                           0x0000000FU
14866
14867 /*Reserved. Return zeroes on reads.*/
14868 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL
14869 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
14870 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK
14871 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
14872 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT                                  24
14873 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
14874
14875 /*Configurable Read Data Enable*/
14876 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL
14877 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
14878 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK
14879 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                                          0x00141800
14880 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                                           23
14881 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                                            0x00800000U
14882
14883 /*OX Extension during Post-amble*/
14884 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL
14885 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
14886 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK
14887 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                                         0x00141800
14888 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                                          20
14889 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                                           0x00700000U
14890
14891 /*OE Extension during Pre-amble*/
14892 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL
14893 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
14894 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK
14895 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                                         0x00141800
14896 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                                          18
14897 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                                           0x000C0000U
14898
14899 /*Reserved. Return zeroes on reads.*/
14900 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL
14901 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
14902 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK
14903 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
14904 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                                     17
14905 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                                      0x00020000U
14906
14907 /*I/O Assisted Gate Select*/
14908 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL
14909 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
14910 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK
14911 #define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                                           0x00141800
14912 #define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                                            16
14913 #define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                                             0x00010000U
14914
14915 /*I/O Loopback Select*/
14916 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL
14917 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
14918 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK
14919 #define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                                           0x00141800
14920 #define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                                            15
14921 #define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                                             0x00008000U
14922
14923 /*Reserved. Return zeroes on reads.*/
14924 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL
14925 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
14926 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK
14927 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
14928 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT                                  13
14929 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
14930
14931 /*Low Power Wakeup Threshold*/
14932 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL
14933 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
14934 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK
14935 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
14936 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
14937 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
14938
14939 /*Read Data Bus Inversion Enable*/
14940 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL
14941 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
14942 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK
14943 #define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                                           0x00141800
14944 #define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                                            8
14945 #define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                                             0x00000100U
14946
14947 /*Write Data Bus Inversion Enable*/
14948 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL
14949 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
14950 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK
14951 #define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                                           0x00141800
14952 #define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                                            7
14953 #define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                                             0x00000080U
14954
14955 /*PUB Read FIFO Bypass*/
14956 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL
14957 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
14958 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK
14959 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                                         0x00141800
14960 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                                          6
14961 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                                           0x00000040U
14962
14963 /*DATX8 Receive FIFO Read Mode*/
14964 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL
14965 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
14966 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK
14967 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                                         0x00141800
14968 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                                          4
14969 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                                           0x00000030U
14970
14971 /*Disables the Read FIFO Reset*/
14972 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL
14973 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
14974 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK
14975 #define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                                         0x00141800
14976 #define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                                          3
14977 #define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                                           0x00000008U
14978
14979 /*Read DQS Gate I/O Loopback*/
14980 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL
14981 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
14982 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK
14983 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                                         0x00141800
14984 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                                          1
14985 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                                           0x00000006U
14986
14987 /*Reserved. Return zeroes on reads.*/
14988 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL
14989 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
14990 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK
14991 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
14992 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                                      0
14993 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                                       0x00000001U
14994
14995 /*Reserved. Return zeroes on reads.*/
14996 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL
14997 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
14998 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK
14999 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                                      0x00000000
15000 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                                       31
15001 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                                        0x80000000U
15002
15003 /*PVREF_DAC REFSEL range select*/
15004 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL
15005 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
15006 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK
15007 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15008 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                                        28
15009 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                                         0x70000000U
15010
15011 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15012 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL
15013 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
15014 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK
15015 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15016 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                                         25
15017 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                                          0x0E000000U
15018
15019 /*DX IO Mode*/
15020 #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL
15021 #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
15022 #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK
15023 #define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                                            0x00000000
15024 #define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                                             22
15025 #define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                                              0x01C00000U
15026
15027 /*DX IO Transmitter Mode*/
15028 #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL
15029 #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
15030 #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK
15031 #define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                                            0x00000000
15032 #define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                                             11
15033 #define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                                              0x003FF800U
15034
15035 /*DX IO Receiver Mode*/
15036 #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL
15037 #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
15038 #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK
15039 #define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                                            0x00000000
15040 #define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                                             0
15041 #define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                                              0x000007FFU
15042
15043 /*Reserved. Return zeroes on reads.*/
15044 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
15045 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
15046 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK
15047 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
15048 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT                                  25
15049 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15050
15051 /*Read Path Rise-to-Rise Mode*/
15052 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL
15053 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
15054 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK
15055 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                                        0x01264000
15056 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                                         24
15057 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                                          0x01000000U
15058
15059 /*Reserved. Return zeroes on reads.*/
15060 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL
15061 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
15062 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK
15063 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
15064 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT                                  22
15065 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15066
15067 /*Write Path Rise-to-Rise Mode*/
15068 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL
15069 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
15070 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK
15071 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15072 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                                         21
15073 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                                          0x00200000U
15074
15075 /*DQS Gate Extension*/
15076 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL
15077 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
15078 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK
15079 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                                          0x01264000
15080 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                                           19
15081 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                                            0x00180000U
15082
15083 /*Low Power PLL Power Down*/
15084 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL
15085 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
15086 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK
15087 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15088 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                                         18
15089 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                                          0x00040000U
15090
15091 /*Low Power I/O Power Down*/
15092 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL
15093 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
15094 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK
15095 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15096 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                                          17
15097 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                                           0x00020000U
15098
15099 /*Reserved. Return zeroes on reads.*/
15100 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL
15101 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
15102 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK
15103 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15104 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT                                  15
15105 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15106
15107 /*QS Counter Enable*/
15108 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL
15109 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
15110 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK
15111 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15112 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                                         14
15113 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                                          0x00004000U
15114
15115 /*Unused DQ I/O Mode*/
15116 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL
15117 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
15118 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK
15119 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15120 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                                          13
15121 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                                           0x00002000U
15122
15123 /*Reserved. Return zeroes on reads.*/
15124 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL
15125 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
15126 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK
15127 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15128 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT                                  10
15129 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15130
15131 /*Data Slew Rate*/
15132 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL
15133 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
15134 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK
15135 #define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                                           0x01264000
15136 #define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                                            8
15137 #define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                                             0x00000300U
15138
15139 /*DQS_N Resistor*/
15140 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL
15141 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
15142 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK
15143 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15144 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                                         4
15145 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                                          0x000000F0U
15146
15147 /*DQS Resistor*/
15148 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL
15149 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
15150 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK
15151 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                                         0x01264000
15152 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                                          0
15153 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                                           0x0000000FU
15154
15155 /*Reserved. Return zeroes on reads.*/
15156 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL
15157 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
15158 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK
15159 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15160 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT                                  24
15161 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15162
15163 /*Configurable Read Data Enable*/
15164 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL
15165 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
15166 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK
15167 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                                          0x00141800
15168 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                                           23
15169 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                                            0x00800000U
15170
15171 /*OX Extension during Post-amble*/
15172 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL
15173 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
15174 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK
15175 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                                         0x00141800
15176 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                                          20
15177 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                                           0x00700000U
15178
15179 /*OE Extension during Pre-amble*/
15180 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL
15181 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
15182 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK
15183 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                                         0x00141800
15184 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                                          18
15185 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                                           0x000C0000U
15186
15187 /*Reserved. Return zeroes on reads.*/
15188 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL
15189 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
15190 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK
15191 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
15192 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                                     17
15193 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                                      0x00020000U
15194
15195 /*I/O Assisted Gate Select*/
15196 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL
15197 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
15198 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK
15199 #define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                                           0x00141800
15200 #define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                                            16
15201 #define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                                             0x00010000U
15202
15203 /*I/O Loopback Select*/
15204 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL
15205 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
15206 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK
15207 #define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                                           0x00141800
15208 #define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                                            15
15209 #define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                                             0x00008000U
15210
15211 /*Reserved. Return zeroes on reads.*/
15212 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL
15213 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
15214 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK
15215 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
15216 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT                                  13
15217 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
15218
15219 /*Low Power Wakeup Threshold*/
15220 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL
15221 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
15222 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK
15223 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
15224 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
15225 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
15226
15227 /*Read Data Bus Inversion Enable*/
15228 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL
15229 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
15230 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK
15231 #define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                                           0x00141800
15232 #define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                                            8
15233 #define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                                             0x00000100U
15234
15235 /*Write Data Bus Inversion Enable*/
15236 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL
15237 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
15238 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK
15239 #define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                                           0x00141800
15240 #define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                                            7
15241 #define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                                             0x00000080U
15242
15243 /*PUB Read FIFO Bypass*/
15244 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL
15245 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
15246 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK
15247 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                                         0x00141800
15248 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                                          6
15249 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                                           0x00000040U
15250
15251 /*DATX8 Receive FIFO Read Mode*/
15252 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL
15253 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
15254 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK
15255 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                                         0x00141800
15256 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                                          4
15257 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                                           0x00000030U
15258
15259 /*Disables the Read FIFO Reset*/
15260 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL
15261 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
15262 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK
15263 #define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                                         0x00141800
15264 #define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                                          3
15265 #define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                                           0x00000008U
15266
15267 /*Read DQS Gate I/O Loopback*/
15268 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL
15269 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
15270 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK
15271 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                                         0x00141800
15272 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                                          1
15273 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                                           0x00000006U
15274
15275 /*Reserved. Return zeroes on reads.*/
15276 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL
15277 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
15278 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK
15279 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
15280 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                                      0
15281 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                                       0x00000001U
15282
15283 /*Reserved. Return zeroes on reads.*/
15284 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL
15285 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
15286 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK
15287 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                                      0x00000000
15288 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                                       31
15289 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                                        0x80000000U
15290
15291 /*PVREF_DAC REFSEL range select*/
15292 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL
15293 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
15294 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK
15295 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15296 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                                        28
15297 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                                         0x70000000U
15298
15299 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15300 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL
15301 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
15302 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK
15303 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15304 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                                         25
15305 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                                          0x0E000000U
15306
15307 /*DX IO Mode*/
15308 #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL
15309 #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
15310 #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK
15311 #define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                                            0x00000000
15312 #define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                                             22
15313 #define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                                              0x01C00000U
15314
15315 /*DX IO Transmitter Mode*/
15316 #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL
15317 #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
15318 #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK
15319 #define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                                            0x00000000
15320 #define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                                             11
15321 #define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                                              0x003FF800U
15322
15323 /*DX IO Receiver Mode*/
15324 #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL
15325 #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
15326 #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK
15327 #define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                                            0x00000000
15328 #define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                                             0
15329 #define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                                              0x000007FFU
15330
15331 /*Reserved. Return zeroes on reads.*/
15332 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
15333 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
15334 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK
15335 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
15336 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT                                  25
15337 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15338
15339 /*Read Path Rise-to-Rise Mode*/
15340 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL
15341 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
15342 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK
15343 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                                        0x01264000
15344 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                                         24
15345 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                                          0x01000000U
15346
15347 /*Reserved. Return zeroes on reads.*/
15348 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL
15349 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
15350 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK
15351 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
15352 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT                                  22
15353 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15354
15355 /*Write Path Rise-to-Rise Mode*/
15356 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL
15357 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
15358 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK
15359 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15360 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                                         21
15361 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                                          0x00200000U
15362
15363 /*DQS Gate Extension*/
15364 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL
15365 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
15366 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK
15367 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                                          0x01264000
15368 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                                           19
15369 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                                            0x00180000U
15370
15371 /*Low Power PLL Power Down*/
15372 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL
15373 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
15374 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK
15375 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15376 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                                         18
15377 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                                          0x00040000U
15378
15379 /*Low Power I/O Power Down*/
15380 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL
15381 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
15382 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK
15383 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15384 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                                          17
15385 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                                           0x00020000U
15386
15387 /*Reserved. Return zeroes on reads.*/
15388 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL
15389 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
15390 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK
15391 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15392 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT                                  15
15393 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15394
15395 /*QS Counter Enable*/
15396 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL
15397 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
15398 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK
15399 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15400 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                                         14
15401 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                                          0x00004000U
15402
15403 /*Unused DQ I/O Mode*/
15404 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL
15405 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
15406 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK
15407 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15408 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                                          13
15409 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                                           0x00002000U
15410
15411 /*Reserved. Return zeroes on reads.*/
15412 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL
15413 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
15414 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK
15415 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15416 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT                                  10
15417 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15418
15419 /*Data Slew Rate*/
15420 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL
15421 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
15422 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK
15423 #define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                                           0x01264000
15424 #define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                                            8
15425 #define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                                             0x00000300U
15426
15427 /*DQS_N Resistor*/
15428 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL
15429 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
15430 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK
15431 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15432 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                                         4
15433 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                                          0x000000F0U
15434
15435 /*DQS Resistor*/
15436 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL
15437 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
15438 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK
15439 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                                         0x01264000
15440 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                                          0
15441 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                                           0x0000000FU
15442
15443 /*Reserved. Return zeroes on reads.*/
15444 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL
15445 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
15446 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK
15447 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15448 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT                                  24
15449 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15450
15451 /*Configurable Read Data Enable*/
15452 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL
15453 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
15454 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK
15455 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                                          0x00141800
15456 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                                           23
15457 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                                            0x00800000U
15458
15459 /*OX Extension during Post-amble*/
15460 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL
15461 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
15462 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK
15463 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                                         0x00141800
15464 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                                          20
15465 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                                           0x00700000U
15466
15467 /*OE Extension during Pre-amble*/
15468 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL
15469 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
15470 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK
15471 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                                         0x00141800
15472 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                                          18
15473 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                                           0x000C0000U
15474
15475 /*Reserved. Return zeroes on reads.*/
15476 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL
15477 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
15478 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK
15479 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
15480 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                                     17
15481 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                                      0x00020000U
15482
15483 /*I/O Assisted Gate Select*/
15484 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL
15485 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
15486 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK
15487 #define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                                           0x00141800
15488 #define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                                            16
15489 #define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                                             0x00010000U
15490
15491 /*I/O Loopback Select*/
15492 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL
15493 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
15494 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK
15495 #define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                                           0x00141800
15496 #define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                                            15
15497 #define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                                             0x00008000U
15498
15499 /*Reserved. Return zeroes on reads.*/
15500 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL
15501 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
15502 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK
15503 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
15504 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT                                  13
15505 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
15506
15507 /*Low Power Wakeup Threshold*/
15508 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL
15509 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
15510 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK
15511 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
15512 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
15513 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
15514
15515 /*Read Data Bus Inversion Enable*/
15516 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL
15517 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
15518 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK
15519 #define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                                           0x00141800
15520 #define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                                            8
15521 #define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                                             0x00000100U
15522
15523 /*Write Data Bus Inversion Enable*/
15524 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL
15525 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
15526 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK
15527 #define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                                           0x00141800
15528 #define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                                            7
15529 #define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                                             0x00000080U
15530
15531 /*PUB Read FIFO Bypass*/
15532 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL
15533 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
15534 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK
15535 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                                         0x00141800
15536 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                                          6
15537 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                                           0x00000040U
15538
15539 /*DATX8 Receive FIFO Read Mode*/
15540 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL
15541 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
15542 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK
15543 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                                         0x00141800
15544 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                                          4
15545 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                                           0x00000030U
15546
15547 /*Disables the Read FIFO Reset*/
15548 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL
15549 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
15550 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK
15551 #define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                                         0x00141800
15552 #define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                                          3
15553 #define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                                           0x00000008U
15554
15555 /*Read DQS Gate I/O Loopback*/
15556 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL
15557 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
15558 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK
15559 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                                         0x00141800
15560 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                                          1
15561 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                                           0x00000006U
15562
15563 /*Reserved. Return zeroes on reads.*/
15564 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL
15565 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
15566 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK
15567 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
15568 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                                      0
15569 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                                       0x00000001U
15570
15571 /*Reserved. Return zeroes on reads.*/
15572 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL
15573 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
15574 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK
15575 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                                      0x00000000
15576 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                                       31
15577 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                                        0x80000000U
15578
15579 /*PVREF_DAC REFSEL range select*/
15580 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL
15581 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
15582 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK
15583 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15584 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                                        28
15585 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                                         0x70000000U
15586
15587 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15588 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL
15589 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
15590 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK
15591 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15592 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                                         25
15593 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                                          0x0E000000U
15594
15595 /*DX IO Mode*/
15596 #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL
15597 #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
15598 #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK
15599 #define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                                            0x00000000
15600 #define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                                             22
15601 #define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                                              0x01C00000U
15602
15603 /*DX IO Transmitter Mode*/
15604 #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL
15605 #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
15606 #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK
15607 #define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                                            0x00000000
15608 #define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                                             11
15609 #define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                                              0x003FF800U
15610
15611 /*DX IO Receiver Mode*/
15612 #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL
15613 #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
15614 #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK
15615 #define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                                            0x00000000
15616 #define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                                             0
15617 #define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                                              0x000007FFU
15618
15619 /*Reserved. Return zeroes on reads.*/
15620 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
15621 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
15622 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK
15623 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
15624 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT                                  25
15625 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15626
15627 /*Read Path Rise-to-Rise Mode*/
15628 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL
15629 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
15630 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK
15631 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                                        0x01264000
15632 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                                         24
15633 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                                          0x01000000U
15634
15635 /*Reserved. Return zeroes on reads.*/
15636 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL
15637 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
15638 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK
15639 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
15640 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT                                  22
15641 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15642
15643 /*Write Path Rise-to-Rise Mode*/
15644 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL
15645 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
15646 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK
15647 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                                        0x01264000
15648 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                                         21
15649 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                                          0x00200000U
15650
15651 /*DQS Gate Extension*/
15652 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL
15653 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
15654 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK
15655 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                                          0x01264000
15656 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                                           19
15657 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                                            0x00180000U
15658
15659 /*Low Power PLL Power Down*/
15660 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL
15661 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
15662 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK
15663 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
15664 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                                         18
15665 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                                          0x00040000U
15666
15667 /*Low Power I/O Power Down*/
15668 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL
15669 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
15670 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK
15671 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                                         0x01264000
15672 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                                          17
15673 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                                           0x00020000U
15674
15675 /*Reserved. Return zeroes on reads.*/
15676 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL
15677 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
15678 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK
15679 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
15680 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT                                  15
15681 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15682
15683 /*QS Counter Enable*/
15684 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL
15685 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
15686 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK
15687 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
15688 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                                         14
15689 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                                          0x00004000U
15690
15691 /*Unused DQ I/O Mode*/
15692 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL
15693 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
15694 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK
15695 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                                         0x01264000
15696 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                                          13
15697 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                                           0x00002000U
15698
15699 /*Reserved. Return zeroes on reads.*/
15700 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL
15701 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
15702 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK
15703 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
15704 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT                                  10
15705 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15706
15707 /*Data Slew Rate*/
15708 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL
15709 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
15710 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK
15711 #define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                                           0x01264000
15712 #define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                                            8
15713 #define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                                             0x00000300U
15714
15715 /*DQS_N Resistor*/
15716 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL
15717 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
15718 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK
15719 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                                        0x01264000
15720 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                                         4
15721 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                                          0x000000F0U
15722
15723 /*DQS Resistor*/
15724 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL
15725 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
15726 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK
15727 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                                         0x01264000
15728 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                                          0
15729 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                                           0x0000000FU
15730
15731 /*Reserved. Return zeroes on reads.*/
15732 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL
15733 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
15734 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK
15735 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
15736 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT                                  24
15737 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
15738
15739 /*Configurable Read Data Enable*/
15740 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL
15741 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
15742 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK
15743 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                                          0x00141800
15744 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                                           23
15745 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                                            0x00800000U
15746
15747 /*OX Extension during Post-amble*/
15748 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL
15749 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
15750 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK
15751 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                                         0x00141800
15752 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                                          20
15753 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                                           0x00700000U
15754
15755 /*OE Extension during Pre-amble*/
15756 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL
15757 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
15758 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK
15759 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                                         0x00141800
15760 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                                          18
15761 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                                           0x000C0000U
15762
15763 /*Reserved. Return zeroes on reads.*/
15764 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL
15765 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
15766 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK
15767 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
15768 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                                     17
15769 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                                      0x00020000U
15770
15771 /*I/O Assisted Gate Select*/
15772 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL
15773 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
15774 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK
15775 #define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                                           0x00141800
15776 #define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                                            16
15777 #define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                                             0x00010000U
15778
15779 /*I/O Loopback Select*/
15780 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL
15781 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
15782 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK
15783 #define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                                           0x00141800
15784 #define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                                            15
15785 #define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                                             0x00008000U
15786
15787 /*Reserved. Return zeroes on reads.*/
15788 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL
15789 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
15790 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK
15791 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
15792 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT                                  13
15793 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
15794
15795 /*Low Power Wakeup Threshold*/
15796 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL
15797 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
15798 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK
15799 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
15800 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
15801 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
15802
15803 /*Read Data Bus Inversion Enable*/
15804 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL
15805 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
15806 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK
15807 #define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                                           0x00141800
15808 #define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                                            8
15809 #define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                                             0x00000100U
15810
15811 /*Write Data Bus Inversion Enable*/
15812 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL
15813 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
15814 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK
15815 #define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                                           0x00141800
15816 #define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                                            7
15817 #define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                                             0x00000080U
15818
15819 /*PUB Read FIFO Bypass*/
15820 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL
15821 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
15822 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK
15823 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                                         0x00141800
15824 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                                          6
15825 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                                           0x00000040U
15826
15827 /*DATX8 Receive FIFO Read Mode*/
15828 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL
15829 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
15830 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK
15831 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                                         0x00141800
15832 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                                          4
15833 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                                           0x00000030U
15834
15835 /*Disables the Read FIFO Reset*/
15836 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL
15837 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
15838 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK
15839 #define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                                         0x00141800
15840 #define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                                          3
15841 #define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                                           0x00000008U
15842
15843 /*Read DQS Gate I/O Loopback*/
15844 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL
15845 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
15846 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK
15847 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                                         0x00141800
15848 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                                          1
15849 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                                           0x00000006U
15850
15851 /*Reserved. Return zeroes on reads.*/
15852 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL
15853 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
15854 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK
15855 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
15856 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                                      0
15857 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                                       0x00000001U
15858
15859 /*Reserved. Return zeroes on reads.*/
15860 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL
15861 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
15862 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK
15863 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                                      0x00000000
15864 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                                       31
15865 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                                        0x80000000U
15866
15867 /*PVREF_DAC REFSEL range select*/
15868 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL
15869 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
15870 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK
15871 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                                       0x00000000
15872 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                                        28
15873 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                                         0x70000000U
15874
15875 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15876 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL
15877 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
15878 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK
15879 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                                        0x00000000
15880 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                                         25
15881 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                                          0x0E000000U
15882
15883 /*DX IO Mode*/
15884 #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL
15885 #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
15886 #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK
15887 #define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                                            0x00000000
15888 #define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                                             22
15889 #define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                                              0x01C00000U
15890
15891 /*DX IO Transmitter Mode*/
15892 #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL
15893 #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
15894 #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK
15895 #define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                                            0x00000000
15896 #define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                                             11
15897 #define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                                              0x003FF800U
15898
15899 /*DX IO Receiver Mode*/
15900 #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL
15901 #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
15902 #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK
15903 #define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                                            0x00000000
15904 #define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                                             0
15905 #define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                                              0x000007FFU
15906
15907 /*Reserved. Return zeroes on reads.*/
15908 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL
15909 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
15910 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK
15911 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL                                 0x00000000
15912 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT                                  25
15913 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
15914
15915 /*Read Path Rise-to-Rise Mode*/
15916 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL
15917 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
15918 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK
15919 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                                        0x00000000
15920 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                                         24
15921 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                                          0x01000000U
15922
15923 /*Reserved. Return zeroes on reads.*/
15924 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL
15925 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
15926 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK
15927 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL                                 0x00000000
15928 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT                                  22
15929 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
15930
15931 /*Write Path Rise-to-Rise Mode*/
15932 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL
15933 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
15934 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK
15935 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                                        0x00000000
15936 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                                         21
15937 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                                          0x00200000U
15938
15939 /*DQS Gate Extension*/
15940 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL
15941 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
15942 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK
15943 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                                          0x00000000
15944 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                                           19
15945 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                                            0x00180000U
15946
15947 /*Low Power PLL Power Down*/
15948 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL
15949 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
15950 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK
15951 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                                        0x00000000
15952 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                                         18
15953 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                                          0x00040000U
15954
15955 /*Low Power I/O Power Down*/
15956 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL
15957 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
15958 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK
15959 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                                         0x00000000
15960 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                                          17
15961 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                                           0x00020000U
15962
15963 /*Reserved. Return zeroes on reads.*/
15964 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL
15965 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
15966 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK
15967 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL                                 0x00000000
15968 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT                                  15
15969 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK                                   0x00018000U
15970
15971 /*QS Counter Enable*/
15972 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL
15973 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
15974 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK
15975 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                                        0x00000000
15976 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                                         14
15977 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                                          0x00004000U
15978
15979 /*Unused DQ I/O Mode*/
15980 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL
15981 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
15982 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK
15983 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                                         0x00000000
15984 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                                          13
15985 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                                           0x00002000U
15986
15987 /*Reserved. Return zeroes on reads.*/
15988 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL
15989 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
15990 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK
15991 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL                                 0x00000000
15992 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT                                  10
15993 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
15994
15995 /*Data Slew Rate*/
15996 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL
15997 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
15998 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK
15999 #define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                                           0x00000000
16000 #define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                                            8
16001 #define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                                             0x00000300U
16002
16003 /*DQS# Resistor*/
16004 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL
16005 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
16006 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK
16007 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                                        0x00000000
16008 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                                         4
16009 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                                          0x000000F0U
16010
16011 /*DQS Resistor*/
16012 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL
16013 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
16014 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK
16015 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                                         0x00000000
16016 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                                          0
16017 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                                           0x0000000FU
16018
16019 /*Reserved. Return zeroes on reads.*/
16020 #undef DDR_PHY_PIR_RESERVED_31_DEFVAL
16021 #undef DDR_PHY_PIR_RESERVED_31_SHIFT
16022 #undef DDR_PHY_PIR_RESERVED_31_MASK
16023 #define DDR_PHY_PIR_RESERVED_31_DEFVAL                                             0x00000000
16024 #define DDR_PHY_PIR_RESERVED_31_SHIFT                                              31
16025 #define DDR_PHY_PIR_RESERVED_31_MASK                                               0x80000000U
16026
16027 /*Impedance Calibration Bypass*/
16028 #undef DDR_PHY_PIR_ZCALBYP_DEFVAL
16029 #undef DDR_PHY_PIR_ZCALBYP_SHIFT
16030 #undef DDR_PHY_PIR_ZCALBYP_MASK
16031 #define DDR_PHY_PIR_ZCALBYP_DEFVAL                                                 0x00000000
16032 #define DDR_PHY_PIR_ZCALBYP_SHIFT                                                  30
16033 #define DDR_PHY_PIR_ZCALBYP_MASK                                                   0x40000000U
16034
16035 /*Digital Delay Line (DDL) Calibration Pause*/
16036 #undef DDR_PHY_PIR_DCALPSE_DEFVAL
16037 #undef DDR_PHY_PIR_DCALPSE_SHIFT
16038 #undef DDR_PHY_PIR_DCALPSE_MASK
16039 #define DDR_PHY_PIR_DCALPSE_DEFVAL                                                 0x00000000
16040 #define DDR_PHY_PIR_DCALPSE_SHIFT                                                  29
16041 #define DDR_PHY_PIR_DCALPSE_MASK                                                   0x20000000U
16042
16043 /*Reserved. Return zeroes on reads.*/
16044 #undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL
16045 #undef DDR_PHY_PIR_RESERVED_28_21_SHIFT
16046 #undef DDR_PHY_PIR_RESERVED_28_21_MASK
16047 #define DDR_PHY_PIR_RESERVED_28_21_DEFVAL                                          0x00000000
16048 #define DDR_PHY_PIR_RESERVED_28_21_SHIFT                                           21
16049 #define DDR_PHY_PIR_RESERVED_28_21_MASK                                            0x1FE00000U
16050
16051 /*Write DQS2DQ Training*/
16052 #undef DDR_PHY_PIR_DQS2DQ_DEFVAL
16053 #undef DDR_PHY_PIR_DQS2DQ_SHIFT
16054 #undef DDR_PHY_PIR_DQS2DQ_MASK
16055 #define DDR_PHY_PIR_DQS2DQ_DEFVAL                                                  0x00000000
16056 #define DDR_PHY_PIR_DQS2DQ_SHIFT                                                   20
16057 #define DDR_PHY_PIR_DQS2DQ_MASK                                                    0x00100000U
16058
16059 /*RDIMM Initialization*/
16060 #undef DDR_PHY_PIR_RDIMMINIT_DEFVAL
16061 #undef DDR_PHY_PIR_RDIMMINIT_SHIFT
16062 #undef DDR_PHY_PIR_RDIMMINIT_MASK
16063 #define DDR_PHY_PIR_RDIMMINIT_DEFVAL                                               0x00000000
16064 #define DDR_PHY_PIR_RDIMMINIT_SHIFT                                                19
16065 #define DDR_PHY_PIR_RDIMMINIT_MASK                                                 0x00080000U
16066
16067 /*Controller DRAM Initialization*/
16068 #undef DDR_PHY_PIR_CTLDINIT_DEFVAL
16069 #undef DDR_PHY_PIR_CTLDINIT_SHIFT
16070 #undef DDR_PHY_PIR_CTLDINIT_MASK
16071 #define DDR_PHY_PIR_CTLDINIT_DEFVAL                                                0x00000000
16072 #define DDR_PHY_PIR_CTLDINIT_SHIFT                                                 18
16073 #define DDR_PHY_PIR_CTLDINIT_MASK                                                  0x00040000U
16074
16075 /*VREF Training*/
16076 #undef DDR_PHY_PIR_VREF_DEFVAL
16077 #undef DDR_PHY_PIR_VREF_SHIFT
16078 #undef DDR_PHY_PIR_VREF_MASK
16079 #define DDR_PHY_PIR_VREF_DEFVAL                                                    0x00000000
16080 #define DDR_PHY_PIR_VREF_SHIFT                                                     17
16081 #define DDR_PHY_PIR_VREF_MASK                                                      0x00020000U
16082
16083 /*Static Read Training*/
16084 #undef DDR_PHY_PIR_SRD_DEFVAL
16085 #undef DDR_PHY_PIR_SRD_SHIFT
16086 #undef DDR_PHY_PIR_SRD_MASK
16087 #define DDR_PHY_PIR_SRD_DEFVAL                                                     0x00000000
16088 #define DDR_PHY_PIR_SRD_SHIFT                                                      16
16089 #define DDR_PHY_PIR_SRD_MASK                                                       0x00010000U
16090
16091 /*Write Data Eye Training*/
16092 #undef DDR_PHY_PIR_WREYE_DEFVAL
16093 #undef DDR_PHY_PIR_WREYE_SHIFT
16094 #undef DDR_PHY_PIR_WREYE_MASK
16095 #define DDR_PHY_PIR_WREYE_DEFVAL                                                   0x00000000
16096 #define DDR_PHY_PIR_WREYE_SHIFT                                                    15
16097 #define DDR_PHY_PIR_WREYE_MASK                                                     0x00008000U
16098
16099 /*Read Data Eye Training*/
16100 #undef DDR_PHY_PIR_RDEYE_DEFVAL
16101 #undef DDR_PHY_PIR_RDEYE_SHIFT
16102 #undef DDR_PHY_PIR_RDEYE_MASK
16103 #define DDR_PHY_PIR_RDEYE_DEFVAL                                                   0x00000000
16104 #define DDR_PHY_PIR_RDEYE_SHIFT                                                    14
16105 #define DDR_PHY_PIR_RDEYE_MASK                                                     0x00004000U
16106
16107 /*Write Data Bit Deskew*/
16108 #undef DDR_PHY_PIR_WRDSKW_DEFVAL
16109 #undef DDR_PHY_PIR_WRDSKW_SHIFT
16110 #undef DDR_PHY_PIR_WRDSKW_MASK
16111 #define DDR_PHY_PIR_WRDSKW_DEFVAL                                                  0x00000000
16112 #define DDR_PHY_PIR_WRDSKW_SHIFT                                                   13
16113 #define DDR_PHY_PIR_WRDSKW_MASK                                                    0x00002000U
16114
16115 /*Read Data Bit Deskew*/
16116 #undef DDR_PHY_PIR_RDDSKW_DEFVAL
16117 #undef DDR_PHY_PIR_RDDSKW_SHIFT
16118 #undef DDR_PHY_PIR_RDDSKW_MASK
16119 #define DDR_PHY_PIR_RDDSKW_DEFVAL                                                  0x00000000
16120 #define DDR_PHY_PIR_RDDSKW_SHIFT                                                   12
16121 #define DDR_PHY_PIR_RDDSKW_MASK                                                    0x00001000U
16122
16123 /*Write Leveling Adjust*/
16124 #undef DDR_PHY_PIR_WLADJ_DEFVAL
16125 #undef DDR_PHY_PIR_WLADJ_SHIFT
16126 #undef DDR_PHY_PIR_WLADJ_MASK
16127 #define DDR_PHY_PIR_WLADJ_DEFVAL                                                   0x00000000
16128 #define DDR_PHY_PIR_WLADJ_SHIFT                                                    11
16129 #define DDR_PHY_PIR_WLADJ_MASK                                                     0x00000800U
16130
16131 /*Read DQS Gate Training*/
16132 #undef DDR_PHY_PIR_QSGATE_DEFVAL
16133 #undef DDR_PHY_PIR_QSGATE_SHIFT
16134 #undef DDR_PHY_PIR_QSGATE_MASK
16135 #define DDR_PHY_PIR_QSGATE_DEFVAL                                                  0x00000000
16136 #define DDR_PHY_PIR_QSGATE_SHIFT                                                   10
16137 #define DDR_PHY_PIR_QSGATE_MASK                                                    0x00000400U
16138
16139 /*Write Leveling*/
16140 #undef DDR_PHY_PIR_WL_DEFVAL
16141 #undef DDR_PHY_PIR_WL_SHIFT
16142 #undef DDR_PHY_PIR_WL_MASK
16143 #define DDR_PHY_PIR_WL_DEFVAL                                                      0x00000000
16144 #define DDR_PHY_PIR_WL_SHIFT                                                       9
16145 #define DDR_PHY_PIR_WL_MASK                                                        0x00000200U
16146
16147 /*DRAM Initialization*/
16148 #undef DDR_PHY_PIR_DRAMINIT_DEFVAL
16149 #undef DDR_PHY_PIR_DRAMINIT_SHIFT
16150 #undef DDR_PHY_PIR_DRAMINIT_MASK
16151 #define DDR_PHY_PIR_DRAMINIT_DEFVAL                                                0x00000000
16152 #define DDR_PHY_PIR_DRAMINIT_SHIFT                                                 8
16153 #define DDR_PHY_PIR_DRAMINIT_MASK                                                  0x00000100U
16154
16155 /*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/
16156 #undef DDR_PHY_PIR_DRAMRST_DEFVAL
16157 #undef DDR_PHY_PIR_DRAMRST_SHIFT
16158 #undef DDR_PHY_PIR_DRAMRST_MASK
16159 #define DDR_PHY_PIR_DRAMRST_DEFVAL                                                 0x00000000
16160 #define DDR_PHY_PIR_DRAMRST_SHIFT                                                  7
16161 #define DDR_PHY_PIR_DRAMRST_MASK                                                   0x00000080U
16162
16163 /*PHY Reset*/
16164 #undef DDR_PHY_PIR_PHYRST_DEFVAL
16165 #undef DDR_PHY_PIR_PHYRST_SHIFT
16166 #undef DDR_PHY_PIR_PHYRST_MASK
16167 #define DDR_PHY_PIR_PHYRST_DEFVAL                                                  0x00000000
16168 #define DDR_PHY_PIR_PHYRST_SHIFT                                                   6
16169 #define DDR_PHY_PIR_PHYRST_MASK                                                    0x00000040U
16170
16171 /*Digital Delay Line (DDL) Calibration*/
16172 #undef DDR_PHY_PIR_DCAL_DEFVAL
16173 #undef DDR_PHY_PIR_DCAL_SHIFT
16174 #undef DDR_PHY_PIR_DCAL_MASK
16175 #define DDR_PHY_PIR_DCAL_DEFVAL                                                    0x00000000
16176 #define DDR_PHY_PIR_DCAL_SHIFT                                                     5
16177 #define DDR_PHY_PIR_DCAL_MASK                                                      0x00000020U
16178
16179 /*PLL Initialiazation*/
16180 #undef DDR_PHY_PIR_PLLINIT_DEFVAL
16181 #undef DDR_PHY_PIR_PLLINIT_SHIFT
16182 #undef DDR_PHY_PIR_PLLINIT_MASK
16183 #define DDR_PHY_PIR_PLLINIT_DEFVAL                                                 0x00000000
16184 #define DDR_PHY_PIR_PLLINIT_SHIFT                                                  4
16185 #define DDR_PHY_PIR_PLLINIT_MASK                                                   0x00000010U
16186
16187 /*Reserved. Return zeroes on reads.*/
16188 #undef DDR_PHY_PIR_RESERVED_3_DEFVAL
16189 #undef DDR_PHY_PIR_RESERVED_3_SHIFT
16190 #undef DDR_PHY_PIR_RESERVED_3_MASK
16191 #define DDR_PHY_PIR_RESERVED_3_DEFVAL                                              0x00000000
16192 #define DDR_PHY_PIR_RESERVED_3_SHIFT                                               3
16193 #define DDR_PHY_PIR_RESERVED_3_MASK                                                0x00000008U
16194
16195 /*CA Training*/
16196 #undef DDR_PHY_PIR_CA_DEFVAL
16197 #undef DDR_PHY_PIR_CA_SHIFT
16198 #undef DDR_PHY_PIR_CA_MASK
16199 #define DDR_PHY_PIR_CA_DEFVAL                                                      0x00000000
16200 #define DDR_PHY_PIR_CA_SHIFT                                                       2
16201 #define DDR_PHY_PIR_CA_MASK                                                        0x00000004U
16202
16203 /*Impedance Calibration*/
16204 #undef DDR_PHY_PIR_ZCAL_DEFVAL
16205 #undef DDR_PHY_PIR_ZCAL_SHIFT
16206 #undef DDR_PHY_PIR_ZCAL_MASK
16207 #define DDR_PHY_PIR_ZCAL_DEFVAL                                                    0x00000000
16208 #define DDR_PHY_PIR_ZCAL_SHIFT                                                     1
16209 #define DDR_PHY_PIR_ZCAL_MASK                                                      0x00000002U
16210
16211 /*Initialization Trigger*/
16212 #undef DDR_PHY_PIR_INIT_DEFVAL
16213 #undef DDR_PHY_PIR_INIT_SHIFT
16214 #undef DDR_PHY_PIR_INIT_MASK
16215 #define DDR_PHY_PIR_INIT_DEFVAL                                                    0x00000000
16216 #define DDR_PHY_PIR_INIT_SHIFT                                                     0
16217 #define DDR_PHY_PIR_INIT_MASK                                                      0x00000001U
16218 #undef IOU_SLCR_MIO_PIN_0_OFFSET
16219 #define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
16220 #undef IOU_SLCR_MIO_PIN_1_OFFSET
16221 #define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
16222 #undef IOU_SLCR_MIO_PIN_2_OFFSET
16223 #define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
16224 #undef IOU_SLCR_MIO_PIN_3_OFFSET
16225 #define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
16226 #undef IOU_SLCR_MIO_PIN_4_OFFSET
16227 #define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
16228 #undef IOU_SLCR_MIO_PIN_5_OFFSET
16229 #define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
16230 #undef IOU_SLCR_MIO_PIN_6_OFFSET
16231 #define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
16232 #undef IOU_SLCR_MIO_PIN_7_OFFSET
16233 #define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
16234 #undef IOU_SLCR_MIO_PIN_8_OFFSET
16235 #define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
16236 #undef IOU_SLCR_MIO_PIN_9_OFFSET
16237 #define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
16238 #undef IOU_SLCR_MIO_PIN_10_OFFSET
16239 #define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
16240 #undef IOU_SLCR_MIO_PIN_11_OFFSET
16241 #define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
16242 #undef IOU_SLCR_MIO_PIN_12_OFFSET
16243 #define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
16244 #undef IOU_SLCR_MIO_PIN_13_OFFSET
16245 #define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
16246 #undef IOU_SLCR_MIO_PIN_14_OFFSET
16247 #define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
16248 #undef IOU_SLCR_MIO_PIN_15_OFFSET
16249 #define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
16250 #undef IOU_SLCR_MIO_PIN_16_OFFSET
16251 #define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
16252 #undef IOU_SLCR_MIO_PIN_17_OFFSET
16253 #define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
16254 #undef IOU_SLCR_MIO_PIN_18_OFFSET
16255 #define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
16256 #undef IOU_SLCR_MIO_PIN_19_OFFSET
16257 #define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
16258 #undef IOU_SLCR_MIO_PIN_20_OFFSET
16259 #define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
16260 #undef IOU_SLCR_MIO_PIN_21_OFFSET
16261 #define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
16262 #undef IOU_SLCR_MIO_PIN_22_OFFSET
16263 #define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
16264 #undef IOU_SLCR_MIO_PIN_23_OFFSET
16265 #define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
16266 #undef IOU_SLCR_MIO_PIN_24_OFFSET
16267 #define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
16268 #undef IOU_SLCR_MIO_PIN_25_OFFSET
16269 #define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
16270 #undef IOU_SLCR_MIO_PIN_26_OFFSET
16271 #define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
16272 #undef IOU_SLCR_MIO_PIN_27_OFFSET
16273 #define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
16274 #undef IOU_SLCR_MIO_PIN_28_OFFSET
16275 #define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
16276 #undef IOU_SLCR_MIO_PIN_29_OFFSET
16277 #define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
16278 #undef IOU_SLCR_MIO_PIN_30_OFFSET
16279 #define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
16280 #undef IOU_SLCR_MIO_PIN_31_OFFSET
16281 #define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
16282 #undef IOU_SLCR_MIO_PIN_32_OFFSET
16283 #define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
16284 #undef IOU_SLCR_MIO_PIN_33_OFFSET
16285 #define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
16286 #undef IOU_SLCR_MIO_PIN_34_OFFSET
16287 #define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
16288 #undef IOU_SLCR_MIO_PIN_35_OFFSET
16289 #define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
16290 #undef IOU_SLCR_MIO_PIN_36_OFFSET
16291 #define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
16292 #undef IOU_SLCR_MIO_PIN_37_OFFSET
16293 #define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
16294 #undef IOU_SLCR_MIO_PIN_38_OFFSET
16295 #define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
16296 #undef IOU_SLCR_MIO_PIN_39_OFFSET
16297 #define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
16298 #undef IOU_SLCR_MIO_PIN_40_OFFSET
16299 #define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
16300 #undef IOU_SLCR_MIO_PIN_41_OFFSET
16301 #define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
16302 #undef IOU_SLCR_MIO_PIN_42_OFFSET
16303 #define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
16304 #undef IOU_SLCR_MIO_PIN_43_OFFSET
16305 #define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
16306 #undef IOU_SLCR_MIO_PIN_44_OFFSET
16307 #define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
16308 #undef IOU_SLCR_MIO_PIN_45_OFFSET
16309 #define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
16310 #undef IOU_SLCR_MIO_PIN_46_OFFSET
16311 #define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
16312 #undef IOU_SLCR_MIO_PIN_47_OFFSET
16313 #define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
16314 #undef IOU_SLCR_MIO_PIN_48_OFFSET
16315 #define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
16316 #undef IOU_SLCR_MIO_PIN_49_OFFSET
16317 #define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
16318 #undef IOU_SLCR_MIO_PIN_50_OFFSET
16319 #define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
16320 #undef IOU_SLCR_MIO_PIN_51_OFFSET
16321 #define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
16322 #undef IOU_SLCR_MIO_PIN_52_OFFSET
16323 #define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
16324 #undef IOU_SLCR_MIO_PIN_53_OFFSET
16325 #define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
16326 #undef IOU_SLCR_MIO_PIN_54_OFFSET
16327 #define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
16328 #undef IOU_SLCR_MIO_PIN_55_OFFSET
16329 #define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
16330 #undef IOU_SLCR_MIO_PIN_56_OFFSET
16331 #define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
16332 #undef IOU_SLCR_MIO_PIN_57_OFFSET
16333 #define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
16334 #undef IOU_SLCR_MIO_PIN_58_OFFSET
16335 #define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
16336 #undef IOU_SLCR_MIO_PIN_59_OFFSET
16337 #define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
16338 #undef IOU_SLCR_MIO_PIN_60_OFFSET
16339 #define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
16340 #undef IOU_SLCR_MIO_PIN_61_OFFSET
16341 #define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
16342 #undef IOU_SLCR_MIO_PIN_62_OFFSET
16343 #define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
16344 #undef IOU_SLCR_MIO_PIN_63_OFFSET
16345 #define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
16346 #undef IOU_SLCR_MIO_PIN_64_OFFSET
16347 #define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
16348 #undef IOU_SLCR_MIO_PIN_65_OFFSET
16349 #define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
16350 #undef IOU_SLCR_MIO_PIN_66_OFFSET
16351 #define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
16352 #undef IOU_SLCR_MIO_PIN_67_OFFSET
16353 #define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
16354 #undef IOU_SLCR_MIO_PIN_68_OFFSET
16355 #define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
16356 #undef IOU_SLCR_MIO_PIN_69_OFFSET
16357 #define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
16358 #undef IOU_SLCR_MIO_PIN_70_OFFSET
16359 #define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
16360 #undef IOU_SLCR_MIO_PIN_71_OFFSET
16361 #define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
16362 #undef IOU_SLCR_MIO_PIN_72_OFFSET
16363 #define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
16364 #undef IOU_SLCR_MIO_PIN_73_OFFSET
16365 #define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
16366 #undef IOU_SLCR_MIO_PIN_74_OFFSET
16367 #define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
16368 #undef IOU_SLCR_MIO_PIN_75_OFFSET
16369 #define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
16370 #undef IOU_SLCR_MIO_PIN_76_OFFSET
16371 #define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
16372 #undef IOU_SLCR_MIO_PIN_77_OFFSET
16373 #define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
16374 #undef IOU_SLCR_MIO_MST_TRI0_OFFSET
16375 #define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
16376 #undef IOU_SLCR_MIO_MST_TRI1_OFFSET
16377 #define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
16378 #undef IOU_SLCR_MIO_MST_TRI2_OFFSET
16379 #define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
16380 #undef IOU_SLCR_BANK0_CTRL0_OFFSET
16381 #define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
16382 #undef IOU_SLCR_BANK0_CTRL1_OFFSET
16383 #define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
16384 #undef IOU_SLCR_BANK0_CTRL3_OFFSET
16385 #define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
16386 #undef IOU_SLCR_BANK0_CTRL4_OFFSET
16387 #define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
16388 #undef IOU_SLCR_BANK0_CTRL5_OFFSET
16389 #define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
16390 #undef IOU_SLCR_BANK0_CTRL6_OFFSET
16391 #define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
16392 #undef IOU_SLCR_BANK1_CTRL0_OFFSET
16393 #define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
16394 #undef IOU_SLCR_BANK1_CTRL1_OFFSET
16395 #define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
16396 #undef IOU_SLCR_BANK1_CTRL3_OFFSET
16397 #define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
16398 #undef IOU_SLCR_BANK1_CTRL4_OFFSET
16399 #define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
16400 #undef IOU_SLCR_BANK1_CTRL5_OFFSET
16401 #define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
16402 #undef IOU_SLCR_BANK1_CTRL6_OFFSET
16403 #define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
16404 #undef IOU_SLCR_BANK2_CTRL0_OFFSET
16405 #define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
16406 #undef IOU_SLCR_BANK2_CTRL1_OFFSET
16407 #define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
16408 #undef IOU_SLCR_BANK2_CTRL3_OFFSET
16409 #define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
16410 #undef IOU_SLCR_BANK2_CTRL4_OFFSET
16411 #define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
16412 #undef IOU_SLCR_BANK2_CTRL5_OFFSET
16413 #define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
16414 #undef IOU_SLCR_BANK2_CTRL6_OFFSET
16415 #define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
16416 #undef IOU_SLCR_MIO_LOOPBACK_OFFSET
16417 #define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
16418
16419 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
16420 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
16421 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
16422 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
16423 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
16424 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
16425 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
16426
16427 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16428 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
16429 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
16430 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
16431 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
16432 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
16433 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
16434
16435 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
16436                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
16437 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
16438 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
16439 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
16440 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
16441 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
16442 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
16443
16444 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
16445                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
16446                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
16447                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
16448                 lk- (Trace Port Clock)*/
16449 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
16450 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
16451 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
16452 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
16453 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
16454 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
16455
16456 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
16457                 us)*/
16458 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
16459 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
16460 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
16461 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
16462 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
16463 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
16464
16465 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16466 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
16467 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
16468 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
16469 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
16470 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
16471 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
16472
16473 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
16474                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
16475 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
16476 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
16477 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
16478 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
16479 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
16480 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
16481
16482 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
16483                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
16484                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
16485                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
16486                 Signal)*/
16487 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
16488 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
16489 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
16490 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
16491 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
16492 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
16493
16494 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
16495 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
16496 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
16497 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
16498 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
16499 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
16500 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
16501
16502 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16503 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
16504 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
16505 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
16506 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
16507 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
16508 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
16509
16510 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
16511                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
16512 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
16513 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
16514 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
16515 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
16516 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
16517 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
16518
16519 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
16520                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
16521                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
16522                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
16523 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
16524 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
16525 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
16526 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
16527 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
16528 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
16529
16530 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
16531 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
16532 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
16533 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
16534 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
16535 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
16536 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
16537
16538 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16539 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
16540 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
16541 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
16542 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
16543 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
16544 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
16545
16546 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
16547                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
16548 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
16549 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
16550 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
16551 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
16552 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
16553 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
16554
16555 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
16556                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
16557                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
16558                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
16559                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
16560 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
16561 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
16562 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
16563 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
16564 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
16565 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
16566
16567 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
16568                 us)*/
16569 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
16570 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
16571 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
16572 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
16573 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
16574 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
16575
16576 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16577 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
16578 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
16579 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
16580 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
16581 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
16582 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
16583
16584 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
16585                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
16586 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
16587 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
16588 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
16589 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
16590 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
16591 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
16592
16593 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
16594                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
16595                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
16596                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
16597                 utput, tracedq[2]- (Trace Port Databus)*/
16598 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
16599 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
16600 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
16601 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
16602 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
16603 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
16604
16605 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
16606 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
16607 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
16608 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
16609 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
16610 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
16611 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
16612
16613 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16614 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
16615 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
16616 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
16617 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
16618 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
16619 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
16620
16621 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
16622                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
16623 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
16624 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
16625 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
16626 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
16627 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
16628 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
16629
16630 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
16631                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
16632                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
16633                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
16634                  trace, Output, tracedq[3]- (Trace Port Databus)*/
16635 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
16636 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
16637 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
16638 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
16639 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
16640 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
16641
16642 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
16643 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL
16644 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
16645 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK
16646 #define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
16647 #define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
16648 #define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
16649
16650 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16651 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL
16652 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
16653 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK
16654 #define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
16655 #define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
16656 #define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
16657
16658 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
16659                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
16660 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL
16661 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
16662 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK
16663 #define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
16664 #define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
16665 #define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
16666
16667 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
16668                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
16669                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
16670                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
16671                 Output, tracedq[4]- (Trace Port Databus)*/
16672 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL
16673 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
16674 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK
16675 #define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
16676 #define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
16677 #define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
16678
16679 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
16680 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL
16681 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
16682 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK
16683 #define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
16684 #define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
16685 #define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
16686
16687 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16688 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL
16689 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
16690 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK
16691 #define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
16692 #define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
16693 #define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
16694
16695 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
16696                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
16697 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL
16698 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
16699 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK
16700 #define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
16701 #define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
16702 #define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
16703
16704 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
16705                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
16706                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
16707                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
16708                 racedq[5]- (Trace Port Databus)*/
16709 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL
16710 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
16711 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK
16712 #define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
16713 #define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
16714 #define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
16715
16716 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
16717                 [0]- (QSPI Upper Databus)*/
16718 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL
16719 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
16720 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK
16721 #define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
16722 #define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
16723 #define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
16724
16725 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
16726 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL
16727 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
16728 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK
16729 #define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
16730 #define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
16731 #define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
16732
16733 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
16734                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
16735 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL
16736 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
16737 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK
16738 #define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
16739 #define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
16740 #define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
16741
16742 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
16743                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
16744                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
16745                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
16746                 ce Port Databus)*/
16747 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL
16748 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
16749 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK
16750 #define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
16751 #define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
16752 #define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
16753
16754 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
16755                 [1]- (QSPI Upper Databus)*/
16756 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL
16757 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
16758 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK
16759 #define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
16760 #define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
16761 #define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
16762
16763 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
16764 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL
16765 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
16766 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK
16767 #define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
16768 #define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
16769 #define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
16770
16771 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
16772                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
16773 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL
16774 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
16775 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK
16776 #define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
16777 #define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
16778 #define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
16779
16780 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
16781                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
16782                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
16783                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
16784                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
16785 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL
16786 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
16787 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK
16788 #define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
16789 #define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
16790 #define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
16791
16792 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
16793                 [2]- (QSPI Upper Databus)*/
16794 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL
16795 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
16796 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK
16797 #define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
16798 #define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
16799 #define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
16800
16801 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
16802 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL
16803 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
16804 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK
16805 #define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
16806 #define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
16807 #define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
16808
16809 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
16810                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
16811 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL
16812 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
16813 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK
16814 #define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
16815 #define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
16816 #define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
16817
16818 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
16819                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
16820                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
16821                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
16822                 t, tracedq[8]- (Trace Port Databus)*/
16823 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL
16824 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
16825 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK
16826 #define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
16827 #define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
16828 #define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
16829
16830 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
16831                 [3]- (QSPI Upper Databus)*/
16832 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL
16833 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
16834 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK
16835 #define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
16836 #define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
16837 #define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
16838
16839 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
16840 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL
16841 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
16842 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK
16843 #define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
16844 #define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
16845 #define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
16846
16847 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
16848                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
16849 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL
16850 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
16851 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK
16852 #define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
16853 #define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
16854 #define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
16855
16856 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
16857                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
16858                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
16859                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
16860                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
16861 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL
16862 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
16863 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK
16864 #define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
16865 #define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
16866 #define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
16867
16868 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
16869 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL
16870 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
16871 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK
16872 #define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
16873 #define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
16874 #define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
16875
16876 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
16877                 */
16878 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL
16879 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
16880 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK
16881 #define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
16882 #define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
16883 #define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
16884
16885 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
16886                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
16887 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL
16888 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
16889 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK
16890 #define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
16891 #define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
16892 #define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
16893
16894 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
16895                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
16896                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
16897                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
16898                 dq[10]- (Trace Port Databus)*/
16899 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL
16900 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
16901 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK
16902 #define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
16903 #define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
16904 #define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
16905
16906 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
16907 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL
16908 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
16909 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK
16910 #define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
16911 #define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
16912 #define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
16913
16914 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
16915 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL
16916 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
16917 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK
16918 #define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
16919 #define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
16920 #define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
16921
16922 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
16923                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
16924                  3= Not Used*/
16925 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL
16926 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
16927 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK
16928 #define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
16929 #define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
16930 #define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
16931
16932 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
16933                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
16934                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
16935                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
16936                 bus)*/
16937 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL
16938 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
16939 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK
16940 #define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
16941 #define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
16942 #define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
16943
16944 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
16945 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL
16946 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
16947 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK
16948 #define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
16949 #define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
16950 #define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
16951
16952 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
16953 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL
16954 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
16955 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK
16956 #define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
16957 #define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
16958 #define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
16959
16960 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
16961                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
16962                  3= Not Used*/
16963 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL
16964 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
16965 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK
16966 #define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
16967 #define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
16968 #define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
16969
16970 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
16971                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
16972                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
16973                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
16974 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL
16975 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
16976 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK
16977 #define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
16978 #define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
16979 #define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
16980
16981 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
16982 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL
16983 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
16984 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK
16985 #define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
16986 #define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
16987 #define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
16988
16989 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
16990 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL
16991 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
16992 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK
16993 #define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
16994 #define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
16995 #define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
16996
16997 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
16998                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
16999                  3= Not Used*/
17000 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL
17001 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
17002 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK
17003 #define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
17004 #define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
17005 #define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
17006
17007 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
17008                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17009                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
17010                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
17011                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
17012 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL
17013 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
17014 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK
17015 #define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
17016 #define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
17017 #define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
17018
17019 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17020 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
17021 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
17022 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
17023 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
17024 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
17025 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
17026
17027 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
17028                 ata Bus)*/
17029 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
17030 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
17031 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
17032 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
17033 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
17034 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
17035
17036 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
17037                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
17038                  3= Not Used*/
17039 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
17040 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
17041 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
17042 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
17043 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
17044 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
17045
17046 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
17047                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17048                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
17049                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
17050                  Output, tracedq[14]- (Trace Port Databus)*/
17051 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
17052 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
17053 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
17054 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
17055 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
17056 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
17057
17058 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17059 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
17060 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
17061 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
17062 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
17063 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
17064 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
17065
17066 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
17067                 ata Bus)*/
17068 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
17069 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
17070 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
17071 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
17072 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
17073 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
17074
17075 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
17076                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
17077                  3= Not Used*/
17078 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
17079 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
17080 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
17081 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
17082 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
17083 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
17084
17085 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
17086                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17087                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
17088                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
17089                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
17090 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
17091 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
17092 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
17093 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
17094 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
17095 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
17096
17097 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17098 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
17099 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
17100 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
17101 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
17102 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
17103 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
17104
17105 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
17106                 ata Bus)*/
17107 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
17108 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
17109 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
17110 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
17111 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
17112 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
17113
17114 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
17115                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
17116                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17117 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
17118 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
17119 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
17120 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
17121 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
17122 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
17123
17124 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
17125                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17126                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
17127                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
17128 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
17129 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
17130 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
17131 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
17132 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
17133 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
17134
17135 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17136 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
17137 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
17138 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
17139 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
17140 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
17141 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
17142
17143 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
17144                 ata Bus)*/
17145 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
17146 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
17147 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
17148 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
17149 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
17150 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
17151
17152 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
17153                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
17154                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17155 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
17156 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
17157 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
17158 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
17159 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
17160 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
17161
17162 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
17163                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17164                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
17165                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
17166 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
17167 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
17168 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
17169 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
17170 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
17171 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
17172
17173 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17174 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
17175 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
17176 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
17177 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
17178 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
17179 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
17180
17181 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
17182                 ata Bus)*/
17183 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
17184 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
17185 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
17186 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
17187 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
17188 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
17189
17190 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
17191                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
17192                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17193 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
17194 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
17195 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
17196 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
17197 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
17198 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
17199
17200 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
17201                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17202                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
17203                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
17204 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
17205 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
17206 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
17207 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
17208 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
17209 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
17210
17211 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17212 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
17213 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
17214 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
17215 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
17216 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
17217 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
17218
17219 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
17220                 ata Bus)*/
17221 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
17222 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
17223 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
17224 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
17225 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
17226 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
17227
17228 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
17229                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
17230                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17231 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
17232 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
17233 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
17234 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
17235 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
17236 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
17237
17238 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
17239                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17240                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
17241                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
17242                 UART receiver serial input) 7= Not Used*/
17243 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
17244 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
17245 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
17246 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
17247 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
17248 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
17249
17250 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17251 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL
17252 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
17253 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK
17254 #define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
17255 #define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
17256 #define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
17257
17258 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
17259 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL
17260 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
17261 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK
17262 #define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
17263 #define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
17264 #define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
17265
17266 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
17267                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17268 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL
17269 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
17270 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK
17271 #define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
17272 #define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
17273 #define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
17274
17275 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
17276                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17277                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
17278                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
17279                 sed*/
17280 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL
17281 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
17282 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK
17283 #define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
17284 #define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
17285 #define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
17286
17287 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17288 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL
17289 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
17290 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK
17291 #define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
17292 #define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
17293 #define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
17294
17295 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
17296                 ata Bus)*/
17297 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL
17298 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
17299 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK
17300 #define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
17301 #define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
17302 #define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
17303
17304 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
17305                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
17306                 */
17307 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL
17308 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
17309 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK
17310 #define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
17311 #define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
17312 #define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
17313
17314 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
17315                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17316                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
17317                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
17318                 tput) 7= Not Used*/
17319 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL
17320 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
17321 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK
17322 #define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
17323 #define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
17324 #define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
17325
17326 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17327 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
17328 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
17329 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
17330 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
17331 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
17332 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
17333
17334 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
17335                 ata Bus)*/
17336 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
17337 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
17338 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
17339 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
17340 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
17341 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
17342
17343 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
17344                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
17345                  Tamper)*/
17346 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
17347 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
17348 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
17349 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
17350 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
17351 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
17352
17353 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
17354                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17355                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
17356                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
17357 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
17358 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
17359 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
17360 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
17361 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
17362 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
17363
17364 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17365 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
17366 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
17367 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
17368 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
17369 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
17370 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
17371
17372 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
17373 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
17374 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
17375 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
17376 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
17377 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
17378 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
17379
17380 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
17381                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
17382                 U Ext Tamper)*/
17383 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
17384 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
17385 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
17386 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
17387 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
17388 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
17389
17390 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
17391                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17392                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
17393                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
17394 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
17395 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
17396 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
17397 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
17398 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
17399 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
17400
17401 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
17402 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL
17403 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
17404 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK
17405 #define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
17406 #define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
17407 #define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
17408
17409 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
17410 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL
17411 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
17412 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK
17413 #define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
17414 #define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
17415 #define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
17416
17417 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
17418                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17419 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL
17420 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
17421 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK
17422 #define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
17423 #define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
17424 #define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
17425
17426 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
17427                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17428                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
17429                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
17430                 Trace Port Databus)*/
17431 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL
17432 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
17433 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK
17434 #define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
17435 #define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
17436 #define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
17437
17438 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
17439 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
17440 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
17441 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
17442 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
17443 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
17444 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
17445
17446 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
17447 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
17448 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
17449 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
17450 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
17451 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
17452 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
17453
17454 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
17455                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
17456                 t, dp_aux_data_out- (Dp Aux Data)*/
17457 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
17458 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
17459 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
17460 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
17461 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
17462 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
17463
17464 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
17465                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17466                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
17467                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
17468                 atabus)*/
17469 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
17470 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
17471 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
17472 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
17473 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
17474 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
17475
17476 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
17477 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
17478 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
17479 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
17480 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
17481 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
17482 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
17483
17484 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
17485 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
17486 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
17487 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
17488 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
17489 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
17490 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
17491
17492 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
17493                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
17494 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
17495 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
17496 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
17497 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
17498 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
17499 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
17500
17501 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
17502                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17503                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
17504                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
17505 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
17506 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
17507 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
17508 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
17509 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
17510 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
17511
17512 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
17513 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
17514 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
17515 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
17516 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
17517 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
17518 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
17519
17520 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17521 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
17522 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
17523 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
17524 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
17525 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
17526 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
17527
17528 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
17529                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
17530                 t, dp_aux_data_out- (Dp Aux Data)*/
17531 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
17532 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
17533 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
17534 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
17535 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
17536 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
17537
17538 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
17539                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17540                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
17541                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
17542                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
17543 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
17544 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
17545 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
17546 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
17547 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
17548 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
17549
17550 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
17551 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
17552 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
17553 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
17554 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
17555 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
17556 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
17557
17558 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17559 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
17560 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
17561 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
17562 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
17563 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
17564 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
17565
17566 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
17567                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
17568 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
17569 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
17570 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
17571 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
17572 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
17573 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
17574
17575 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
17576                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17577                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
17578                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
17579                  tracedq[8]- (Trace Port Databus)*/
17580 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
17581 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
17582 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
17583 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
17584 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
17585 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
17586
17587 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
17588 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL
17589 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
17590 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK
17591 #define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
17592 #define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
17593 #define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
17594
17595 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17596 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL
17597 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
17598 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK
17599 #define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
17600 #define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
17601 #define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
17602
17603 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
17604                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17605 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL
17606 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
17607 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK
17608 #define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
17609 #define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
17610 #define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
17611
17612 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
17613                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17614                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
17615                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
17616                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
17617 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL
17618 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
17619 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK
17620 #define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
17621 #define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
17622 #define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
17623
17624 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
17625 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL
17626 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
17627 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK
17628 #define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
17629 #define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
17630 #define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
17631
17632 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
17633                 */
17634 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL
17635 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
17636 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK
17637 #define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
17638 #define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
17639 #define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
17640
17641 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
17642                 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17643 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL
17644 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
17645 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK
17646 #define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
17647 #define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
17648 #define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
17649
17650 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
17651                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17652                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
17653                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
17654                 race, Output, tracedq[10]- (Trace Port Databus)*/
17655 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL
17656 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
17657 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK
17658 #define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
17659 #define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
17660 #define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
17661
17662 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
17663 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL
17664 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
17665 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK
17666 #define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
17667 #define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
17668 #define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
17669
17670 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17671 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL
17672 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
17673 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK
17674 #define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
17675 #define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
17676 #define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
17677
17678 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
17679                 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17680 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL
17681 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
17682 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK
17683 #define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
17684 #define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
17685 #define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
17686
17687 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
17688                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17689                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
17690                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
17691                 [11]- (Trace Port Databus)*/
17692 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL
17693 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
17694 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK
17695 #define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
17696 #define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
17697 #define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
17698
17699 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
17700 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL
17701 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
17702 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK
17703 #define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
17704 #define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
17705 #define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
17706
17707 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17708 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL
17709 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
17710 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK
17711 #define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
17712 #define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
17713 #define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
17714
17715 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
17716                 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
17717                 ut, dp_aux_data_out- (Dp Aux Data)*/
17718 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL
17719 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
17720 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK
17721 #define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
17722 #define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
17723 #define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
17724
17725 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
17726                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17727                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
17728                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
17729                 rt Databus)*/
17730 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL
17731 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
17732 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK
17733 #define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
17734 #define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
17735 #define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
17736
17737 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
17738 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL
17739 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
17740 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK
17741 #define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
17742 #define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
17743 #define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
17744
17745 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17746 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL
17747 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
17748 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK
17749 #define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
17750 #define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
17751 #define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
17752
17753 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
17754                 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
17755 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL
17756 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
17757 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK
17758 #define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
17759 #define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
17760 #define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
17761
17762 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
17763                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17764                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
17765                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
17766                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
17767 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL
17768 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
17769 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK
17770 #define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
17771 #define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
17772 #define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
17773
17774 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
17775 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL
17776 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
17777 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK
17778 #define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
17779 #define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
17780 #define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
17781
17782 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17783 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL
17784 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
17785 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK
17786 #define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
17787 #define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
17788 #define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
17789
17790 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
17791                 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
17792                 ut, dp_aux_data_out- (Dp Aux Data)*/
17793 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL
17794 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
17795 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK
17796 #define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
17797 #define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
17798 #define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
17799
17800 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
17801                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17802                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
17803                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
17804                  Output, tracedq[14]- (Trace Port Databus)*/
17805 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL
17806 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
17807 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK
17808 #define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
17809 #define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
17810 #define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
17811
17812 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
17813 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL
17814 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
17815 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK
17816 #define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
17817 #define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
17818 #define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
17819
17820 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
17821 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL
17822 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
17823 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK
17824 #define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
17825 #define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
17826 #define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
17827
17828 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
17829                 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
17830 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL
17831 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
17832 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK
17833 #define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
17834 #define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
17835 #define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
17836
17837 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
17838                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17839                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
17840                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
17841                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
17842 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL
17843 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
17844 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK
17845 #define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
17846 #define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
17847 #define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
17848
17849 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
17850 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL
17851 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
17852 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK
17853 #define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
17854 #define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
17855 #define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
17856
17857 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17858 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL
17859 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
17860 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK
17861 #define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
17862 #define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
17863 #define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
17864
17865 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
17866 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL
17867 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
17868 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK
17869 #define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
17870 #define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
17871 #define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
17872
17873 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
17874                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17875                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
17876                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
17877                 (Trace Port Clock)*/
17878 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL
17879 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
17880 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK
17881 #define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
17882 #define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
17883 #define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
17884
17885 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
17886 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL
17887 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
17888 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
17889 #define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
17890 #define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
17891 #define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
17892
17893 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17894 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL
17895 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
17896 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK
17897 #define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
17898 #define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
17899 #define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
17900
17901 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
17902                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
17903 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL
17904 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
17905 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK
17906 #define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
17907 #define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
17908 #define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
17909
17910 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
17911                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17912                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
17913                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
17914                 Control Signal)*/
17915 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL
17916 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
17917 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK
17918 #define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
17919 #define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
17920 #define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
17921
17922 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
17923 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL
17924 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
17925 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK
17926 #define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
17927 #define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
17928 #define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
17929
17930 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17931 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL
17932 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
17933 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK
17934 #define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
17935 #define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
17936 #define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
17937
17938 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
17939                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
17940 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL
17941 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
17942 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK
17943 #define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
17944 #define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
17945 #define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
17946
17947 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
17948                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17949                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
17950                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
17951 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL
17952 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
17953 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK
17954 #define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
17955 #define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
17956 #define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
17957
17958 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
17959 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL
17960 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
17961 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK
17962 #define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
17963 #define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
17964 #define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
17965
17966 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17967 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL
17968 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
17969 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK
17970 #define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
17971 #define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
17972 #define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
17973
17974 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
17975                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
17976 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL
17977 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
17978 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK
17979 #define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
17980 #define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
17981 #define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
17982
17983 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
17984                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17985                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
17986                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
17987                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
17988 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL
17989 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
17990 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK
17991 #define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
17992 #define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
17993 #define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
17994
17995 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
17996 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL
17997 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
17998 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK
17999 #define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
18000 #define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
18001 #define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
18002
18003 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18004 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL
18005 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
18006 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK
18007 #define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
18008 #define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
18009 #define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
18010
18011 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
18012                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
18013 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL
18014 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
18015 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK
18016 #define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
18017 #define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
18018 #define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
18019
18020 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
18021                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18022                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
18023                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
18024                 t, tracedq[2]- (Trace Port Databus)*/
18025 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL
18026 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
18027 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK
18028 #define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
18029 #define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
18030 #define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
18031
18032 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
18033 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL
18034 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
18035 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK
18036 #define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
18037 #define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
18038 #define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
18039
18040 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18041 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL
18042 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
18043 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK
18044 #define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
18045 #define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
18046 #define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
18047
18048 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
18049                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
18050 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL
18051 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
18052 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK
18053 #define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
18054 #define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
18055 #define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
18056
18057 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
18058                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18059                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
18060                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
18061                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
18062 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL
18063 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
18064 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK
18065 #define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
18066 #define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
18067 #define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
18068
18069 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
18070 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL
18071 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
18072 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK
18073 #define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
18074 #define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
18075 #define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
18076
18077 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18078 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL
18079 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
18080 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK
18081 #define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
18082 #define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
18083 #define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
18084
18085 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
18086                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
18087 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL
18088 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
18089 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK
18090 #define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
18091 #define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
18092 #define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
18093
18094 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
18095                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18096                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
18097                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
18098                  Not Used*/
18099 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL
18100 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
18101 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK
18102 #define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
18103 #define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
18104 #define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
18105
18106 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
18107 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
18108 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
18109 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
18110 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
18111 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
18112 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
18113
18114 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18115 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
18116 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
18117 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
18118 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
18119 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
18120 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
18121
18122 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
18123                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
18124 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
18125 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
18126 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
18127 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
18128 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
18129 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
18130
18131 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
18132                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18133                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
18134                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
18135 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
18136 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
18137 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
18138 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
18139 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
18140 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
18141
18142 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
18143 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
18144 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
18145 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
18146 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
18147 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
18148 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
18149
18150 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18151 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
18152 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
18153 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
18154 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
18155 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
18156 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
18157
18158 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
18159                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
18160 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
18161 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
18162 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
18163 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
18164 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
18165 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
18166
18167 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
18168                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18169                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
18170                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
18171 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
18172 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
18173 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
18174 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
18175 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
18176 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
18177
18178 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
18179 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
18180 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
18181 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
18182 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
18183 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
18184 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
18185
18186 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18187 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
18188 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
18189 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
18190 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
18191 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
18192 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
18193
18194 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
18195                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
18196 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
18197 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
18198 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
18199 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
18200 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
18201 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
18202
18203 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
18204                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18205                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
18206                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
18207                  (UART transmitter serial output) 7= Not Used*/
18208 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
18209 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
18210 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
18211 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
18212 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
18213 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
18214
18215 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
18216 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
18217 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
18218 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
18219 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
18220 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
18221 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
18222
18223 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18224 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
18225 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
18226 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
18227 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
18228 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
18229 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
18230
18231 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
18232                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
18233 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
18234 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
18235 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
18236 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
18237 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
18238 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
18239
18240 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
18241                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18242                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
18243                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
18244                 ed*/
18245 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
18246 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
18247 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
18248 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
18249 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
18250 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
18251
18252 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
18253 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
18254 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
18255 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
18256 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
18257 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
18258 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
18259
18260 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18261 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
18262 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
18263 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
18264 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
18265 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
18266 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
18267
18268 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
18269                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
18270 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
18271 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
18272 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
18273 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
18274 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
18275 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
18276
18277 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
18278                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18279                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
18280                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
18281                 7= Not Used*/
18282 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
18283 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
18284 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
18285 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
18286 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
18287 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
18288
18289 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
18290 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
18291 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
18292 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
18293 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
18294 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
18295 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
18296
18297 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18298 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
18299 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
18300 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
18301 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
18302 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
18303 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
18304
18305 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
18306                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
18307 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
18308 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
18309 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
18310 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
18311 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
18312 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
18313
18314 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
18315                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18316                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
18317                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
18318 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
18319 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
18320 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
18321 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
18322 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
18323 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
18324
18325 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
18326 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
18327 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
18328 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
18329 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
18330 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
18331 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
18332
18333 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18334 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
18335 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
18336 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
18337 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
18338 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
18339 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
18340
18341 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
18342 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
18343 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
18344 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
18345 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
18346 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
18347 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
18348
18349 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
18350                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18351                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
18352                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
18353                 serial output) 7= Not Used*/
18354 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
18355 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
18356 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
18357 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
18358 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
18359 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
18360
18361 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
18362 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
18363 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
18364 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
18365 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
18366 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
18367 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
18368
18369 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
18370 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
18371 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
18372 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
18373 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
18374 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
18375 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
18376
18377 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18378 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
18379 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
18380 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
18381 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
18382 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
18383 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
18384
18385 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
18386                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18387                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
18388                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
18389                 lk- (Trace Port Clock)*/
18390 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
18391 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
18392 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
18393 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
18394 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
18395 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
18396
18397 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
18398 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
18399 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
18400 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
18401 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
18402 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
18403 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
18404
18405 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
18406 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
18407 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
18408 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
18409 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
18410 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
18411 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
18412
18413 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18414 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
18415 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
18416 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
18417 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
18418 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
18419 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
18420
18421 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
18422                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18423                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
18424                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
18425                 Signal)*/
18426 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
18427 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
18428 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
18429 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
18430 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
18431 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
18432
18433 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
18434 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
18435 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
18436 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
18437 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
18438 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
18439 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
18440
18441 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18442                 ata[2]- (ULPI data bus)*/
18443 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
18444 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
18445 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
18446 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
18447 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
18448 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
18449
18450 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18451 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
18452 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
18453 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
18454 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
18455 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
18456 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
18457
18458 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
18459                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18460                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
18461                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
18462 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
18463 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
18464 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
18465 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
18466 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
18467 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
18468
18469 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
18470 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
18471 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
18472 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
18473 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
18474 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
18475 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
18476
18477 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
18478 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
18479 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
18480 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
18481 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
18482 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
18483 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
18484
18485 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18486 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
18487 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
18488 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
18489 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
18490 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
18491 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
18492
18493 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
18494                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18495                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
18496                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
18497                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
18498 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
18499 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
18500 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
18501 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
18502 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
18503 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
18504
18505 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
18506 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
18507 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
18508 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
18509 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
18510 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
18511 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
18512
18513 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18514                 ata[0]- (ULPI data bus)*/
18515 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
18516 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
18517 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
18518 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
18519 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
18520 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
18521
18522 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18523 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
18524 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
18525 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
18526 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
18527 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
18528 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
18529
18530 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
18531                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18532                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
18533                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
18534                 utput, tracedq[2]- (Trace Port Databus)*/
18535 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
18536 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
18537 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
18538 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
18539 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
18540 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
18541
18542 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
18543 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
18544 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
18545 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
18546 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
18547 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
18548 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
18549
18550 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18551                 ata[1]- (ULPI data bus)*/
18552 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
18553 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
18554 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
18555 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
18556 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
18557 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
18558
18559 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18560 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
18561 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
18562 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
18563 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
18564 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
18565 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
18566
18567 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
18568                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18569                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
18570                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
18571                  trace, Output, tracedq[3]- (Trace Port Databus)*/
18572 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
18573 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
18574 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
18575 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
18576 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
18577 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
18578
18579 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
18580 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
18581 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
18582 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
18583 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
18584 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
18585 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
18586
18587 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
18588 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
18589 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
18590 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
18591 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
18592 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
18593 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
18594
18595 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18596 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
18597 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
18598 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
18599 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
18600 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
18601 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
18602
18603 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
18604                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18605                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
18606                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
18607                 Trace Port Databus)*/
18608 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
18609 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
18610 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
18611 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
18612 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
18613 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
18614
18615 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
18616 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
18617 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
18618 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
18619 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
18620 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
18621 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
18622
18623 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18624                 ata[3]- (ULPI data bus)*/
18625 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
18626 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
18627 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
18628 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
18629 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
18630 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
18631
18632 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18633 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
18634 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
18635 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
18636 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
18637 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
18638 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
18639
18640 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
18641                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18642                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
18643                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
18644                 atabus)*/
18645 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
18646 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
18647 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
18648 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
18649 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
18650 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
18651
18652 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
18653 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
18654 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
18655 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
18656 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
18657 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
18658 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
18659
18660 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18661                 ata[4]- (ULPI data bus)*/
18662 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
18663 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
18664 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
18665 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
18666 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
18667 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
18668
18669 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18670 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
18671 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
18672 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
18673 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
18674 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
18675 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
18676
18677 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
18678                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18679                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
18680                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
18681 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
18682 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
18683 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
18684 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
18685 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
18686 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
18687
18688 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
18689 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
18690 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
18691 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
18692 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
18693 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
18694 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
18695
18696 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18697                 ata[5]- (ULPI data bus)*/
18698 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
18699 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
18700 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
18701 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
18702 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
18703 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
18704
18705 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18706 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
18707 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
18708 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
18709 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
18710 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
18711 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
18712
18713 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
18714                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18715                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
18716                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
18717                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
18718 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
18719 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
18720 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
18721 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
18722 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
18723 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
18724
18725 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
18726 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
18727 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
18728 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
18729 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
18730 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
18731 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
18732
18733 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18734                 ata[6]- (ULPI data bus)*/
18735 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
18736 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
18737 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
18738 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
18739 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
18740 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
18741
18742 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18743 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
18744 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
18745 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
18746 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
18747 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
18748 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
18749
18750 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
18751                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18752                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
18753                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
18754                 t, tracedq[8]- (Trace Port Databus)*/
18755 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
18756 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
18757 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
18758 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
18759 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
18760 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
18761
18762 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
18763 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
18764 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
18765 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
18766 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
18767 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
18768 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
18769
18770 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
18771                 ata[7]- (ULPI data bus)*/
18772 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
18773 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
18774 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
18775 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
18776 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
18777 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
18778
18779 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
18780 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
18781 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
18782 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
18783 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
18784 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
18785 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
18786
18787 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
18788                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18789                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
18790                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
18791                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
18792 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
18793 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
18794 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
18795 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
18796 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
18797 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
18798
18799 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
18800 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
18801 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
18802 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
18803 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
18804 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
18805 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
18806
18807 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
18808 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
18809 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
18810 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
18811 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
18812 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
18813 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
18814
18815 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
18816 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
18817 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
18818 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
18819 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
18820 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
18821 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
18822
18823 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
18824                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18825                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
18826                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
18827                  trace, Output, tracedq[10]- (Trace Port Databus)*/
18828 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
18829 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
18830 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
18831 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
18832 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
18833 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
18834
18835 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
18836 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
18837 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
18838 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
18839 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
18840 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
18841 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
18842
18843 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
18844 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
18845 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
18846 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
18847 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
18848 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
18849 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
18850
18851 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
18852 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
18853 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
18854 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
18855 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
18856 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
18857 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
18858
18859 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
18860                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18861                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
18862                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
18863                 dq[11]- (Trace Port Databus)*/
18864 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
18865 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
18866 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
18867 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
18868 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
18869 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
18870
18871 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
18872 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
18873 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
18874 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
18875 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
18876 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
18877 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
18878
18879 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
18880                 ata[2]- (ULPI data bus)*/
18881 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
18882 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
18883 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
18884 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
18885 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
18886 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
18887
18888 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
18889                  Indicator) 2= Not Used 3= Not Used*/
18890 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
18891 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
18892 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
18893 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
18894 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
18895 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
18896
18897 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
18898                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18899                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
18900                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
18901                 Port Databus)*/
18902 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
18903 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
18904 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
18905 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
18906 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
18907 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
18908
18909 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
18910 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
18911 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
18912 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
18913 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
18914 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
18915 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
18916
18917 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
18918 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
18919 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
18920 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
18921 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
18922 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
18923 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
18924
18925 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
18926                 bit Data bus) 2= Not Used 3= Not Used*/
18927 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
18928 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
18929 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
18930 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
18931 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
18932 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
18933
18934 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
18935                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18936                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
18937                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
18938                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
18939 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
18940 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
18941 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
18942 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
18943 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
18944 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
18945
18946 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
18947 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
18948 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
18949 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
18950 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
18951 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
18952 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
18953
18954 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
18955                 ata[0]- (ULPI data bus)*/
18956 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
18957 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
18958 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
18959 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
18960 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
18961 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
18962
18963 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
18964                 bit Data bus) 2= Not Used 3= Not Used*/
18965 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
18966 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
18967 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
18968 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
18969 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
18970 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
18971
18972 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
18973                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18974                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
18975                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
18976                  Output, tracedq[14]- (Trace Port Databus)*/
18977 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
18978 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
18979 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
18980 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
18981 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
18982 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
18983
18984 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
18985 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
18986 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
18987 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
18988 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
18989 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
18990 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
18991
18992 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
18993                 ata[1]- (ULPI data bus)*/
18994 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
18995 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
18996 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
18997 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
18998 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
18999 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
19000
19001 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
19002                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
19003 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
19004 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
19005 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
19006 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
19007 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
19008 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
19009
19010 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
19011                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19012                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
19013                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
19014                 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
19015 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
19016 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
19017 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
19018 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
19019 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
19020 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
19021
19022 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
19023 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
19024 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
19025 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
19026 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
19027 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
19028 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
19029
19030 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
19031 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
19032 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
19033 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
19034 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
19035 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
19036 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
19037
19038 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
19039                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
19040 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
19041 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
19042 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
19043 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
19044 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
19045 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
19046
19047 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
19048                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19049                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
19050                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
19051                 sed*/
19052 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
19053 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
19054 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
19055 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
19056 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
19057 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
19058
19059 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
19060 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
19061 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
19062 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
19063 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
19064 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
19065 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
19066
19067 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19068                 ata[3]- (ULPI data bus)*/
19069 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
19070 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
19071 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
19072 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
19073 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
19074 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
19075
19076 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
19077                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
19078 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
19079 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
19080 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
19081 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
19082 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
19083 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
19084
19085 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
19086                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19087                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
19088                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19089 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
19090 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
19091 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
19092 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
19093 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
19094 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
19095
19096 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
19097 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
19098 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
19099 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
19100 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
19101 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
19102 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
19103
19104 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19105                 ata[4]- (ULPI data bus)*/
19106 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
19107 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
19108 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
19109 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
19110 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
19111 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
19112
19113 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
19114                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
19115 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
19116 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
19117 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
19118 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
19119 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
19120 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
19121
19122 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
19123                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19124                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
19125                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
19126 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
19127 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
19128 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
19129 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
19130 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
19131 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
19132
19133 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
19134 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
19135 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
19136 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
19137 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
19138 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
19139 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
19140
19141 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19142                 ata[5]- (ULPI data bus)*/
19143 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
19144 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
19145 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
19146 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
19147 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
19148 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
19149
19150 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
19151                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
19152 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
19153 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
19154 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
19155 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
19156 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
19157 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
19158
19159 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
19160                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19161                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
19162                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
19163 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
19164 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
19165 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
19166 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
19167 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
19168 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
19169
19170 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
19171 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
19172 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
19173 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
19174 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
19175 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
19176 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
19177
19178 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19179                 ata[6]- (ULPI data bus)*/
19180 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
19181 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
19182 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
19183 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
19184 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
19185 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
19186
19187 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
19188                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
19189 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
19190 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
19191 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
19192 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
19193 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
19194 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
19195
19196 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
19197                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19198                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
19199                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
19200 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
19201 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
19202 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
19203 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
19204 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
19205 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
19206
19207 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
19208 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
19209 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
19210 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
19211 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
19212 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
19213 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
19214
19215 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19216                 ata[7]- (ULPI data bus)*/
19217 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
19218 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
19219 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
19220 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
19221 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
19222 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
19223
19224 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
19225                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
19226 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
19227 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
19228 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
19229 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
19230 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
19231 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
19232
19233 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
19234                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19235                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
19236                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19237 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
19238 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
19239 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
19240 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
19241 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
19242 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
19243
19244 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19245 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
19246 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
19247 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
19248 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
19249 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
19250 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
19251
19252 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19253 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
19254 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
19255 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
19256 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
19257 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
19258 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
19259
19260 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
19261                 _clk_out- (SDSDIO clock) 3= Not Used*/
19262 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
19263 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
19264 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
19265 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
19266 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
19267 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
19268
19269 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
19270                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19271                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
19272                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
19273 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
19274 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
19275 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
19276 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
19277 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
19278 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
19279
19280 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19281 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
19282 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
19283 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
19284 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
19285 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
19286 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
19287
19288 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19289 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
19290 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
19291 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
19292 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
19293 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
19294 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
19295
19296 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
19297 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
19298 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
19299 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
19300 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
19301 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
19302 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
19303
19304 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
19305                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19306                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
19307                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
19308                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
19309 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
19310 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
19311 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
19312 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
19313 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
19314 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
19315
19316 /*Master Tri-state Enable for pin 0, active high*/
19317 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
19318 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
19319 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
19320 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
19321 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
19322 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
19323
19324 /*Master Tri-state Enable for pin 1, active high*/
19325 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
19326 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
19327 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
19328 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
19329 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
19330 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
19331
19332 /*Master Tri-state Enable for pin 2, active high*/
19333 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
19334 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
19335 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
19336 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
19337 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
19338 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
19339
19340 /*Master Tri-state Enable for pin 3, active high*/
19341 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
19342 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
19343 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
19344 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
19345 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
19346 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
19347
19348 /*Master Tri-state Enable for pin 4, active high*/
19349 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
19350 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
19351 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
19352 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
19353 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
19354 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
19355
19356 /*Master Tri-state Enable for pin 5, active high*/
19357 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
19358 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
19359 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
19360 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
19361 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
19362 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
19363
19364 /*Master Tri-state Enable for pin 6, active high*/
19365 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL
19366 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
19367 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK
19368 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
19369 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
19370 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
19371
19372 /*Master Tri-state Enable for pin 7, active high*/
19373 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL
19374 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
19375 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK
19376 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
19377 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
19378 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
19379
19380 /*Master Tri-state Enable for pin 8, active high*/
19381 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL
19382 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
19383 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK
19384 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
19385 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
19386 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
19387
19388 /*Master Tri-state Enable for pin 9, active high*/
19389 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL
19390 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
19391 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK
19392 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
19393 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
19394 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
19395
19396 /*Master Tri-state Enable for pin 10, active high*/
19397 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL
19398 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
19399 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK
19400 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
19401 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
19402 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
19403
19404 /*Master Tri-state Enable for pin 11, active high*/
19405 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL
19406 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
19407 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK
19408 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
19409 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
19410 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
19411
19412 /*Master Tri-state Enable for pin 12, active high*/
19413 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL
19414 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
19415 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK
19416 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
19417 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
19418 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
19419
19420 /*Master Tri-state Enable for pin 13, active high*/
19421 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL
19422 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
19423 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK
19424 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
19425 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
19426 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
19427
19428 /*Master Tri-state Enable for pin 14, active high*/
19429 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL
19430 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
19431 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK
19432 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
19433 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
19434 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
19435
19436 /*Master Tri-state Enable for pin 15, active high*/
19437 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL
19438 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
19439 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK
19440 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
19441 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
19442 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
19443
19444 /*Master Tri-state Enable for pin 16, active high*/
19445 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
19446 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
19447 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
19448 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
19449 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
19450 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
19451
19452 /*Master Tri-state Enable for pin 17, active high*/
19453 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
19454 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
19455 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
19456 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
19457 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
19458 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
19459
19460 /*Master Tri-state Enable for pin 18, active high*/
19461 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
19462 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
19463 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
19464 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
19465 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
19466 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
19467
19468 /*Master Tri-state Enable for pin 19, active high*/
19469 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
19470 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
19471 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
19472 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
19473 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
19474 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
19475
19476 /*Master Tri-state Enable for pin 20, active high*/
19477 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
19478 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
19479 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
19480 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
19481 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
19482 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
19483
19484 /*Master Tri-state Enable for pin 21, active high*/
19485 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
19486 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
19487 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
19488 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
19489 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
19490 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
19491
19492 /*Master Tri-state Enable for pin 22, active high*/
19493 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL
19494 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
19495 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK
19496 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
19497 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
19498 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
19499
19500 /*Master Tri-state Enable for pin 23, active high*/
19501 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL
19502 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
19503 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK
19504 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
19505 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
19506 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
19507
19508 /*Master Tri-state Enable for pin 24, active high*/
19509 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
19510 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
19511 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
19512 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
19513 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
19514 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
19515
19516 /*Master Tri-state Enable for pin 25, active high*/
19517 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
19518 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
19519 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
19520 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
19521 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
19522 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
19523
19524 /*Master Tri-state Enable for pin 26, active high*/
19525 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL
19526 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
19527 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK
19528 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
19529 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
19530 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
19531
19532 /*Master Tri-state Enable for pin 27, active high*/
19533 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
19534 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
19535 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
19536 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
19537 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
19538 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
19539
19540 /*Master Tri-state Enable for pin 28, active high*/
19541 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
19542 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
19543 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
19544 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
19545 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
19546 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
19547
19548 /*Master Tri-state Enable for pin 29, active high*/
19549 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
19550 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
19551 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
19552 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
19553 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
19554 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
19555
19556 /*Master Tri-state Enable for pin 30, active high*/
19557 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
19558 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
19559 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
19560 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
19561 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
19562 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
19563
19564 /*Master Tri-state Enable for pin 31, active high*/
19565 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL
19566 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
19567 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK
19568 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
19569 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
19570 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
19571
19572 /*Master Tri-state Enable for pin 32, active high*/
19573 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL
19574 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
19575 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK
19576 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
19577 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
19578 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
19579
19580 /*Master Tri-state Enable for pin 33, active high*/
19581 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL
19582 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
19583 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK
19584 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
19585 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
19586 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
19587
19588 /*Master Tri-state Enable for pin 34, active high*/
19589 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL
19590 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
19591 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK
19592 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
19593 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
19594 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
19595
19596 /*Master Tri-state Enable for pin 35, active high*/
19597 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL
19598 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
19599 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK
19600 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
19601 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
19602 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
19603
19604 /*Master Tri-state Enable for pin 36, active high*/
19605 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL
19606 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
19607 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK
19608 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
19609 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
19610 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
19611
19612 /*Master Tri-state Enable for pin 37, active high*/
19613 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL
19614 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
19615 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK
19616 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
19617 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
19618 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
19619
19620 /*Master Tri-state Enable for pin 38, active high*/
19621 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL
19622 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
19623 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK
19624 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
19625 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
19626 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
19627
19628 /*Master Tri-state Enable for pin 39, active high*/
19629 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL
19630 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
19631 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK
19632 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
19633 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
19634 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
19635
19636 /*Master Tri-state Enable for pin 40, active high*/
19637 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL
19638 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
19639 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK
19640 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
19641 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
19642 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
19643
19644 /*Master Tri-state Enable for pin 41, active high*/
19645 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL
19646 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
19647 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK
19648 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
19649 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
19650 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
19651
19652 /*Master Tri-state Enable for pin 42, active high*/
19653 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL
19654 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
19655 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK
19656 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
19657 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
19658 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
19659
19660 /*Master Tri-state Enable for pin 43, active high*/
19661 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL
19662 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
19663 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK
19664 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
19665 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
19666 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
19667
19668 /*Master Tri-state Enable for pin 44, active high*/
19669 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL
19670 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
19671 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK
19672 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
19673 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
19674 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
19675
19676 /*Master Tri-state Enable for pin 45, active high*/
19677 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
19678 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
19679 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
19680 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
19681 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
19682 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
19683
19684 /*Master Tri-state Enable for pin 46, active high*/
19685 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
19686 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
19687 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
19688 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
19689 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
19690 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
19691
19692 /*Master Tri-state Enable for pin 47, active high*/
19693 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
19694 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
19695 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
19696 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
19697 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
19698 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
19699
19700 /*Master Tri-state Enable for pin 48, active high*/
19701 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
19702 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
19703 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
19704 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
19705 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
19706 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
19707
19708 /*Master Tri-state Enable for pin 49, active high*/
19709 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
19710 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
19711 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
19712 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
19713 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
19714 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
19715
19716 /*Master Tri-state Enable for pin 50, active high*/
19717 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
19718 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
19719 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
19720 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
19721 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
19722 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
19723
19724 /*Master Tri-state Enable for pin 51, active high*/
19725 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
19726 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
19727 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
19728 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
19729 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
19730 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
19731
19732 /*Master Tri-state Enable for pin 52, active high*/
19733 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
19734 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
19735 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
19736 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
19737 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
19738 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
19739
19740 /*Master Tri-state Enable for pin 53, active high*/
19741 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
19742 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
19743 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
19744 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
19745 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
19746 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
19747
19748 /*Master Tri-state Enable for pin 54, active high*/
19749 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
19750 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
19751 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
19752 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
19753 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
19754 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
19755
19756 /*Master Tri-state Enable for pin 55, active high*/
19757 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
19758 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
19759 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
19760 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
19761 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
19762 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
19763
19764 /*Master Tri-state Enable for pin 56, active high*/
19765 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
19766 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
19767 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
19768 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
19769 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
19770 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
19771
19772 /*Master Tri-state Enable for pin 57, active high*/
19773 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
19774 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
19775 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
19776 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
19777 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
19778 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
19779
19780 /*Master Tri-state Enable for pin 58, active high*/
19781 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
19782 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
19783 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
19784 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
19785 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
19786 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
19787
19788 /*Master Tri-state Enable for pin 59, active high*/
19789 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
19790 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
19791 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
19792 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
19793 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
19794 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
19795
19796 /*Master Tri-state Enable for pin 60, active high*/
19797 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
19798 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
19799 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
19800 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
19801 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
19802 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
19803
19804 /*Master Tri-state Enable for pin 61, active high*/
19805 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
19806 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
19807 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
19808 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
19809 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
19810 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
19811
19812 /*Master Tri-state Enable for pin 62, active high*/
19813 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
19814 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
19815 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
19816 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
19817 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
19818 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
19819
19820 /*Master Tri-state Enable for pin 63, active high*/
19821 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
19822 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
19823 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
19824 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
19825 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
19826 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
19827
19828 /*Master Tri-state Enable for pin 64, active high*/
19829 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
19830 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
19831 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
19832 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
19833 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
19834 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
19835
19836 /*Master Tri-state Enable for pin 65, active high*/
19837 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
19838 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
19839 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
19840 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
19841 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
19842 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
19843
19844 /*Master Tri-state Enable for pin 66, active high*/
19845 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
19846 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
19847 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
19848 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
19849 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
19850 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
19851
19852 /*Master Tri-state Enable for pin 67, active high*/
19853 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
19854 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
19855 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
19856 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
19857 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
19858 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
19859
19860 /*Master Tri-state Enable for pin 68, active high*/
19861 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
19862 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
19863 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
19864 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
19865 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
19866 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
19867
19868 /*Master Tri-state Enable for pin 69, active high*/
19869 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
19870 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
19871 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
19872 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
19873 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
19874 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
19875
19876 /*Master Tri-state Enable for pin 70, active high*/
19877 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
19878 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
19879 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
19880 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
19881 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
19882 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
19883
19884 /*Master Tri-state Enable for pin 71, active high*/
19885 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
19886 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
19887 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
19888 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
19889 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
19890 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
19891
19892 /*Master Tri-state Enable for pin 72, active high*/
19893 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
19894 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
19895 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
19896 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
19897 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
19898 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
19899
19900 /*Master Tri-state Enable for pin 73, active high*/
19901 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
19902 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
19903 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
19904 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
19905 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
19906 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
19907
19908 /*Master Tri-state Enable for pin 74, active high*/
19909 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
19910 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
19911 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
19912 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
19913 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
19914 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
19915
19916 /*Master Tri-state Enable for pin 75, active high*/
19917 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
19918 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
19919 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
19920 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
19921 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
19922 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
19923
19924 /*Master Tri-state Enable for pin 76, active high*/
19925 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
19926 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
19927 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
19928 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
19929 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
19930 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
19931
19932 /*Master Tri-state Enable for pin 77, active high*/
19933 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
19934 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
19935 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
19936 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
19937 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
19938 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
19939
19940 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19941 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
19942 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
19943 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK
19944 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
19945 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
19946 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
19947
19948 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19949 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
19950 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
19951 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK
19952 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
19953 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
19954 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
19955
19956 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19957 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
19958 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
19959 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK
19960 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
19961 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
19962 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
19963
19964 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19965 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
19966 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
19967 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK
19968 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
19969 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
19970 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
19971
19972 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19973 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
19974 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
19975 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK
19976 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
19977 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
19978 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
19979
19980 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19981 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
19982 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
19983 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK
19984 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
19985 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
19986 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
19987
19988 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19989 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
19990 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
19991 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK
19992 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
19993 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
19994 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
19995
19996 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
19997 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
19998 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
19999 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK
20000 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
20001 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
20002 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
20003
20004 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20005 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20006 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
20007 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK
20008 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20009 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
20010 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
20011
20012 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20013 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20014 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
20015 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK
20016 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20017 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
20018 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
20019
20020 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20021 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20022 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
20023 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK
20024 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20025 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
20026 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
20027
20028 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20029 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20030 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
20031 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK
20032 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20033 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
20034 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
20035
20036 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20037 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20038 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
20039 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK
20040 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20041 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
20042 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
20043
20044 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20045 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20046 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
20047 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK
20048 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20049 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
20050 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
20051
20052 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20053 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20054 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
20055 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK
20056 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20057 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
20058 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
20059
20060 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20061 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20062 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
20063 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK
20064 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20065 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
20066 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
20067
20068 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20069 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20070 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
20071 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK
20072 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20073 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
20074 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
20075
20076 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20077 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20078 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
20079 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK
20080 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20081 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
20082 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
20083
20084 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20085 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20086 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
20087 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK
20088 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20089 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
20090 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
20091
20092 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20093 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20094 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
20095 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK
20096 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20097 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
20098 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
20099
20100 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20101 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20102 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
20103 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK
20104 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20105 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
20106 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
20107
20108 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20109 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20110 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
20111 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK
20112 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20113 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
20114 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
20115
20116 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20117 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20118 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
20119 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK
20120 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20121 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
20122 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
20123
20124 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20125 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20126 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
20127 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK
20128 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20129 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
20130 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
20131
20132 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20133 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20134 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
20135 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK
20136 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20137 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
20138 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
20139
20140 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20141 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20142 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
20143 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK
20144 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20145 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
20146 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
20147
20148 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20149 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20150 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
20151 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK
20152 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20153 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
20154 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
20155
20156 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20157 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20158 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
20159 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK
20160 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20161 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
20162 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
20163
20164 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20165 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20166 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
20167 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK
20168 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20169 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
20170 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
20171
20172 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20173 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20174 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
20175 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK
20176 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20177 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
20178 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
20179
20180 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20181 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20182 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
20183 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK
20184 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20185 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
20186 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
20187
20188 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20189 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20190 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
20191 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK
20192 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20193 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
20194 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
20195
20196 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20197 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20198 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
20199 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK
20200 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20201 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
20202 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
20203
20204 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20205 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20206 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
20207 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK
20208 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20209 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
20210 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
20211
20212 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20213 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20214 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
20215 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK
20216 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20217 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
20218 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
20219
20220 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20221 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20222 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
20223 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK
20224 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20225 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
20226 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
20227
20228 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20229 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20230 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
20231 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK
20232 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20233 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
20234 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
20235
20236 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20237 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20238 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
20239 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK
20240 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20241 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
20242 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
20243
20244 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20245 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20246 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
20247 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK
20248 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20249 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
20250 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
20251
20252 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20253 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20254 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
20255 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK
20256 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20257 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
20258 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
20259
20260 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20261 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20262 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
20263 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK
20264 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20265 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
20266 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
20267
20268 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20269 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20270 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
20271 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK
20272 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20273 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
20274 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
20275
20276 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20277 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20278 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
20279 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK
20280 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20281 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
20282 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
20283
20284 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20285 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
20286 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
20287 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK
20288 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
20289 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
20290 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
20291
20292 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20293 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
20294 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
20295 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK
20296 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
20297 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
20298 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
20299
20300 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20301 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
20302 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
20303 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK
20304 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
20305 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
20306 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
20307
20308 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20309 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
20310 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
20311 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK
20312 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
20313 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
20314 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
20315
20316 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20317 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
20318 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
20319 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK
20320 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
20321 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
20322 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
20323
20324 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20325 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
20326 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
20327 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK
20328 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
20329 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
20330 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
20331
20332 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20333 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
20334 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
20335 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK
20336 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
20337 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
20338 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
20339
20340 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20341 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
20342 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
20343 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK
20344 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
20345 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
20346 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
20347
20348 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20349 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
20350 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
20351 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK
20352 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
20353 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
20354 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
20355
20356 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20357 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
20358 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
20359 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
20360 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
20361 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
20362 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
20363
20364 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20365 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
20366 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
20367 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
20368 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
20369 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
20370 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
20371
20372 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20373 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
20374 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
20375 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
20376 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
20377 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
20378 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
20379
20380 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20381 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
20382 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
20383 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
20384 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
20385 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
20386 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
20387
20388 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20389 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
20390 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
20391 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
20392 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
20393 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
20394 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
20395
20396 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20397 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
20398 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
20399 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
20400 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
20401 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
20402 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
20403
20404 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20405 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
20406 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
20407 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
20408 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
20409 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
20410 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
20411
20412 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20413 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
20414 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
20415 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
20416 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
20417 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
20418 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
20419
20420 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20421 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
20422 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
20423 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
20424 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
20425 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
20426 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
20427
20428 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20429 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
20430 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
20431 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
20432 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
20433 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
20434 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
20435
20436 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20437 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
20438 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
20439 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
20440 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
20441 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
20442 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
20443
20444 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20445 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
20446 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
20447 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
20448 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
20449 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
20450 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
20451
20452 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20453 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
20454 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
20455 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
20456 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
20457 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
20458 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
20459
20460 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20461 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
20462 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
20463 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
20464 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
20465 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
20466 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
20467
20468 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20469 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
20470 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
20471 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
20472 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
20473 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
20474 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
20475
20476 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20477 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
20478 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
20479 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
20480 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
20481 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
20482 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
20483
20484 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20485 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
20486 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
20487 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
20488 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
20489 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
20490 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
20491
20492 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20493 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
20494 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
20495 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
20496 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
20497 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
20498 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
20499
20500 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20501 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
20502 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
20503 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
20504 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
20505 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
20506 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
20507
20508 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20509 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
20510 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
20511 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
20512 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
20513 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
20514 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
20515
20516 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20517 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
20518 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
20519 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
20520 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
20521 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
20522 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
20523
20524 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20525 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
20526 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
20527 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
20528 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
20529 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
20530 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
20531
20532 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20533 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
20534 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
20535 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
20536 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
20537 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
20538 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
20539
20540 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20541 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
20542 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
20543 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
20544 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
20545 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
20546 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
20547
20548 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20549 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
20550 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
20551 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
20552 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
20553 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
20554 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
20555
20556 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20557 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
20558 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
20559 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
20560 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
20561 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
20562 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
20563
20564 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20565 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
20566 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
20567 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
20568 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
20569 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
20570 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
20571
20572 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20573 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
20574 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
20575 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
20576 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
20577 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
20578 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
20579
20580 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20581 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
20582 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
20583 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
20584 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
20585 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
20586 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
20587
20588 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20589 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
20590 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
20591 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
20592 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
20593 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
20594 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
20595
20596 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20597 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
20598 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
20599 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
20600 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
20601 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
20602 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
20603
20604 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20605 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
20606 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
20607 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
20608 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
20609 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
20610 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
20611
20612 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20613 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
20614 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
20615 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
20616 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
20617 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
20618 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
20619
20620 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20621 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
20622 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
20623 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
20624 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
20625 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
20626 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
20627
20628 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20629 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
20630 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
20631 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
20632 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
20633 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
20634 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
20635
20636 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20637 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
20638 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
20639 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
20640 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
20641 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
20642 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
20643
20644 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20645 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
20646 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
20647 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
20648 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
20649 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
20650 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
20651
20652 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20653 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
20654 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
20655 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
20656 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
20657 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
20658 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
20659
20660 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20661 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
20662 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
20663 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
20664 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
20665 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
20666 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
20667
20668 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20669 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
20670 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
20671 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
20672 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
20673 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
20674 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
20675
20676 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20677 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
20678 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
20679 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
20680 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
20681 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
20682 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
20683
20684 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20685 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
20686 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
20687 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
20688 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
20689 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
20690 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
20691
20692 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20693 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
20694 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
20695 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
20696 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
20697 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
20698 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
20699
20700 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20701 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
20702 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
20703 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
20704 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
20705 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
20706 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
20707
20708 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20709 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
20710 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
20711 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
20712 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
20713 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
20714 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
20715
20716 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20717 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
20718 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
20719 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
20720 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
20721 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
20722 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
20723
20724 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20725 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
20726 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
20727 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
20728 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
20729 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
20730 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
20731
20732 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20733 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
20734 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
20735 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
20736 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
20737 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
20738 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
20739
20740 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20741 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
20742 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
20743 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
20744 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
20745 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
20746 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
20747
20748 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20749 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
20750 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
20751 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
20752 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
20753 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
20754 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
20755
20756 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20757 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
20758 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
20759 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
20760 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
20761 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
20762 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
20763
20764 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20765 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
20766 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
20767 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
20768 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
20769 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
20770 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
20771
20772 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20773 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
20774 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
20775 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK
20776 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
20777 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
20778 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
20779
20780 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20781 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
20782 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
20783 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK
20784 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
20785 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
20786 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
20787
20788 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20789 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
20790 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
20791 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK
20792 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
20793 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
20794 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
20795
20796 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20797 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
20798 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
20799 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK
20800 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
20801 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
20802 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
20803
20804 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20805 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
20806 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
20807 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK
20808 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
20809 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
20810 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
20811
20812 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20813 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
20814 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
20815 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK
20816 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
20817 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
20818 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
20819
20820 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20821 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
20822 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
20823 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK
20824 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
20825 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
20826 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
20827
20828 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20829 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
20830 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
20831 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK
20832 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
20833 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
20834 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
20835
20836 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20837 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
20838 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
20839 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK
20840 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
20841 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
20842 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
20843
20844 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20845 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
20846 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
20847 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK
20848 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
20849 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
20850 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
20851
20852 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20853 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
20854 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
20855 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK
20856 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
20857 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
20858 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
20859
20860 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20861 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
20862 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
20863 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK
20864 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
20865 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
20866 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
20867
20868 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20869 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
20870 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
20871 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK
20872 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
20873 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
20874 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
20875
20876 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20877 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
20878 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
20879 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK
20880 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
20881 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
20882 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
20883
20884 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20885 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
20886 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
20887 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK
20888 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
20889 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
20890 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
20891
20892 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20893 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
20894 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
20895 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK
20896 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
20897 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
20898 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
20899
20900 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20901 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
20902 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
20903 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK
20904 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
20905 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
20906 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
20907
20908 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20909 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
20910 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
20911 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK
20912 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
20913 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
20914 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
20915
20916 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20917 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
20918 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
20919 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK
20920 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
20921 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
20922 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
20923
20924 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20925 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
20926 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
20927 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK
20928 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
20929 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
20930 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
20931
20932 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20933 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
20934 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
20935 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK
20936 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
20937 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
20938 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
20939
20940 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20941 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
20942 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
20943 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK
20944 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
20945 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
20946 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
20947
20948 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20949 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
20950 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
20951 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK
20952 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
20953 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
20954 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
20955
20956 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20957 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
20958 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
20959 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK
20960 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
20961 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
20962 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
20963
20964 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20965 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
20966 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
20967 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK
20968 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
20969 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
20970 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
20971
20972 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20973 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
20974 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
20975 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK
20976 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
20977 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
20978 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
20979
20980 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20981 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
20982 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
20983 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
20984 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
20985 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
20986 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
20987
20988 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20989 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
20990 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
20991 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
20992 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
20993 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
20994 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
20995
20996 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20997 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
20998 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
20999 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
21000 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
21001 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
21002 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
21003
21004 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21005 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21006 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
21007 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
21008 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21009 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
21010 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
21011
21012 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21013 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21014 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
21015 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
21016 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21017 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
21018 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
21019
21020 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21021 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21022 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
21023 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
21024 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21025 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
21026 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
21027
21028 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21029 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21030 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
21031 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
21032 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21033 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
21034 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
21035
21036 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21037 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21038 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
21039 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
21040 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21041 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
21042 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
21043
21044 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21045 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21046 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
21047 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
21048 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21049 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
21050 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
21051
21052 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21053 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21054 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
21055 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
21056 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21057 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
21058 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
21059
21060 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21061 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21062 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
21063 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
21064 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21065 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
21066 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
21067
21068 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21069 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21070 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
21071 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
21072 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21073 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
21074 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
21075
21076 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21077 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21078 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
21079 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
21080 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21081 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
21082 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
21083
21084 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21085 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21086 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
21087 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
21088 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21089 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
21090 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
21091
21092 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21093 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21094 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
21095 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
21096 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21097 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
21098 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
21099
21100 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21101 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21102 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
21103 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
21104 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21105 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
21106 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
21107
21108 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21109 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21110 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
21111 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
21112 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21113 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
21114 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
21115
21116 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21117 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21118 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
21119 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
21120 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21121 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
21122 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
21123
21124 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21125 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21126 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
21127 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
21128 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21129 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
21130 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
21131
21132 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21133 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21134 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
21135 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
21136 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21137 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
21138 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
21139
21140 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21141 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21142 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
21143 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
21144 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21145 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
21146 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
21147
21148 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21149 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21150 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
21151 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
21152 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21153 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
21154 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
21155
21156 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21157 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21158 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
21159 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
21160 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21161 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
21162 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
21163
21164 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21165 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21166 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
21167 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
21168 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21169 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
21170 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
21171
21172 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21173 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21174 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
21175 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
21176 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21177 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
21178 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
21179
21180 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21181 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21182 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
21183 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
21184 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21185 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
21186 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
21187
21188 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21189 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21190 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
21191 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK
21192 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21193 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
21194 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
21195
21196 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21197 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21198 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
21199 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK
21200 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21201 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
21202 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
21203
21204 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21205 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21206 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
21207 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK
21208 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21209 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
21210 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
21211
21212 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21213 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21214 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
21215 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK
21216 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21217 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
21218 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
21219
21220 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21221 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21222 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
21223 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK
21224 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21225 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
21226 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
21227
21228 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21229 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21230 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
21231 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK
21232 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21233 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
21234 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
21235
21236 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21237 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21238 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
21239 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK
21240 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21241 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
21242 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
21243
21244 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21245 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21246 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
21247 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK
21248 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21249 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
21250 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
21251
21252 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21253 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21254 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
21255 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK
21256 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21257 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
21258 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
21259
21260 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21261 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21262 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
21263 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK
21264 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21265 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
21266 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
21267
21268 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21269 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21270 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
21271 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK
21272 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21273 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
21274 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
21275
21276 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21277 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21278 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
21279 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK
21280 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21281 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
21282 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
21283
21284 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21285 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
21286 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
21287 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK
21288 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
21289 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
21290 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
21291
21292 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21293 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
21294 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
21295 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK
21296 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
21297 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
21298 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
21299
21300 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21301 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
21302 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
21303 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK
21304 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
21305 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
21306 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
21307
21308 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21309 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
21310 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
21311 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK
21312 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
21313 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
21314 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
21315
21316 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21317 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
21318 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
21319 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK
21320 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
21321 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
21322 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
21323
21324 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21325 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
21326 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
21327 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK
21328 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
21329 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
21330 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
21331
21332 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21333 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
21334 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
21335 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK
21336 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
21337 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
21338 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
21339
21340 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21341 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
21342 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
21343 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK
21344 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
21345 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
21346 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
21347
21348 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21349 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
21350 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
21351 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK
21352 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
21353 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
21354 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
21355
21356 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21357 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
21358 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
21359 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK
21360 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
21361 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
21362 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
21363
21364 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21365 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
21366 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
21367 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK
21368 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
21369 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
21370 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
21371
21372 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21373 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
21374 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
21375 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK
21376 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
21377 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
21378 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
21379
21380 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21381 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
21382 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
21383 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK
21384 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
21385 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
21386 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
21387
21388 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21389 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
21390 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
21391 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK
21392 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
21393 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
21394 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
21395
21396 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21397 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
21398 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
21399 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK
21400 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
21401 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
21402 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
21403
21404 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21405 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
21406 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
21407 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK
21408 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
21409 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
21410 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
21411
21412 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21413 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
21414 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
21415 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK
21416 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
21417 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
21418 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
21419
21420 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21421 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
21422 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
21423 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK
21424 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
21425 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
21426 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
21427
21428 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21429 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
21430 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
21431 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK
21432 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
21433 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
21434 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
21435
21436 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21437 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
21438 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
21439 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK
21440 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
21441 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
21442 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
21443
21444 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21445 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
21446 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
21447 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK
21448 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
21449 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
21450 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
21451
21452 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21453 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
21454 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
21455 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK
21456 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
21457 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
21458 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
21459
21460 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21461 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
21462 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
21463 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK
21464 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
21465 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
21466 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
21467
21468 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21469 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
21470 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
21471 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK
21472 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
21473 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
21474 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
21475
21476 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21477 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
21478 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
21479 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK
21480 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
21481 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
21482 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
21483
21484 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21485 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
21486 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
21487 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK
21488 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
21489 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
21490 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
21491
21492 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21493 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
21494 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
21495 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK
21496 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
21497 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
21498 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
21499
21500 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21501 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
21502 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
21503 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK
21504 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
21505 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
21506 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
21507
21508 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21509 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
21510 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
21511 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK
21512 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
21513 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
21514 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
21515
21516 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21517 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
21518 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
21519 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK
21520 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
21521 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
21522 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
21523
21524 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21525 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
21526 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
21527 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK
21528 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
21529 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
21530 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
21531
21532 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21533 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
21534 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
21535 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK
21536 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
21537 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
21538 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
21539
21540 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21541 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
21542 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
21543 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK
21544 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
21545 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
21546 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
21547
21548 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21549 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
21550 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
21551 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK
21552 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
21553 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
21554 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
21555
21556 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21557 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
21558 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
21559 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK
21560 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
21561 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
21562 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
21563
21564 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21565 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
21566 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
21567 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK
21568 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
21569 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
21570 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
21571
21572 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21573 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
21574 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
21575 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK
21576 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
21577 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
21578 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
21579
21580 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21581 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
21582 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
21583 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK
21584 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
21585 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
21586 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
21587
21588 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21589 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
21590 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
21591 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK
21592 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
21593 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
21594 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
21595
21596 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21597 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
21598 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
21599 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK
21600 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
21601 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
21602 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
21603
21604 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21605 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21606 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
21607 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
21608 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21609 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
21610 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
21611
21612 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21613 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21614 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
21615 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
21616 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21617 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
21618 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
21619
21620 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21621 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21622 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
21623 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
21624 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21625 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
21626 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
21627
21628 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21629 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21630 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
21631 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
21632 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21633 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
21634 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
21635
21636 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21637 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21638 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
21639 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
21640 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21641 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
21642 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
21643
21644 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21645 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21646 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
21647 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
21648 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21649 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
21650 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
21651
21652 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21653 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21654 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
21655 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
21656 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21657 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
21658 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
21659
21660 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21661 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21662 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
21663 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
21664 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21665 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
21666 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
21667
21668 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21669 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21670 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
21671 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
21672 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21673 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
21674 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
21675
21676 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21677 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21678 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
21679 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
21680 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21681 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
21682 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
21683
21684 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21685 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21686 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
21687 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
21688 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21689 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
21690 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
21691
21692 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21693 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21694 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
21695 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
21696 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21697 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
21698 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
21699
21700 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21701 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21702 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
21703 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
21704 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21705 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
21706 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
21707
21708 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21709 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21710 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
21711 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
21712 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21713 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
21714 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
21715
21716 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21717 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21718 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
21719 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
21720 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21721 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
21722 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
21723
21724 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21725 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21726 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
21727 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
21728 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21729 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
21730 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
21731
21732 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21733 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21734 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
21735 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
21736 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21737 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
21738 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
21739
21740 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21741 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21742 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
21743 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
21744 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21745 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
21746 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
21747
21748 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21749 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21750 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
21751 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
21752 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21753 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
21754 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
21755
21756 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21757 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21758 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
21759 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
21760 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21761 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
21762 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
21763
21764 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21765 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21766 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
21767 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
21768 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21769 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
21770 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
21771
21772 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21773 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21774 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
21775 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
21776 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21777 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
21778 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
21779
21780 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21781 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21782 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
21783 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
21784 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21785 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
21786 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
21787
21788 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21789 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21790 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
21791 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
21792 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21793 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
21794 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
21795
21796 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21797 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21798 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
21799 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
21800 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21801 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
21802 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
21803
21804 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21805 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21806 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
21807 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
21808 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21809 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
21810 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
21811
21812 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21813 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21814 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
21815 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
21816 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21817 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
21818 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
21819
21820 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21821 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21822 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
21823 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
21824 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21825 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
21826 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
21827
21828 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21829 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21830 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
21831 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
21832 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21833 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
21834 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
21835
21836 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21837 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21838 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
21839 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
21840 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21841 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
21842 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
21843
21844 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21845 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21846 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
21847 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
21848 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21849 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
21850 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
21851
21852 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21853 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21854 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
21855 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
21856 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21857 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
21858 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
21859
21860 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21861 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21862 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
21863 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
21864 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21865 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
21866 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
21867
21868 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21869 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21870 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
21871 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
21872 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21873 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
21874 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
21875
21876 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21877 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21878 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
21879 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
21880 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21881 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
21882 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
21883
21884 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21885 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21886 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
21887 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
21888 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21889 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
21890 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
21891
21892 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21893 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21894 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
21895 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
21896 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21897 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
21898 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
21899
21900 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21901 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21902 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
21903 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
21904 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21905 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
21906 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
21907
21908 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21909 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21910 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
21911 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
21912 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21913 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
21914 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
21915
21916 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21917 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21918 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
21919 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
21920 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21921 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
21922 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
21923
21924 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21925 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21926 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
21927 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
21928 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21929 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
21930 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
21931
21932 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21933 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21934 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
21935 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
21936 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21937 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
21938 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
21939
21940 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21941 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21942 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
21943 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
21944 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21945 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
21946 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
21947
21948 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21949 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21950 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
21951 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
21952 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21953 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
21954 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
21955
21956 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21957 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21958 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
21959 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
21960 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21961 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
21962 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
21963
21964 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21965 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21966 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
21967 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
21968 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21969 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
21970 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
21971
21972 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21973 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21974 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
21975 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
21976 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21977 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
21978 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
21979
21980 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21981 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21982 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
21983 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
21984 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21985 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
21986 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
21987
21988 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21989 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21990 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
21991 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
21992 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21993 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
21994 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
21995
21996 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21997 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
21998 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
21999 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
22000 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
22001 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
22002 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
22003
22004 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22005 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22006 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
22007 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
22008 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22009 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
22010 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
22011
22012 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22013 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22014 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
22015 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
22016 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22017 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
22018 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
22019
22020 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22021 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22022 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
22023 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
22024 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22025 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
22026 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
22027
22028 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22029 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22030 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
22031 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
22032 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22033 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
22034 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
22035
22036 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22037 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22038 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
22039 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
22040 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22041 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
22042 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
22043
22044 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22045 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22046 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
22047 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
22048 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22049 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
22050 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
22051
22052 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22053 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22054 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
22055 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
22056 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22057 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
22058 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
22059
22060 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22061 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22062 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
22063 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
22064 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22065 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
22066 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
22067
22068 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22069 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22070 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
22071 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
22072 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22073 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
22074 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
22075
22076 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22077 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22078 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
22079 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
22080 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22081 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
22082 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
22083
22084 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22085 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22086 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
22087 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
22088 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22089 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
22090 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
22091
22092 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22093 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22094 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
22095 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
22096 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22097 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
22098 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
22099
22100 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22101 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22102 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
22103 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
22104 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22105 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
22106 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
22107
22108 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22109 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22110 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
22111 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
22112 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22113 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
22114 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
22115
22116 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22117 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22118 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
22119 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
22120 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22121 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
22122 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
22123
22124 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22125 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22126 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
22127 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
22128 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22129 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
22130 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
22131
22132 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22133 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22134 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
22135 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
22136 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22137 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
22138 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
22139
22140 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22141 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22142 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
22143 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
22144 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22145 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
22146 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
22147
22148 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22149 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22150 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
22151 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
22152 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22153 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
22154 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
22155
22156 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22157 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22158 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
22159 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
22160 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22161 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
22162 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
22163
22164 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22165 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22166 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
22167 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
22168 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22169 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
22170 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
22171
22172 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22173 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22174 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
22175 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
22176 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22177 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
22178 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
22179
22180 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22181 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22182 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
22183 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
22184 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22185 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
22186 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
22187
22188 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22189 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22190 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
22191 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
22192 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22193 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
22194 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
22195
22196 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22197 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22198 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
22199 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
22200 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22201 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
22202 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
22203
22204 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22205 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22206 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
22207 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
22208 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22209 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
22210 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
22211
22212 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22213 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22214 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
22215 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
22216 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22217 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
22218 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
22219
22220 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22221 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22222 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
22223 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
22224 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22225 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
22226 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
22227
22228 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22229 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22230 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
22231 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
22232 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22233 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
22234 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
22235
22236 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22237 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22238 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
22239 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
22240 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22241 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
22242 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
22243
22244 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22245 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22246 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
22247 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
22248 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22249 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
22250 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
22251
22252 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22253 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22254 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
22255 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
22256 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22257 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
22258 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
22259
22260 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22261 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22262 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
22263 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
22264 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22265 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
22266 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
22267
22268 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22269 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22270 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
22271 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
22272 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22273 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
22274 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
22275
22276 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22277 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22278 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
22279 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
22280 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22281 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
22282 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
22283
22284 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22285 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
22286 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
22287 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
22288 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
22289 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
22290 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
22291
22292 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22293 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
22294 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
22295 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
22296 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
22297 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
22298 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
22299
22300 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22301 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
22302 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
22303 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
22304 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
22305 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
22306 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
22307
22308 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22309 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
22310 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
22311 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
22312 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
22313 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
22314 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
22315
22316 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22317 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
22318 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
22319 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
22320 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
22321 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
22322 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
22323
22324 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22325 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
22326 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
22327 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
22328 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
22329 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
22330 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
22331
22332 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22333 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
22334 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
22335 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
22336 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
22337 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
22338 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
22339
22340 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22341 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
22342 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
22343 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
22344 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
22345 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
22346 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
22347
22348 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22349 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
22350 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
22351 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
22352 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
22353 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
22354 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
22355
22356 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22357 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
22358 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
22359 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
22360 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
22361 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
22362 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
22363
22364 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22365 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
22366 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
22367 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
22368 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
22369 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
22370 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
22371
22372 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22373 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
22374 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
22375 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
22376 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
22377 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
22378 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
22379
22380 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22381 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
22382 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
22383 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
22384 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
22385 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
22386 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
22387
22388 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22389 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
22390 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
22391 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
22392 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
22393 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
22394 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
22395
22396 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22397 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
22398 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
22399 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
22400 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
22401 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
22402 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
22403
22404 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22405 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
22406 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
22407 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
22408 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
22409 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
22410 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
22411
22412 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22413 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
22414 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
22415 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
22416 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
22417 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
22418 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
22419
22420 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22421 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
22422 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
22423 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
22424 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
22425 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
22426 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
22427
22428 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22429 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
22430 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
22431 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
22432 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
22433 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
22434 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
22435
22436 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22437 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
22438 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
22439 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK
22440 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
22441 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
22442 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
22443
22444 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22445 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
22446 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
22447 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK
22448 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
22449 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
22450 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
22451
22452 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22453 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
22454 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
22455 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK
22456 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
22457 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
22458 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
22459
22460 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22461 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
22462 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
22463 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK
22464 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
22465 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
22466 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
22467
22468 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22469 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
22470 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
22471 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK
22472 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
22473 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
22474 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
22475
22476 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22477 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
22478 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
22479 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK
22480 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
22481 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
22482 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
22483
22484 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22485 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
22486 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
22487 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK
22488 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
22489 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
22490 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
22491
22492 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22493 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
22494 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
22495 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK
22496 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
22497 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
22498 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
22499
22500 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22501 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
22502 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
22503 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK
22504 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
22505 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
22506 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
22507
22508 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22509 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
22510 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
22511 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK
22512 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
22513 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
22514 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
22515
22516 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22517 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
22518 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
22519 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK
22520 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
22521 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
22522 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
22523
22524 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22525 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
22526 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
22527 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK
22528 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
22529 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
22530 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
22531
22532 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22533 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
22534 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
22535 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK
22536 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
22537 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
22538 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
22539
22540 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22541 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
22542 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
22543 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK
22544 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
22545 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
22546 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
22547
22548 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22549 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
22550 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
22551 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK
22552 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
22553 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
22554 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
22555
22556 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22557 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
22558 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
22559 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK
22560 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
22561 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
22562 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
22563
22564 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22565 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
22566 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
22567 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK
22568 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
22569 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
22570 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
22571
22572 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22573 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
22574 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
22575 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK
22576 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
22577 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
22578 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
22579
22580 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22581 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
22582 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
22583 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK
22584 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
22585 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
22586 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
22587
22588 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22589 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
22590 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
22591 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK
22592 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
22593 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
22594 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
22595
22596 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22597 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
22598 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
22599 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK
22600 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
22601 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
22602 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
22603
22604 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22605 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
22606 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
22607 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK
22608 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
22609 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
22610 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
22611
22612 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22613 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
22614 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
22615 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK
22616 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
22617 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
22618 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
22619
22620 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22621 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
22622 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
22623 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK
22624 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
22625 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
22626 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
22627
22628 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22629 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
22630 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
22631 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK
22632 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
22633 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
22634 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
22635
22636 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22637 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
22638 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
22639 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK
22640 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
22641 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
22642 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
22643
22644 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22645 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
22646 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
22647 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK
22648 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
22649 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
22650 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
22651
22652 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22653 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
22654 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
22655 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK
22656 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
22657 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
22658 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
22659
22660 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22661 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
22662 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
22663 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK
22664 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
22665 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
22666 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
22667
22668 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22669 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
22670 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
22671 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK
22672 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
22673 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
22674 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
22675
22676 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22677 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
22678 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
22679 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK
22680 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
22681 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
22682 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
22683
22684 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22685 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
22686 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
22687 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK
22688 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
22689 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
22690 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
22691
22692 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22693 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
22694 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
22695 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK
22696 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
22697 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
22698 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
22699
22700 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22701 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
22702 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
22703 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK
22704 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
22705 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
22706 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
22707
22708 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22709 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
22710 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
22711 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK
22712 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
22713 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
22714 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
22715
22716 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22717 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
22718 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
22719 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK
22720 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
22721 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
22722 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
22723
22724 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22725 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
22726 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
22727 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK
22728 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
22729 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
22730 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
22731
22732 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22733 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
22734 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
22735 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK
22736 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
22737 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
22738 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
22739
22740 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22741 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
22742 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
22743 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK
22744 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
22745 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
22746 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
22747
22748 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22749 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
22750 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
22751 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK
22752 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
22753 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
22754 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
22755
22756 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22757 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
22758 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
22759 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK
22760 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
22761 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
22762 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
22763
22764 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22765 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
22766 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
22767 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK
22768 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
22769 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
22770 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
22771
22772 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22773 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
22774 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
22775 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK
22776 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
22777 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
22778 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
22779
22780 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22781 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
22782 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
22783 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK
22784 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
22785 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
22786 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
22787
22788 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22789 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
22790 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
22791 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK
22792 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
22793 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
22794 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
22795
22796 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22797 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
22798 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
22799 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK
22800 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
22801 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
22802 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
22803
22804 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22805 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
22806 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
22807 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK
22808 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
22809 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
22810 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
22811
22812 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22813 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
22814 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
22815 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK
22816 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
22817 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
22818 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
22819
22820 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22821 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
22822 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
22823 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK
22824 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
22825 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
22826 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
22827
22828 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22829 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
22830 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
22831 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK
22832 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
22833 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
22834 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
22835
22836 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22837 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
22838 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
22839 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK
22840 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
22841 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
22842 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
22843
22844 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22845 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
22846 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
22847 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK
22848 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
22849 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
22850 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
22851
22852 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22853 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22854 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
22855 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
22856 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22857 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
22858 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
22859
22860 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22861 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22862 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
22863 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
22864 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22865 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
22866 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
22867
22868 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22869 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22870 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
22871 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
22872 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22873 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
22874 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
22875
22876 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22877 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22878 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
22879 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
22880 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22881 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
22882 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
22883
22884 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22885 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22886 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
22887 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
22888 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22889 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
22890 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
22891
22892 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22893 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22894 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
22895 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
22896 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22897 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
22898 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
22899
22900 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22901 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22902 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
22903 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
22904 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22905 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
22906 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
22907
22908 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22909 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22910 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
22911 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
22912 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22913 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
22914 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
22915
22916 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22917 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22918 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
22919 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
22920 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22921 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
22922 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
22923
22924 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22925 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22926 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
22927 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
22928 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22929 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
22930 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
22931
22932 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22933 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22934 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
22935 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
22936 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22937 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
22938 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
22939
22940 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22941 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22942 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
22943 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
22944 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22945 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
22946 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
22947
22948 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22949 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22950 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
22951 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
22952 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22953 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
22954 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
22955
22956 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22957 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22958 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
22959 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
22960 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22961 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
22962 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
22963
22964 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22965 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22966 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
22967 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
22968 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22969 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
22970 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
22971
22972 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22973 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22974 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
22975 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
22976 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22977 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
22978 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
22979
22980 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22981 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22982 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
22983 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
22984 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22985 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
22986 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
22987
22988 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22989 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22990 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
22991 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
22992 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22993 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
22994 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
22995
22996 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
22997 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
22998 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
22999 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
23000 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
23001 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
23002 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
23003
23004 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23005 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23006 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
23007 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
23008 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23009 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
23010 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
23011
23012 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23013 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23014 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
23015 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
23016 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23017 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
23018 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
23019
23020 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23021 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23022 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
23023 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
23024 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23025 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
23026 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
23027
23028 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23029 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23030 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
23031 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
23032 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23033 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
23034 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
23035
23036 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23037 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23038 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
23039 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
23040 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23041 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
23042 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
23043
23044 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23045 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23046 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
23047 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
23048 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23049 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
23050 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
23051
23052 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23053 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23054 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
23055 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
23056 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23057 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
23058 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
23059
23060 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23061 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23062 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
23063 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
23064 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23065 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
23066 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
23067
23068 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23069 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23070 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
23071 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
23072 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23073 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
23074 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
23075
23076 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23077 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23078 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
23079 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
23080 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23081 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
23082 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
23083
23084 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23085 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23086 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
23087 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
23088 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23089 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
23090 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
23091
23092 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23093 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23094 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
23095 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
23096 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23097 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
23098 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
23099
23100 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23101 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23102 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
23103 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
23104 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23105 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
23106 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
23107
23108 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23109 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23110 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
23111 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
23112 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23113 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
23114 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
23115
23116 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23117 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23118 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
23119 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
23120 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23121 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
23122 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
23123
23124 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23125 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23126 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
23127 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
23128 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23129 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
23130 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
23131
23132 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23133 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23134 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
23135 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
23136 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23137 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
23138 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
23139
23140 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23141 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23142 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
23143 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
23144 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23145 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
23146 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
23147
23148 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23149 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23150 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
23151 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
23152 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23153 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
23154 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
23155
23156 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23157 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23158 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
23159 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
23160 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23161 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
23162 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
23163
23164 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23165 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23166 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
23167 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
23168 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23169 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
23170 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
23171
23172 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23173 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23174 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
23175 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
23176 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23177 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
23178 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
23179
23180 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23181 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23182 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
23183 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
23184 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23185 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
23186 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
23187
23188 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23189 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23190 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
23191 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
23192 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23193 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
23194 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
23195
23196 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23197 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23198 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
23199 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
23200 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23201 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
23202 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
23203
23204 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23205 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23206 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
23207 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
23208 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23209 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
23210 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
23211
23212 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23213 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23214 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
23215 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
23216 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23217 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
23218 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
23219
23220 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23221 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23222 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
23223 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
23224 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23225 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
23226 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
23227
23228 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23229 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23230 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
23231 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
23232 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23233 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
23234 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
23235
23236 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23237 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23238 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
23239 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
23240 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23241 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
23242 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
23243
23244 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23245 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23246 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
23247 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
23248 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23249 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
23250 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
23251
23252 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23253 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23254 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
23255 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
23256 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23257 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
23258 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
23259
23260 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23261 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23262 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
23263 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
23264 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23265 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
23266 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
23267
23268 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23269 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23270 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
23271 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK
23272 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23273 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
23274 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
23275
23276 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23277 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23278 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
23279 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK
23280 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23281 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
23282 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
23283
23284 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23285 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
23286 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
23287 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK
23288 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
23289 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
23290 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
23291
23292 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23293 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
23294 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
23295 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK
23296 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
23297 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
23298 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
23299
23300 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23301 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
23302 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
23303 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK
23304 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
23305 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
23306 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
23307
23308 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23309 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
23310 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
23311 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK
23312 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
23313 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
23314 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
23315
23316 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23317 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
23318 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
23319 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK
23320 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
23321 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
23322 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
23323
23324 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23325 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
23326 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
23327 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK
23328 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
23329 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
23330 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
23331
23332 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23333 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
23334 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
23335 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK
23336 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
23337 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
23338 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
23339
23340 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23341 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
23342 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
23343 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK
23344 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
23345 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
23346 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
23347
23348 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23349 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
23350 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
23351 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK
23352 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
23353 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
23354 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
23355
23356 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23357 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
23358 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
23359 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK
23360 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
23361 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
23362 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
23363
23364 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23365 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
23366 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
23367 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK
23368 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
23369 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
23370 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
23371
23372 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23373 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
23374 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
23375 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK
23376 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
23377 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
23378 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
23379
23380 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23381 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
23382 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
23383 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK
23384 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
23385 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
23386 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
23387
23388 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23389 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
23390 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
23391 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK
23392 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
23393 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
23394 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
23395
23396 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23397 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
23398 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
23399 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK
23400 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
23401 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
23402 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
23403
23404 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23405 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
23406 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
23407 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK
23408 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
23409 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
23410 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
23411
23412 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23413 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
23414 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
23415 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK
23416 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
23417 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
23418 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
23419
23420 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23421 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
23422 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
23423 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK
23424 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
23425 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
23426 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
23427
23428 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23429 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
23430 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
23431 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK
23432 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
23433 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
23434 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
23435
23436 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23437 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
23438 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
23439 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK
23440 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
23441 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
23442 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
23443
23444 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23445 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
23446 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
23447 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK
23448 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
23449 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
23450 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
23451
23452 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23453 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
23454 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
23455 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK
23456 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
23457 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
23458 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
23459
23460 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23461 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
23462 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
23463 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK
23464 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
23465 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
23466 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
23467
23468 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23469 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
23470 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
23471 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK
23472 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
23473 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
23474 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
23475
23476 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23477 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
23478 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
23479 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
23480 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
23481 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
23482 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
23483
23484 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23485 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
23486 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
23487 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
23488 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
23489 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
23490 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
23491
23492 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23493 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
23494 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
23495 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
23496 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
23497 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
23498 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
23499
23500 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23501 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
23502 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
23503 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
23504 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
23505 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
23506 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
23507
23508 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23509 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
23510 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
23511 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
23512 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
23513 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
23514 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
23515
23516 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23517 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
23518 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
23519 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
23520 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
23521 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
23522 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
23523
23524 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23525 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
23526 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
23527 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
23528 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
23529 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
23530 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
23531
23532 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23533 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
23534 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
23535 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
23536 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
23537 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
23538 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
23539
23540 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23541 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
23542 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
23543 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
23544 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
23545 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
23546 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
23547
23548 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23549 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
23550 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
23551 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
23552 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
23553 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
23554 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
23555
23556 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23557 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
23558 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
23559 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
23560 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
23561 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
23562 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
23563
23564 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23565 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
23566 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
23567 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
23568 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
23569 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
23570 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
23571
23572 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23573 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23574 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
23575 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
23576 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23577 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
23578 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
23579
23580 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23581 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23582 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
23583 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
23584 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23585 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
23586 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
23587
23588 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23589 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23590 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
23591 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
23592 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23593 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
23594 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
23595
23596 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23597 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23598 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
23599 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
23600 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23601 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
23602 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
23603
23604 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23605 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23606 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
23607 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
23608 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23609 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
23610 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
23611
23612 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23613 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23614 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
23615 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
23616 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23617 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
23618 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
23619
23620 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23621 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23622 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
23623 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
23624 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23625 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
23626 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
23627
23628 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23629 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23630 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
23631 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
23632 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23633 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
23634 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
23635
23636 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23637 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23638 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
23639 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
23640 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23641 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
23642 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
23643
23644 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23645 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23646 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
23647 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
23648 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23649 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
23650 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
23651
23652 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23653 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23654 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
23655 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
23656 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23657 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
23658 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
23659
23660 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23661 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23662 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
23663 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
23664 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23665 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
23666 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
23667
23668 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23669 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23670 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
23671 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
23672 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23673 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
23674 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
23675
23676 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23677 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23678 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
23679 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
23680 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23681 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
23682 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
23683
23684 /*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
23685                 ts to I2C 0 inputs.*/
23686 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
23687 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
23688 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
23689 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
23690 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
23691 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
23692
23693 /*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
23694                 .*/
23695 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
23696 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
23697 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
23698 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
23699 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
23700 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
23701
23702 /*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
23703                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
23704 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
23705 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
23706 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
23707 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
23708 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
23709 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
23710
23711 /*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
23712                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
23713 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
23714 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
23715 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
23716 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
23717 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
23718 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
23719 #undef CRL_APB_RST_LPD_IOU0_OFFSET
23720 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
23721 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23722 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23723 #undef CRL_APB_RST_LPD_TOP_OFFSET
23724 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
23725 #undef CRF_APB_RST_FPD_TOP_OFFSET
23726 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
23727 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23728 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23729 #undef IOU_SLCR_CTRL_REG_SD_OFFSET
23730 #define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
23731 #undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
23732 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
23733 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
23734 #define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
23735 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23736 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23737 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23738 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23739 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23740 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23741 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23742 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23743 #undef CRL_APB_RST_LPD_IOU2_OFFSET
23744 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
23745 #undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
23746 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
23747 #undef UART0_BAUD_RATE_GEN_REG0_OFFSET
23748 #define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
23749 #undef UART0_CONTROL_REG0_OFFSET
23750 #define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
23751 #undef UART0_MODE_REG0_OFFSET
23752 #define UART0_MODE_REG0_OFFSET                                                     0XFF000004
23753 #undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
23754 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
23755 #undef UART1_BAUD_RATE_GEN_REG0_OFFSET
23756 #define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
23757 #undef UART1_CONTROL_REG0_OFFSET
23758 #define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
23759 #undef UART1_MODE_REG0_OFFSET
23760 #define UART1_MODE_REG0_OFFSET                                                     0XFF010004
23761 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
23762 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
23763 #undef CSU_TAMPER_STATUS_OFFSET
23764 #define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
23765 #undef APU_ACE_CTRL_OFFSET
23766 #define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
23767 #undef RTC_CONTROL_OFFSET
23768 #define RTC_CONTROL_OFFSET                                                         0XFFA60040
23769
23770 /*GEM 3 reset*/
23771 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
23772 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
23773 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
23774 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
23775 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
23776 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
23777
23778 /*Block level reset*/
23779 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
23780 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
23781 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
23782 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
23783 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
23784 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
23785
23786 /*USB 0 reset for control registers*/
23787 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
23788 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
23789 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
23790 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
23791 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
23792 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
23793
23794 /*USB 0 sleep circuit reset*/
23795 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
23796 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
23797 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
23798 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
23799 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
23800 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
23801
23802 /*USB 0 reset*/
23803 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
23804 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
23805 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
23806 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
23807 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
23808 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
23809
23810 /*PCIE config reset*/
23811 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
23812 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
23813 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
23814 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
23815 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
23816 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
23817
23818 /*PCIE control block level reset*/
23819 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
23820 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
23821 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
23822 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
23823 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
23824 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
23825
23826 /*PCIE bridge block level reset (AXI interface)*/
23827 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
23828 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
23829 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
23830 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
23831 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
23832 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
23833
23834 /*Display Port block level reset (includes DPDMA)*/
23835 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
23836 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
23837 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
23838 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
23839 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
23840 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
23841
23842 /*FPD WDT reset*/
23843 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL
23844 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
23845 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK
23846 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                                      0x000F9FFE
23847 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                                       15
23848 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                                        0x00008000U
23849
23850 /*GDMA block level reset*/
23851 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL
23852 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
23853 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK
23854 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                                      0x000F9FFE
23855 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                                       6
23856 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                                        0x00000040U
23857
23858 /*Pixel Processor (submodule of GPU) block level reset*/
23859 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL
23860 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
23861 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK
23862 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL                                   0x000F9FFE
23863 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                                    4
23864 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                                     0x00000010U
23865
23866 /*Pixel Processor (submodule of GPU) block level reset*/
23867 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL
23868 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
23869 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK
23870 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL                                   0x000F9FFE
23871 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                                    5
23872 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                                     0x00000020U
23873
23874 /*GPU block level reset*/
23875 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL
23876 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
23877 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK
23878 #define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                                       0x000F9FFE
23879 #define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                                        3
23880 #define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                                         0x00000008U
23881
23882 /*GT block level reset*/
23883 #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL
23884 #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
23885 #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK
23886 #define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                                        0x000F9FFE
23887 #define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                                         2
23888 #define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                                          0x00000004U
23889
23890 /*Sata block level reset*/
23891 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
23892 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
23893 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
23894 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
23895 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
23896 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
23897
23898 /*Block level reset*/
23899 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
23900 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
23901 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
23902 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
23903 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
23904 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
23905
23906 /*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
23907 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
23908 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
23909 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
23910 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
23911 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
23912 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
23913
23914 /*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
23915                 t 11 - Reserved*/
23916 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
23917 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
23918 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
23919 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
23920 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
23921 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
23922
23923 /*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
23924 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
23925 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
23926 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
23927 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
23928 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
23929 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
23930
23931 /*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
23932 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
23933 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
23934 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
23935 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
23936 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
23937 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
23938
23939 /*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
23940 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
23941 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
23942 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
23943 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
23944 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
23945 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
23946
23947 /*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/
23948 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL
23949 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
23950 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK
23951 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL                                 0x32403240
23952 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT                                  23
23953 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK                                   0x7F800000U
23954
23955 /*Block level reset*/
23956 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
23957 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
23958 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
23959 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
23960 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
23961 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
23962
23963 /*Block level reset*/
23964 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL
23965 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
23966 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK
23967 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
23968 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
23969 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
23970
23971 /*Block level reset*/
23972 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
23973 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
23974 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
23975 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
23976 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
23977 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
23978
23979 /*Block level reset*/
23980 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL
23981 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
23982 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK
23983 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                                     0x0017FFFF
23984 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                                      15
23985 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                                       0x00008000U
23986
23987 /*Block level reset*/
23988 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
23989 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
23990 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
23991 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
23992 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
23993 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
23994
23995 /*Block level reset*/
23996 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
23997 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
23998 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
23999 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
24000 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
24001 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
24002
24003 /*Block level reset*/
24004 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
24005 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
24006 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
24007 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
24008 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
24009 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
24010
24011 /*Block level reset*/
24012 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
24013 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
24014 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
24015 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
24016 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
24017 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
24018
24019 /*Block level reset*/
24020 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
24021 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
24022 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
24023 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
24024 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
24025 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
24026
24027 /*Block level reset*/
24028 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
24029 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
24030 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
24031 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
24032 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
24033 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
24034
24035 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24036 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24037 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24038 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24039 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
24040 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
24041 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
24042
24043 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24044 #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
24045 #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
24046 #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
24047 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
24048 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
24049 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
24050
24051 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24052                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24053 #undef UART0_CONTROL_REG0_STPBRK_DEFVAL
24054 #undef UART0_CONTROL_REG0_STPBRK_SHIFT
24055 #undef UART0_CONTROL_REG0_STPBRK_MASK
24056 #define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
24057 #define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
24058 #define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
24059
24060 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24061                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24062 #undef UART0_CONTROL_REG0_STTBRK_DEFVAL
24063 #undef UART0_CONTROL_REG0_STTBRK_SHIFT
24064 #undef UART0_CONTROL_REG0_STTBRK_MASK
24065 #define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
24066 #define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
24067 #define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
24068
24069 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24070                 pleted.*/
24071 #undef UART0_CONTROL_REG0_RSTTO_DEFVAL
24072 #undef UART0_CONTROL_REG0_RSTTO_SHIFT
24073 #undef UART0_CONTROL_REG0_RSTTO_MASK
24074 #define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
24075 #define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
24076 #define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
24077
24078 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24079 #undef UART0_CONTROL_REG0_TXDIS_DEFVAL
24080 #undef UART0_CONTROL_REG0_TXDIS_SHIFT
24081 #undef UART0_CONTROL_REG0_TXDIS_MASK
24082 #define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
24083 #define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
24084 #define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
24085
24086 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24087 #undef UART0_CONTROL_REG0_TXEN_DEFVAL
24088 #undef UART0_CONTROL_REG0_TXEN_SHIFT
24089 #undef UART0_CONTROL_REG0_TXEN_MASK
24090 #define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
24091 #define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
24092 #define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
24093
24094 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24095 #undef UART0_CONTROL_REG0_RXDIS_DEFVAL
24096 #undef UART0_CONTROL_REG0_RXDIS_SHIFT
24097 #undef UART0_CONTROL_REG0_RXDIS_MASK
24098 #define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
24099 #define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
24100 #define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
24101
24102 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24103 #undef UART0_CONTROL_REG0_RXEN_DEFVAL
24104 #undef UART0_CONTROL_REG0_RXEN_SHIFT
24105 #undef UART0_CONTROL_REG0_RXEN_MASK
24106 #define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
24107 #define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
24108 #define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
24109
24110 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24111                  bit is self clearing once the reset has completed.*/
24112 #undef UART0_CONTROL_REG0_TXRES_DEFVAL
24113 #undef UART0_CONTROL_REG0_TXRES_SHIFT
24114 #undef UART0_CONTROL_REG0_TXRES_MASK
24115 #define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
24116 #define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
24117 #define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
24118
24119 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
24120                 is self clearing once the reset has completed.*/
24121 #undef UART0_CONTROL_REG0_RXRES_DEFVAL
24122 #undef UART0_CONTROL_REG0_RXRES_SHIFT
24123 #undef UART0_CONTROL_REG0_RXRES_MASK
24124 #define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
24125 #define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
24126 #define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
24127
24128 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
24129 #undef UART0_MODE_REG0_CHMODE_DEFVAL
24130 #undef UART0_MODE_REG0_CHMODE_SHIFT
24131 #undef UART0_MODE_REG0_CHMODE_MASK
24132 #define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
24133 #define UART0_MODE_REG0_CHMODE_SHIFT                                               8
24134 #define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
24135
24136 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
24137                 stop bits 10: 2 stop bits 11: reserved*/
24138 #undef UART0_MODE_REG0_NBSTOP_DEFVAL
24139 #undef UART0_MODE_REG0_NBSTOP_SHIFT
24140 #undef UART0_MODE_REG0_NBSTOP_MASK
24141 #define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
24142 #define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
24143 #define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
24144
24145 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
24146                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
24147 #undef UART0_MODE_REG0_PAR_DEFVAL
24148 #undef UART0_MODE_REG0_PAR_SHIFT
24149 #undef UART0_MODE_REG0_PAR_MASK
24150 #define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
24151 #define UART0_MODE_REG0_PAR_SHIFT                                                  3
24152 #define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
24153
24154 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
24155 #undef UART0_MODE_REG0_CHRL_DEFVAL
24156 #undef UART0_MODE_REG0_CHRL_SHIFT
24157 #undef UART0_MODE_REG0_CHRL_MASK
24158 #define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
24159 #define UART0_MODE_REG0_CHRL_SHIFT                                                 1
24160 #define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
24161
24162 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
24163                 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
24164 #undef UART0_MODE_REG0_CLKS_DEFVAL
24165 #undef UART0_MODE_REG0_CLKS_SHIFT
24166 #undef UART0_MODE_REG0_CLKS_MASK
24167 #define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
24168 #define UART0_MODE_REG0_CLKS_SHIFT                                                 0
24169 #define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
24170
24171 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24172 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24173 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24174 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24175 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
24176 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
24177 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
24178
24179 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24180 #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
24181 #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
24182 #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
24183 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
24184 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
24185 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
24186
24187 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24188                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24189 #undef UART1_CONTROL_REG0_STPBRK_DEFVAL
24190 #undef UART1_CONTROL_REG0_STPBRK_SHIFT
24191 #undef UART1_CONTROL_REG0_STPBRK_MASK
24192 #define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
24193 #define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
24194 #define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
24195
24196 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24197                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24198 #undef UART1_CONTROL_REG0_STTBRK_DEFVAL
24199 #undef UART1_CONTROL_REG0_STTBRK_SHIFT
24200 #undef UART1_CONTROL_REG0_STTBRK_MASK
24201 #define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
24202 #define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
24203 #define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
24204
24205 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24206                 pleted.*/
24207 #undef UART1_CONTROL_REG0_RSTTO_DEFVAL
24208 #undef UART1_CONTROL_REG0_RSTTO_SHIFT
24209 #undef UART1_CONTROL_REG0_RSTTO_MASK
24210 #define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
24211 #define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
24212 #define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
24213
24214 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24215 #undef UART1_CONTROL_REG0_TXDIS_DEFVAL
24216 #undef UART1_CONTROL_REG0_TXDIS_SHIFT
24217 #undef UART1_CONTROL_REG0_TXDIS_MASK
24218 #define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
24219 #define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
24220 #define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
24221
24222 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24223 #undef UART1_CONTROL_REG0_TXEN_DEFVAL
24224 #undef UART1_CONTROL_REG0_TXEN_SHIFT
24225 #undef UART1_CONTROL_REG0_TXEN_MASK
24226 #define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
24227 #define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
24228 #define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
24229
24230 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24231 #undef UART1_CONTROL_REG0_RXDIS_DEFVAL
24232 #undef UART1_CONTROL_REG0_RXDIS_SHIFT
24233 #undef UART1_CONTROL_REG0_RXDIS_MASK
24234 #define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
24235 #define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
24236 #define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
24237
24238 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24239 #undef UART1_CONTROL_REG0_RXEN_DEFVAL
24240 #undef UART1_CONTROL_REG0_RXEN_SHIFT
24241 #undef UART1_CONTROL_REG0_RXEN_MASK
24242 #define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
24243 #define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
24244 #define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
24245
24246 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24247                  bit is self clearing once the reset has completed.*/
24248 #undef UART1_CONTROL_REG0_TXRES_DEFVAL
24249 #undef UART1_CONTROL_REG0_TXRES_SHIFT
24250 #undef UART1_CONTROL_REG0_TXRES_MASK
24251 #define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
24252 #define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
24253 #define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
24254
24255 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
24256                 is self clearing once the reset has completed.*/
24257 #undef UART1_CONTROL_REG0_RXRES_DEFVAL
24258 #undef UART1_CONTROL_REG0_RXRES_SHIFT
24259 #undef UART1_CONTROL_REG0_RXRES_MASK
24260 #define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
24261 #define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
24262 #define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
24263
24264 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
24265 #undef UART1_MODE_REG0_CHMODE_DEFVAL
24266 #undef UART1_MODE_REG0_CHMODE_SHIFT
24267 #undef UART1_MODE_REG0_CHMODE_MASK
24268 #define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
24269 #define UART1_MODE_REG0_CHMODE_SHIFT                                               8
24270 #define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
24271
24272 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
24273                 stop bits 10: 2 stop bits 11: reserved*/
24274 #undef UART1_MODE_REG0_NBSTOP_DEFVAL
24275 #undef UART1_MODE_REG0_NBSTOP_SHIFT
24276 #undef UART1_MODE_REG0_NBSTOP_MASK
24277 #define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
24278 #define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
24279 #define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
24280
24281 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
24282                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
24283 #undef UART1_MODE_REG0_PAR_DEFVAL
24284 #undef UART1_MODE_REG0_PAR_SHIFT
24285 #undef UART1_MODE_REG0_PAR_MASK
24286 #define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
24287 #define UART1_MODE_REG0_PAR_SHIFT                                                  3
24288 #define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
24289
24290 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
24291 #undef UART1_MODE_REG0_CHRL_DEFVAL
24292 #undef UART1_MODE_REG0_CHRL_SHIFT
24293 #undef UART1_MODE_REG0_CHRL_MASK
24294 #define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
24295 #define UART1_MODE_REG0_CHRL_SHIFT                                                 1
24296 #define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
24297
24298 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
24299                 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
24300 #undef UART1_MODE_REG0_CLKS_DEFVAL
24301 #undef UART1_MODE_REG0_CLKS_SHIFT
24302 #undef UART1_MODE_REG0_CLKS_MASK
24303 #define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
24304 #define UART1_MODE_REG0_CLKS_SHIFT                                                 0
24305 #define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
24306
24307 /*TrustZone Classification for ADMA*/
24308 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
24309 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
24310 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
24311 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
24312 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
24313 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
24314
24315 /*CSU regsiter*/
24316 #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
24317 #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
24318 #undef CSU_TAMPER_STATUS_TAMPER_0_MASK
24319 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
24320 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
24321 #define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
24322
24323 /*External MIO*/
24324 #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
24325 #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
24326 #undef CSU_TAMPER_STATUS_TAMPER_1_MASK
24327 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
24328 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
24329 #define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
24330
24331 /*JTAG toggle detect*/
24332 #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
24333 #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
24334 #undef CSU_TAMPER_STATUS_TAMPER_2_MASK
24335 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
24336 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
24337 #define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
24338
24339 /*PL SEU error*/
24340 #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
24341 #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
24342 #undef CSU_TAMPER_STATUS_TAMPER_3_MASK
24343 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
24344 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
24345 #define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
24346
24347 /*AMS over temperature alarm for LPD*/
24348 #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
24349 #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
24350 #undef CSU_TAMPER_STATUS_TAMPER_4_MASK
24351 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
24352 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
24353 #define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
24354
24355 /*AMS over temperature alarm for APU*/
24356 #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
24357 #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
24358 #undef CSU_TAMPER_STATUS_TAMPER_5_MASK
24359 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
24360 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
24361 #define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
24362
24363 /*AMS voltage alarm for VCCPINT_FPD*/
24364 #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
24365 #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
24366 #undef CSU_TAMPER_STATUS_TAMPER_6_MASK
24367 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
24368 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
24369 #define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
24370
24371 /*AMS voltage alarm for VCCPINT_LPD*/
24372 #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
24373 #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
24374 #undef CSU_TAMPER_STATUS_TAMPER_7_MASK
24375 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
24376 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
24377 #define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
24378
24379 /*AMS voltage alarm for VCCPAUX*/
24380 #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
24381 #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
24382 #undef CSU_TAMPER_STATUS_TAMPER_8_MASK
24383 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
24384 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
24385 #define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
24386
24387 /*AMS voltage alarm for DDRPHY*/
24388 #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
24389 #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
24390 #undef CSU_TAMPER_STATUS_TAMPER_9_MASK
24391 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
24392 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
24393 #define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
24394
24395 /*AMS voltage alarm for PSIO bank 0/1/2*/
24396 #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
24397 #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
24398 #undef CSU_TAMPER_STATUS_TAMPER_10_MASK
24399 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
24400 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
24401 #define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
24402
24403 /*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
24404 #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
24405 #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
24406 #undef CSU_TAMPER_STATUS_TAMPER_11_MASK
24407 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
24408 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
24409 #define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
24410
24411 /*AMS voltaage alarm for GT*/
24412 #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
24413 #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
24414 #undef CSU_TAMPER_STATUS_TAMPER_12_MASK
24415 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
24416 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
24417 #define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
24418
24419 /*Set ACE outgoing AWQOS value*/
24420 #undef APU_ACE_CTRL_AWQOS_DEFVAL
24421 #undef APU_ACE_CTRL_AWQOS_SHIFT
24422 #undef APU_ACE_CTRL_AWQOS_MASK
24423 #define APU_ACE_CTRL_AWQOS_DEFVAL                                                  0x000F000F
24424 #define APU_ACE_CTRL_AWQOS_SHIFT                                                   16
24425 #define APU_ACE_CTRL_AWQOS_MASK                                                    0x000F0000U
24426
24427 /*Set ACE outgoing ARQOS value*/
24428 #undef APU_ACE_CTRL_ARQOS_DEFVAL
24429 #undef APU_ACE_CTRL_ARQOS_SHIFT
24430 #undef APU_ACE_CTRL_ARQOS_MASK
24431 #define APU_ACE_CTRL_ARQOS_DEFVAL                                                  0x000F000F
24432 #define APU_ACE_CTRL_ARQOS_SHIFT                                                   0
24433 #define APU_ACE_CTRL_ARQOS_MASK                                                    0x0000000FU
24434
24435 /*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
24436                 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
24437                 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
24438                 g a 0 to this bit.*/
24439 #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL
24440 #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT
24441 #undef RTC_CONTROL_BATTERY_DISABLE_MASK
24442 #define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                                         0x01000000
24443 #define RTC_CONTROL_BATTERY_DISABLE_SHIFT                                          31
24444 #define RTC_CONTROL_BATTERY_DISABLE_MASK                                           0x80000000U
24445 #undef SERDES_PLL_REF_SEL0_OFFSET
24446 #define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
24447 #undef SERDES_PLL_REF_SEL1_OFFSET
24448 #define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
24449 #undef SERDES_PLL_REF_SEL2_OFFSET
24450 #define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
24451 #undef SERDES_PLL_REF_SEL3_OFFSET
24452 #define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
24453 #undef SERDES_L0_L0_REF_CLK_SEL_OFFSET
24454 #define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
24455 #undef SERDES_L0_L1_REF_CLK_SEL_OFFSET
24456 #define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
24457 #undef SERDES_L0_L2_REF_CLK_SEL_OFFSET
24458 #define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
24459 #undef SERDES_L0_L3_REF_CLK_SEL_OFFSET
24460 #define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
24461 #undef SERDES_L2_TM_PLL_DIG_37_OFFSET
24462 #define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
24463 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET
24464 #define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
24465 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET
24466 #define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
24467 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET
24468 #define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
24469 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
24470 #define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
24471 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
24472 #define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
24473 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
24474 #define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
24475 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
24476 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
24477 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
24478 #define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
24479 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET
24480 #define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
24481 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET
24482 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
24483 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET
24484 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
24485 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET
24486 #define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
24487 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET
24488 #define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
24489 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET
24490 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
24491 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET
24492 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
24493 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET
24494 #define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
24495 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET
24496 #define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
24497 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET
24498 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
24499 #undef SERDES_L2_TM_DIG_6_OFFSET
24500 #define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
24501 #undef SERDES_L2_TX_DIG_TM_61_OFFSET
24502 #define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
24503 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET
24504 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
24505 #undef SERDES_L3_TM_DIG_6_OFFSET
24506 #define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
24507 #undef SERDES_L3_TX_DIG_TM_61_OFFSET
24508 #define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
24509 #undef SERDES_L3_TXPMA_ST_0_OFFSET
24510 #define SERDES_L3_TXPMA_ST_0_OFFSET                                                0XFD40CB00
24511 #undef SERDES_ICM_CFG0_OFFSET
24512 #define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
24513 #undef SERDES_ICM_CFG1_OFFSET
24514 #define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
24515 #undef SERDES_L1_TXPMD_TM_45_OFFSET
24516 #define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
24517 #undef SERDES_L1_TX_ANA_TM_118_OFFSET
24518 #define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
24519 #undef SERDES_L1_TXPMD_TM_48_OFFSET
24520 #define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
24521 #undef SERDES_L1_TX_ANA_TM_18_OFFSET
24522 #define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
24523
24524 /*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
24525                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
24526                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
24527 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL
24528 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
24529 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK
24530 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                                      0x0000000D
24531 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                                       0
24532 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                                        0x0000001FU
24533
24534 /*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
24535                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
24536                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
24537 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL
24538 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
24539 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK
24540 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                                      0x00000008
24541 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                                       0
24542 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                                        0x0000001FU
24543
24544 /*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
24545                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
24546                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
24547 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL
24548 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
24549 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK
24550 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                                      0x0000000F
24551 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                                       0
24552 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                                        0x0000001FU
24553
24554 /*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
24555                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
24556                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
24557 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL
24558 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
24559 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK
24560 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                                      0x0000000E
24561 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                                       0
24562 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                                        0x0000001FU
24563
24564 /*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/
24565 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL
24566 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
24567 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK
24568 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
24569 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT                          7
24570 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK                           0x00000080U
24571
24572 /*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
24573 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
24574 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
24575 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK
24576 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
24577 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT                          7
24578 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK                           0x00000080U
24579
24580 /*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
24581 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL
24582 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
24583 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK
24584 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL                           0x00000080
24585 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT                            3
24586 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK                             0x00000008U
24587
24588 /*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/
24589 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL
24590 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
24591 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK
24592 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
24593 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT                          7
24594 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK                           0x00000080U
24595
24596 /*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/
24597 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL
24598 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
24599 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK
24600 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
24601 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT                          7
24602 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK                           0x00000080U
24603
24604 /*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/
24605 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL
24606 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
24607 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK
24608 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL                           0x00000080
24609 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT                            1
24610 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK                             0x00000002U
24611
24612 /*Enable/Disable coarse code satureation limiting logic*/
24613 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL
24614 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
24615 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK
24616 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL                 0x00000000
24617 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT                  4
24618 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK                   0x00000010U
24619
24620 /*Spread Spectrum No of Steps [7:0]*/
24621 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
24622 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
24623 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
24624 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
24625 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
24626 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
24627
24628 /*Spread Spectrum No of Steps [10:8]*/
24629 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
24630 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
24631 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
24632 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
24633 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
24634 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
24635
24636 /*Spread Spectrum No of Steps [7:0]*/
24637 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
24638 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
24639 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
24640 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
24641 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
24642 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
24643
24644 /*Spread Spectrum No of Steps [10:8]*/
24645 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
24646 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
24647 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
24648 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
24649 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
24650 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
24651
24652 /*Spread Spectrum No of Steps [7:0]*/
24653 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
24654 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
24655 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
24656 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
24657 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
24658 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
24659
24660 /*Spread Spectrum No of Steps [10:8]*/
24661 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
24662 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
24663 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
24664 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
24665 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
24666 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
24667
24668 /*Step Size for Spread Spectrum [7:0]*/
24669 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
24670 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
24671 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
24672 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
24673 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
24674 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
24675
24676 /*Step Size for Spread Spectrum [15:8]*/
24677 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
24678 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
24679 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
24680 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
24681 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
24682 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
24683
24684 /*Step Size for Spread Spectrum [23:16]*/
24685 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
24686 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
24687 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
24688 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
24689 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
24690 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
24691
24692 /*Step Size for Spread Spectrum [25:24]*/
24693 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
24694 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
24695 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
24696 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
24697 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
24698 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
24699
24700 /*Enable/Disable test mode force on SS step size*/
24701 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
24702 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
24703 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
24704 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
24705 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
24706 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
24707
24708 /*Enable/Disable test mode force on SS no of steps*/
24709 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
24710 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
24711 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
24712 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
24713 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
24714 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
24715
24716 /*Step Size for Spread Spectrum [7:0]*/
24717 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
24718 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
24719 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
24720 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
24721 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
24722 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
24723
24724 /*Step Size for Spread Spectrum [15:8]*/
24725 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
24726 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
24727 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
24728 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
24729 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
24730 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
24731
24732 /*Step Size for Spread Spectrum [23:16]*/
24733 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
24734 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
24735 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
24736 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
24737 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
24738 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
24739
24740 /*Step Size for Spread Spectrum [25:24]*/
24741 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
24742 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
24743 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
24744 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
24745 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
24746 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
24747
24748 /*Enable/Disable test mode force on SS step size*/
24749 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
24750 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
24751 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
24752 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
24753 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
24754 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
24755
24756 /*Enable/Disable test mode force on SS no of steps*/
24757 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
24758 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
24759 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
24760 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
24761 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
24762 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
24763
24764 /*Step Size for Spread Spectrum [7:0]*/
24765 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
24766 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
24767 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
24768 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
24769 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
24770 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
24771
24772 /*Step Size for Spread Spectrum [15:8]*/
24773 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
24774 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
24775 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
24776 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
24777 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
24778 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
24779
24780 /*Step Size for Spread Spectrum [23:16]*/
24781 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
24782 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
24783 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
24784 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
24785 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
24786 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
24787
24788 /*Step Size for Spread Spectrum [25:24]*/
24789 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
24790 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
24791 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
24792 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
24793 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
24794 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
24795
24796 /*Enable/Disable test mode force on SS step size*/
24797 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
24798 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
24799 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
24800 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
24801 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
24802 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
24803
24804 /*Enable/Disable test mode force on SS no of steps*/
24805 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
24806 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
24807 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
24808 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
24809 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
24810 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
24811
24812 /*Enable test mode forcing on enable Spread Spectrum*/
24813 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL
24814 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
24815 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK
24816 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL                     0x00000000
24817 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT                      7
24818 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK                       0x00000080U
24819
24820 /*Bypass Descrambler*/
24821 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
24822 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
24823 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK
24824 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
24825 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
24826 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
24827
24828 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
24829 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
24830 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
24831 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
24832 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
24833 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
24834 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
24835
24836 /*Bypass scrambler signal*/
24837 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
24838 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
24839 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK
24840 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
24841 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
24842 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
24843
24844 /*Enable/disable scrambler bypass signal*/
24845 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
24846 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
24847 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
24848 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
24849 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
24850 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
24851
24852 /*Enable test mode force on fractional mode enable*/
24853 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL
24854 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
24855 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK
24856 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL                     0x00000000
24857 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT                      6
24858 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK                       0x00000040U
24859
24860 /*Bypass 8b10b decoder*/
24861 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL
24862 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
24863 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK
24864 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL                                   0x00000000
24865 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                                    3
24866 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                                     0x00000008U
24867
24868 /*Enable Bypass for <3> TM_DIG_CTRL_6*/
24869 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL
24870 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
24871 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK
24872 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL                                 0x00000000
24873 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT                                  2
24874 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK                                   0x00000004U
24875
24876 /*Bypass Descrambler*/
24877 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
24878 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
24879 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK
24880 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
24881 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
24882 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
24883
24884 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
24885 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
24886 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
24887 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
24888 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
24889 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
24890 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
24891
24892 /*Enable/disable encoder bypass signal*/
24893 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL
24894 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
24895 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK
24896 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL                                   0x00000000
24897 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                                    3
24898 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                                     0x00000008U
24899
24900 /*Bypass scrambler signal*/
24901 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
24902 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
24903 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK
24904 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
24905 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
24906 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
24907
24908 /*Enable/disable scrambler bypass signal*/
24909 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
24910 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
24911 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
24912 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
24913 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
24914 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
24915
24916 /*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/
24917 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL
24918 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
24919 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK
24920 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL                                    0x00000001
24921 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT                                     4
24922 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK                                      0x000000F0U
24923
24924 /*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
24925                 , 7 - Unused*/
24926 #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
24927 #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
24928 #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK
24929 #define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                                          0x00000000
24930 #define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                                           0
24931 #define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                                            0x00000007U
24932
24933 /*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
24934                  7 - Unused*/
24935 #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL
24936 #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
24937 #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK
24938 #define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                                          0x00000000
24939 #define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                                           4
24940 #define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                                            0x00000070U
24941
24942 /*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
24943                  7 - Unused*/
24944 #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL
24945 #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
24946 #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK
24947 #define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                                          0x00000000
24948 #define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                                           0
24949 #define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                                            0x00000007U
24950
24951 /*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
24952                  7 - Unused*/
24953 #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL
24954 #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
24955 #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK
24956 #define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                                          0x00000000
24957 #define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                                           4
24958 #define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                                            0x00000070U
24959
24960 /*Enable/disable DP post2 path*/
24961 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
24962 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
24963 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
24964 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL                 0x00000000
24965 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT                  5
24966 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK                   0x00000020U
24967
24968 /*Override enable/disable of DP post2 path*/
24969 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
24970 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
24971 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
24972 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL            0x00000000
24973 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT             4
24974 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK              0x00000010U
24975
24976 /*Override enable/disable of DP post1 path*/
24977 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
24978 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
24979 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
24980 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL            0x00000000
24981 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT             2
24982 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK              0x00000004U
24983
24984 /*Enable/disable DP main path*/
24985 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
24986 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
24987 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
24988 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL                  0x00000000
24989 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT                   1
24990 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK                    0x00000002U
24991
24992 /*Override enable/disable of DP main path*/
24993 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
24994 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
24995 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
24996 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL             0x00000000
24997 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT              0
24998 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK               0x00000001U
24999
25000 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
25001 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
25002 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
25003 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
25004 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
25005 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
25006 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
25007
25008 /*Margining factor value*/
25009 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
25010 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
25011 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
25012 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL                 0x00000000
25013 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT                  0
25014 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK                   0x0000001FU
25015
25016 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
25017 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
25018 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
25019 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
25020 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
25021 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
25022 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
25023 #undef CRL_APB_RST_LPD_TOP_OFFSET
25024 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
25025 #undef USB3_0_FPD_POWER_PRSNT_OFFSET
25026 #define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
25027 #undef CRL_APB_RST_LPD_TOP_OFFSET
25028 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
25029 #undef CRL_APB_RST_LPD_IOU0_OFFSET
25030 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
25031 #undef SIOU_SATA_MISC_CTRL_OFFSET
25032 #define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
25033 #undef CRF_APB_RST_FPD_TOP_OFFSET
25034 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25035 #undef CRF_APB_RST_FPD_TOP_OFFSET
25036 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25037 #undef CRF_APB_RST_FPD_TOP_OFFSET
25038 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25039 #undef DP_DP_PHY_RESET_OFFSET
25040 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
25041 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
25042 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
25043 #undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET
25044 #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
25045 #undef USB3_0_XHCI_GFLADJ_OFFSET
25046 #define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
25047 #undef PCIE_ATTRIB_ATTR_37_OFFSET
25048 #define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
25049 #undef PCIE_ATTRIB_ATTR_25_OFFSET
25050 #define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
25051 #undef PCIE_ATTRIB_ATTR_7_OFFSET
25052 #define PCIE_ATTRIB_ATTR_7_OFFSET                                                  0XFD48001C
25053 #undef PCIE_ATTRIB_ATTR_8_OFFSET
25054 #define PCIE_ATTRIB_ATTR_8_OFFSET                                                  0XFD480020
25055 #undef PCIE_ATTRIB_ATTR_9_OFFSET
25056 #define PCIE_ATTRIB_ATTR_9_OFFSET                                                  0XFD480024
25057 #undef PCIE_ATTRIB_ATTR_10_OFFSET
25058 #define PCIE_ATTRIB_ATTR_10_OFFSET                                                 0XFD480028
25059 #undef PCIE_ATTRIB_ATTR_11_OFFSET
25060 #define PCIE_ATTRIB_ATTR_11_OFFSET                                                 0XFD48002C
25061 #undef PCIE_ATTRIB_ATTR_12_OFFSET
25062 #define PCIE_ATTRIB_ATTR_12_OFFSET                                                 0XFD480030
25063 #undef PCIE_ATTRIB_ATTR_13_OFFSET
25064 #define PCIE_ATTRIB_ATTR_13_OFFSET                                                 0XFD480034
25065 #undef PCIE_ATTRIB_ATTR_14_OFFSET
25066 #define PCIE_ATTRIB_ATTR_14_OFFSET                                                 0XFD480038
25067 #undef PCIE_ATTRIB_ATTR_15_OFFSET
25068 #define PCIE_ATTRIB_ATTR_15_OFFSET                                                 0XFD48003C
25069 #undef PCIE_ATTRIB_ATTR_16_OFFSET
25070 #define PCIE_ATTRIB_ATTR_16_OFFSET                                                 0XFD480040
25071 #undef PCIE_ATTRIB_ATTR_17_OFFSET
25072 #define PCIE_ATTRIB_ATTR_17_OFFSET                                                 0XFD480044
25073 #undef PCIE_ATTRIB_ATTR_18_OFFSET
25074 #define PCIE_ATTRIB_ATTR_18_OFFSET                                                 0XFD480048
25075 #undef PCIE_ATTRIB_ATTR_27_OFFSET
25076 #define PCIE_ATTRIB_ATTR_27_OFFSET                                                 0XFD48006C
25077 #undef PCIE_ATTRIB_ATTR_50_OFFSET
25078 #define PCIE_ATTRIB_ATTR_50_OFFSET                                                 0XFD4800C8
25079 #undef PCIE_ATTRIB_ATTR_105_OFFSET
25080 #define PCIE_ATTRIB_ATTR_105_OFFSET                                                0XFD4801A4
25081 #undef PCIE_ATTRIB_ATTR_106_OFFSET
25082 #define PCIE_ATTRIB_ATTR_106_OFFSET                                                0XFD4801A8
25083 #undef PCIE_ATTRIB_ATTR_107_OFFSET
25084 #define PCIE_ATTRIB_ATTR_107_OFFSET                                                0XFD4801AC
25085 #undef PCIE_ATTRIB_ATTR_108_OFFSET
25086 #define PCIE_ATTRIB_ATTR_108_OFFSET                                                0XFD4801B0
25087 #undef PCIE_ATTRIB_ATTR_109_OFFSET
25088 #define PCIE_ATTRIB_ATTR_109_OFFSET                                                0XFD4801B4
25089 #undef PCIE_ATTRIB_ATTR_34_OFFSET
25090 #define PCIE_ATTRIB_ATTR_34_OFFSET                                                 0XFD480088
25091 #undef PCIE_ATTRIB_ATTR_53_OFFSET
25092 #define PCIE_ATTRIB_ATTR_53_OFFSET                                                 0XFD4800D4
25093 #undef PCIE_ATTRIB_ATTR_41_OFFSET
25094 #define PCIE_ATTRIB_ATTR_41_OFFSET                                                 0XFD4800A4
25095 #undef PCIE_ATTRIB_ATTR_97_OFFSET
25096 #define PCIE_ATTRIB_ATTR_97_OFFSET                                                 0XFD480184
25097 #undef PCIE_ATTRIB_ATTR_100_OFFSET
25098 #define PCIE_ATTRIB_ATTR_100_OFFSET                                                0XFD480190
25099 #undef PCIE_ATTRIB_ATTR_101_OFFSET
25100 #define PCIE_ATTRIB_ATTR_101_OFFSET                                                0XFD480194
25101 #undef PCIE_ATTRIB_ATTR_37_OFFSET
25102 #define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
25103 #undef PCIE_ATTRIB_ATTR_93_OFFSET
25104 #define PCIE_ATTRIB_ATTR_93_OFFSET                                                 0XFD480174
25105 #undef PCIE_ATTRIB_ID_OFFSET
25106 #define PCIE_ATTRIB_ID_OFFSET                                                      0XFD480200
25107 #undef PCIE_ATTRIB_SUBSYS_ID_OFFSET
25108 #define PCIE_ATTRIB_SUBSYS_ID_OFFSET                                               0XFD480204
25109 #undef PCIE_ATTRIB_REV_ID_OFFSET
25110 #define PCIE_ATTRIB_REV_ID_OFFSET                                                  0XFD480208
25111 #undef PCIE_ATTRIB_ATTR_24_OFFSET
25112 #define PCIE_ATTRIB_ATTR_24_OFFSET                                                 0XFD480060
25113 #undef PCIE_ATTRIB_ATTR_25_OFFSET
25114 #define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
25115 #undef PCIE_ATTRIB_ATTR_4_OFFSET
25116 #define PCIE_ATTRIB_ATTR_4_OFFSET                                                  0XFD480010
25117 #undef PCIE_ATTRIB_ATTR_89_OFFSET
25118 #define PCIE_ATTRIB_ATTR_89_OFFSET                                                 0XFD480164
25119 #undef PCIE_ATTRIB_ATTR_79_OFFSET
25120 #define PCIE_ATTRIB_ATTR_79_OFFSET                                                 0XFD48013C
25121 #undef PCIE_ATTRIB_ATTR_43_OFFSET
25122 #define PCIE_ATTRIB_ATTR_43_OFFSET                                                 0XFD4800AC
25123
25124 /*USB 0 reset for control registers*/
25125 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
25126 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
25127 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
25128 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
25129 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
25130 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
25131
25132 /*This bit is used to choose between PIPE power present and 1'b1*/
25133 #undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
25134 #undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
25135 #undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK
25136 #define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
25137 #define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                                        0
25138 #define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                                         0x00000001U
25139
25140 /*USB 0 sleep circuit reset*/
25141 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
25142 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
25143 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
25144 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
25145 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
25146 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
25147
25148 /*USB 0 reset*/
25149 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
25150 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
25151 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
25152 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
25153 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
25154 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
25155
25156 /*GEM 3 reset*/
25157 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
25158 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
25159 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
25160 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
25161 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
25162 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
25163
25164 /*Sata PM clock control select*/
25165 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
25166 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
25167 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK
25168 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
25169 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT                                  0
25170 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK                                   0x00000003U
25171
25172 /*Sata block level reset*/
25173 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
25174 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
25175 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
25176 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
25177 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
25178 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
25179
25180 /*PCIE config reset*/
25181 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
25182 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
25183 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
25184 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
25185 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
25186 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
25187
25188 /*PCIE control block level reset*/
25189 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
25190 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
25191 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
25192 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
25193 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
25194 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
25195
25196 /*PCIE bridge block level reset (AXI interface)*/
25197 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
25198 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
25199 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
25200 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
25201 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
25202 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
25203
25204 /*Display Port block level reset (includes DPDMA)*/
25205 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
25206 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
25207 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
25208 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
25209 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
25210 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
25211
25212 /*Set to '1' to hold the GT in reset. Clear to release.*/
25213 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
25214 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
25215 #undef DP_DP_PHY_RESET_GT_RESET_MASK
25216 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
25217 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
25218 #define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
25219
25220 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
25221                 ane0 Bits [3:2] - lane 1*/
25222 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
25223 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
25224 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
25225 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
25226 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
25227 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
25228
25229 /*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
25230                 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
25231                 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
25232                 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
25233                 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
25234                 alue. Note: This field is valid only in device mode.*/
25235 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
25236 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
25237 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
25238 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL                                   0x00000000
25239 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                                    10
25240 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                                     0x00003C00U
25241
25242 /*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
25243                  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
25244                 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
25245                 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
25246                 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
25247                 ng hibernation. - This bit is valid only in device mode.*/
25248 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
25249 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
25250 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
25251 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                                     0x00000000
25252 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                                      9
25253 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                                       0x00000200U
25254
25255 /*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
25256                 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
25257                  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
25258                 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
25259                 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
25260                 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
25261                 d.*/
25262 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
25263 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
25264 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
25265 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                                    0x00000000
25266 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                                     8
25267 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                                      0x00000100U
25268
25269 /*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
25270                 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
25271                 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
25272                  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
25273                  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
25274 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
25275 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
25276 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK
25277 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                                      0x00000000
25278 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                                       7
25279 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                                        0x00000080U
25280
25281 /*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
25282                 figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
25283                 ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
25284                 r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
25285                 t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
25286                 g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
25287                  when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
25288 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
25289 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
25290 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
25291 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL                                0x00000000
25292 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT                                 6
25293 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK                                  0x00000040U
25294
25295 /*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
25296                 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
25297                 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
25298                 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
25299 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
25300 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
25301 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK
25302 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                                      0x00000000
25303 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                                       5
25304 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                                        0x00000020U
25305
25306 /*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
25307                 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
25308                 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
25309                 lected through DWC_USB3_HSPHY_INTERFACE.*/
25310 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
25311 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
25312 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
25313 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL                               0x00000000
25314 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT                                4
25315 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK                                 0x00000010U
25316
25317 /*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
25318                  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
25319                 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
25320                  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
25321                  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
25322 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
25323 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
25324 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK
25325 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                                       0x00000000
25326 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                                        3
25327 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                                         0x00000008U
25328
25329 /*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
25330                 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
25331                 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
25332                 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
25333                 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
25334                 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
25335                  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
25336                 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
25337 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
25338 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
25339 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
25340 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                                     0x00000000
25341 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                                      0
25342 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                                       0x00000007U
25343
25344 /*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
25345                 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
25346                 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
25347                 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
25348                 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
25349                 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
25350                 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
25351                 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
25352                 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
25353 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
25354 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
25355 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
25356 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL                              0x00000000
25357 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT                               8
25358 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK                                0x003FFF00U
25359
25360 /*Status Read value of PLL Lock*/
25361 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
25362 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
25363 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
25364 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
25365 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
25366 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
25367 #define SERDES_L0_PLL_STATUS_READ_1_OFFSET                                         0XFD4023E4
25368
25369 /*Status Read value of PLL Lock*/
25370 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
25371 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
25372 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
25373 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
25374 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
25375 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
25376 #define SERDES_L1_PLL_STATUS_READ_1_OFFSET                                         0XFD4063E4
25377
25378 /*Status Read value of PLL Lock*/
25379 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
25380 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
25381 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
25382 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
25383 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
25384 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
25385 #define SERDES_L2_PLL_STATUS_READ_1_OFFSET                                         0XFD40A3E4
25386
25387 /*Status Read value of PLL Lock*/
25388 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
25389 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
25390 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
25391 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
25392 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
25393 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
25394 #define SERDES_L3_PLL_STATUS_READ_1_OFFSET                                         0XFD40E3E4
25395
25396 /*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
25397                 gister.; EP=0x0001; RP=0x0001*/
25398 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
25399 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
25400 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
25401 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL                  0x000009FF
25402 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT                   14
25403 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK                    0x00004000U
25404
25405 /*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
25406                 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
25407 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
25408 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
25409 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
25410 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL              0x00000905
25411 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT               9
25412 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK                0x00000200U
25413
25414 /*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
25415                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
25416                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
25417                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
25418                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
25419                 re size in bytes.; EP=0x0004; RP=0x0000*/
25420 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
25421 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
25422 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK
25423 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
25424 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT                                         0
25425 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK                                          0x0000FFFFU
25426
25427 /*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
25428                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
25429                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
25430                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
25431                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
25432                 re size in bytes.; EP=0xFFF0; RP=0x0000*/
25433 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
25434 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
25435 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK
25436 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
25437 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT                                         0
25438 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK                                          0x0000FFFFU
25439
25440 /*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
25441                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
25442                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
25443                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
25444                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
25445                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
25446                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
25447 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
25448 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
25449 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK
25450 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
25451 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT                                         0
25452 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK                                          0x0000FFFFU
25453
25454 /*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
25455                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
25456                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
25457                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
25458                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
25459                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
25460                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
25461 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
25462 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
25463 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK
25464 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
25465 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT                                        0
25466 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK                                         0x0000FFFFU
25467
25468 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
25469                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
25470                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
25471                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
25472                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
25473                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
25474                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
25475                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/
25476 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
25477 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
25478 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK
25479 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
25480 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT                                        0
25481 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK                                         0x0000FFFFU
25482
25483 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
25484                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
25485                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
25486                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
25487                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
25488                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
25489                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
25490                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/
25491 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
25492 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
25493 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK
25494 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
25495 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT                                        0
25496 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK                                         0x0000FFFFU
25497
25498 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
25499                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
25500                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
25501                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
25502                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
25503                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
25504                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
25505                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
25506                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
25507 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
25508 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
25509 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK
25510 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
25511 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT                                        0
25512 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK                                         0x0000FFFFU
25513
25514 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
25515                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
25516                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
25517                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
25518                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
25519                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
25520                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
25521                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
25522                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/
25523 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
25524 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
25525 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK
25526 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
25527 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT                                        0
25528 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK                                         0x0000FFFFU
25529
25530 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
25531                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
25532                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
25533                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
25534                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
25535                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
25536                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
25537                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/
25538 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
25539 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
25540 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK
25541 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
25542 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT                                        0
25543 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK                                         0x0000FFFFU
25544
25545 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
25546                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
25547                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
25548                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
25549                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
25550                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
25551                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
25552                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/
25553 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
25554 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
25555 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK
25556 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
25557 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT                                        0
25558 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK                                         0x0000FFFFU
25559
25560 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
25561                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
25562                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
25563                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
25564                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
25565                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
25566                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
25567                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
25568                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
25569 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
25570 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
25571 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK
25572 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
25573 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT                                        0
25574 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK                                         0x0000FFFFU
25575
25576 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
25577                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
25578                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
25579                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
25580                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
25581                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
25582                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
25583                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
25584                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
25585 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
25586 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
25587 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK
25588 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
25589 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT                                        0
25590 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK                                         0x0000FFFFU
25591
25592 /*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
25593                 to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/
25594 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL
25595 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
25596 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK
25597 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL              0x00002138
25598 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT               8
25599 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK                0x00000700U
25600
25601 /*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
25602                 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
25603                  32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/
25604 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL
25605 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
25606 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK
25607 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL                0x00002138
25608 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT                 3
25609 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK                  0x00000038U
25610
25611 /*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
25612                 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
25613                 tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
25614                 gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/
25615 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL
25616 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
25617 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK
25618 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL                  0x00009C02
25619 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT                   4
25620 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK                    0x000000F0U
25621
25622 /*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
25623                 lity.; EP=0x009C; RP=0x0000*/
25624 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL
25625 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
25626 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK
25627 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL                           0x00009C02
25628 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT                            8
25629 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK                             0x0000FF00U
25630
25631 /*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
25632                 ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/
25633 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
25634 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
25635 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK
25636 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
25637 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT                       0
25638 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK                        0x000007FFU
25639
25640 /*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
25641                 osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/
25642 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL
25643 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
25644 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK
25645 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL                      0x00000248
25646 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT                       0
25647 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK                        0x0000007FU
25648
25649 /*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
25650                 a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
25651                 completion header credits must be <= 80; EP=0x0004; RP=0x000C*/
25652 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL
25653 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
25654 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK
25655 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL                     0x00000248
25656 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT                      7
25657 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK                       0x00003F80U
25658
25659 /*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
25660                 redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
25661                 d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
25662                 less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/
25663 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
25664 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
25665 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK
25666 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
25667 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT                      0
25668 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK                       0x000007FFU
25669
25670 /*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
25671                 han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/
25672 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
25673 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
25674 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK
25675 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
25676 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT                       0
25677 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK                        0x000007FFU
25678
25679 /*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
25680                 0*/
25681 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL
25682 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
25683 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK
25684 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL                              0x00007E04
25685 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT                               15
25686 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK                                0x00008000U
25687
25688 /*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/
25689 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL
25690 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
25691 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK
25692 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL                            0x00007E04
25693 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT                             14
25694 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK                              0x00004000U
25695
25696 /*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
25697                 cap structure; EP=0x0003; RP=0x0003*/
25698 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL
25699 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
25700 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK
25701 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL                                 0x00007E04
25702 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT                                  12
25703 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK                                   0x00003000U
25704
25705 /*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
25706                 mber of brams configured for transmit; EP=0x001C; RP=0x001C*/
25707 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL
25708 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
25709 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK
25710 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL                         0x00007E04
25711 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT                          7
25712 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK                           0x00000F80U
25713
25714 /*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
25715                 d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/
25716 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL
25717 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
25718 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK
25719 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL                      0x00007E04
25720 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT                       0
25721 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK                        0x0000007FU
25722
25723 /*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
25724                 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/
25725 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL
25726 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
25727 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK
25728 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL                                0x00000100
25729 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT                                 0
25730 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK                                  0x000000FFU
25731
25732 /*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
25733                 ty.; EP=0x0048; RP=0x0060*/
25734 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL
25735 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
25736 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK
25737 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL                             0x00003D48
25738 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT                              0
25739 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK                               0x000000FFU
25740
25741 /*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
25742                  to Cap structure; EP=0x0000; RP=0x0000*/
25743 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL
25744 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
25745 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK
25746 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL         0x00000160
25747 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT          9
25748 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK           0x00000200U
25749
25750 /*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
25751                 he management port.; EP=0x0001; RP=0x0000*/
25752 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
25753 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
25754 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
25755 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
25756 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
25757 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
25758
25759 /*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
25760                 ity.; EP=0x0060; RP=0x0000*/
25761 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL
25762 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
25763 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK
25764 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL                            0x00000160
25765 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT                             0
25766 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK                              0x000000FFU
25767
25768 /*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
25769                 he management port.; EP=0x0001; RP=0x0000*/
25770 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
25771 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
25772 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
25773 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
25774 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
25775 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
25776
25777 /*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/
25778 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL
25779 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
25780 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK
25781 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL                    0x00000104
25782 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT                     0
25783 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK                      0x0000003FU
25784
25785 /*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
25786                 4; RP=0x0004*/
25787 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL
25788 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
25789 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK
25790 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL                       0x00000104
25791 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT                        6
25792 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK                         0x00000FC0U
25793
25794 /*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/
25795 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL
25796 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
25797 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK
25798 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL                           0x000000F0
25799 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT                            6
25800 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK                             0x00000040U
25801
25802 /*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
25803                 LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
25804                 Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
25805                 EP=0x0000; RP=0x07FF*/
25806 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL
25807 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
25808 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK
25809 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL                          0x00000000
25810 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT                           5
25811 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK                            0x0000FFE0U
25812
25813 /*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/
25814 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL
25815 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
25816 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK
25817 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL                     0x00000000
25818 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT                      1
25819 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK                       0x00000002U
25820
25821 /*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
25822                 Required for Root.; EP=0x0000; RP=0x0001*/
25823 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL
25824 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
25825 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK
25826 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL   0x000009FF
25827 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT    9
25828 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK     0x00000200U
25829
25830 /*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
25831                 _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
25832 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
25833 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
25834 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK
25835 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL                       0x00000000
25836 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT                        15
25837 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK                         0x00008000U
25838
25839 /*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
25840                 TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
25841                 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/
25842 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL
25843 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
25844 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK
25845 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL                          0x00000000
25846 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT                           0
25847 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK                            0x00007FFFU
25848
25849 /*Device ID for the the PCIe Cap Structure Device ID field*/
25850 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL
25851 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
25852 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK
25853 #define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL                                           0x10EE7024
25854 #define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT                                            0
25855 #define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK                                             0x0000FFFFU
25856
25857 /*Vendor ID for the PCIe Cap Structure Vendor ID field*/
25858 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL
25859 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
25860 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK
25861 #define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL                                          0x10EE7024
25862 #define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT                                           16
25863 #define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK                                            0xFFFF0000U
25864
25865 /*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/
25866 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL
25867 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
25868 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK
25869 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL                                 0x10EE0007
25870 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT                                  0
25871 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK                                   0x0000FFFFU
25872
25873 /*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/
25874 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL
25875 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
25876 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK
25877 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL                            0x10EE0007
25878 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT                             16
25879 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK                              0xFFFF0000U
25880
25881 /*Revision ID for the the PCIe Cap Structure*/
25882 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
25883 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
25884 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK
25885 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
25886 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT                                        0
25887 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK                                         0x000000FFU
25888
25889 /*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
25890                 8000; RP=0x8000*/
25891 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
25892 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
25893 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK
25894 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
25895 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT                                  0
25896 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK                                   0x0000FFFFU
25897
25898 /*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
25899                 0005; RP=0x0006*/
25900 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL
25901 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
25902 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK
25903 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL                                 0x00000905
25904 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT                                  0
25905 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK                                   0x000000FFU
25906
25907 /*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/
25908 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL
25909 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
25910 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK
25911 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL                       0x00000905
25912 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT                        8
25913 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK                         0x00000100U
25914
25915 /*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
25916                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
25917                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
25918 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
25919 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
25920 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
25921 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
25922 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
25923 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
25924
25925 /*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
25926                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
25927                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
25928 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
25929 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
25930 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
25931 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
25932 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
25933 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
25934
25935 /*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
25936                 0x0140; RP=0x0140*/
25937 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL
25938 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
25939 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK
25940 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL                           0x00002281
25941 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT                            1
25942 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK                             0x00001FFEU
25943
25944 /*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/
25945 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL
25946 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
25947 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK
25948 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL                 0x00000000
25949 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT                  5
25950 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK                   0x00000020U
25951
25952 /*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
25953                  the management port.; EP=0x0001; RP=0x0000*/
25954 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL
25955 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
25956 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK
25957 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL                                0x00000100
25958 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT                                 8
25959 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK                                  0x00000100U
25960 #undef CRL_APB_RST_LPD_TOP_OFFSET
25961 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
25962 #undef CRL_APB_RST_LPD_IOU0_OFFSET
25963 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
25964 #undef CRF_APB_RST_FPD_TOP_OFFSET
25965 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25966 #undef CRF_APB_RST_FPD_TOP_OFFSET
25967 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25968 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
25969 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
25970 #undef DP_DP_PHY_RESET_OFFSET
25971 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
25972 #undef CRF_APB_RST_FPD_TOP_OFFSET
25973 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
25974
25975 /*USB 0 reset for control registers*/
25976 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
25977 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
25978 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
25979 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
25980 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
25981 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
25982
25983 /*USB 0 sleep circuit reset*/
25984 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
25985 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
25986 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
25987 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
25988 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
25989 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
25990
25991 /*USB 0 reset*/
25992 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
25993 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
25994 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
25995 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
25996 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
25997 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
25998
25999 /*GEM 3 reset*/
26000 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
26001 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
26002 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
26003 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
26004 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
26005 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
26006
26007 /*Sata block level reset*/
26008 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
26009 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
26010 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
26011 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
26012 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
26013 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
26014
26015 /*PCIE config reset*/
26016 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
26017 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
26018 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
26019 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
26020 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
26021 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
26022
26023 /*PCIE control block level reset*/
26024 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
26025 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
26026 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
26027 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
26028 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
26029 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
26030
26031 /*PCIE bridge block level reset (AXI interface)*/
26032 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
26033 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
26034 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
26035 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
26036 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
26037 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
26038
26039 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
26040                 ane0 Bits [3:2] - lane 1*/
26041 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
26042 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
26043 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
26044 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
26045 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
26046 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
26047
26048 /*Set to '1' to hold the GT in reset. Clear to release.*/
26049 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
26050 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
26051 #undef DP_DP_PHY_RESET_GT_RESET_MASK
26052 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
26053 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
26054 #define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
26055
26056 /*Display Port block level reset (includes DPDMA)*/
26057 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
26058 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
26059 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
26060 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
26061 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
26062 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
26063 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
26064 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
26065 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
26066 #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120
26067
26068 /*Power-up Request Interrupt Enable for PL*/
26069 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
26070 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
26071 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK
26072 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                                      0x00000000
26073 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                                       23
26074 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                                        0x00800000U
26075
26076 /*Power-up Request Trigger for PL*/
26077 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL
26078 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
26079 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK
26080 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                                        0x00000000
26081 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                                         23
26082 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                                          0x00800000U
26083
26084 /*Power-up Request Status for PL*/
26085 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL
26086 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT
26087 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK
26088 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                                      0x00000000
26089 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                                       23
26090 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                                        0x00800000U
26091 #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
26092 #undef GPIO_MASK_DATA_5_MSW_OFFSET
26093 #define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
26094 #undef GPIO_DIRM_5_OFFSET
26095 #define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
26096 #undef GPIO_OEN_5_OFFSET
26097 #define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
26098 #undef GPIO_DATA_5_OFFSET
26099 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
26100 #undef GPIO_DATA_5_OFFSET
26101 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
26102 #undef GPIO_DATA_5_OFFSET
26103 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
26104
26105 /*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/
26106 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL
26107 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
26108 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK
26109 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                                     0x00000000
26110 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                                      16
26111 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                                       0xFFFF0000U
26112
26113 /*Operation is the same as DIRM_0[DIRECTION_0]*/
26114 #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL
26115 #undef GPIO_DIRM_5_DIRECTION_5_SHIFT
26116 #undef GPIO_DIRM_5_DIRECTION_5_MASK
26117 #define GPIO_DIRM_5_DIRECTION_5_DEFVAL
26118 #define GPIO_DIRM_5_DIRECTION_5_SHIFT                                              0
26119 #define GPIO_DIRM_5_DIRECTION_5_MASK                                               0xFFFFFFFFU
26120
26121 /*Operation is the same as OEN_0[OP_ENABLE_0]*/
26122 #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL
26123 #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT
26124 #undef GPIO_OEN_5_OP_ENABLE_5_MASK
26125 #define GPIO_OEN_5_OP_ENABLE_5_DEFVAL
26126 #define GPIO_OEN_5_OP_ENABLE_5_SHIFT                                               0
26127 #define GPIO_OEN_5_OP_ENABLE_5_MASK                                                0xFFFFFFFFU
26128
26129 /*Output Data*/
26130 #undef GPIO_DATA_5_DATA_5_DEFVAL
26131 #undef GPIO_DATA_5_DATA_5_SHIFT
26132 #undef GPIO_DATA_5_DATA_5_MASK
26133 #define GPIO_DATA_5_DATA_5_DEFVAL
26134 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
26135 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
26136
26137 /*Output Data*/
26138 #undef GPIO_DATA_5_DATA_5_DEFVAL
26139 #undef GPIO_DATA_5_DATA_5_SHIFT
26140 #undef GPIO_DATA_5_DATA_5_MASK
26141 #define GPIO_DATA_5_DATA_5_DEFVAL
26142 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
26143 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
26144
26145 /*Output Data*/
26146 #undef GPIO_DATA_5_DATA_5_DEFVAL
26147 #undef GPIO_DATA_5_DATA_5_SHIFT
26148 #undef GPIO_DATA_5_DATA_5_MASK
26149 #define GPIO_DATA_5_DATA_5_DEFVAL
26150 #define GPIO_DATA_5_DATA_5_SHIFT                                                   0
26151 #define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
26152 #ifdef __cplusplus
26153 extern "C" {
26154 #endif
26155  int psu_init ();
26156  unsigned long psu_ps_pl_isolation_removal_data();
26157  unsigned long psu_ps_pl_reset_config_data();
26158 #ifdef __cplusplus
26159 }
26160 #endif