1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_map.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file contains all the peripheral register's definitions
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6 * and memory mapping.
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7 ********************************************************************************
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12 ********************************************************************************
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13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 *******************************************************************************/
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef __STM32F10x_MAP_H
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23 #define __STM32F10x_MAP_H
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29 /* Includes ------------------------------------------------------------------*/
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30 #include "stm32f10x_conf.h"
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31 #include "stm32f10x_type.h"
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32 #include "cortexm3_macro.h"
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34 /* Exported types ------------------------------------------------------------*/
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35 /******************************************************************************/
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36 /* IP registers structures */
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37 /******************************************************************************/
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39 /*------------------------ Analog to Digital Converter -----------------------*/
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64 /*------------------------ Backup Registers ----------------------------------*/
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96 /*------------------------ Controller Area Network ---------------------------*/
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103 } CAN_TxMailBox_TypeDef;
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111 } CAN_FIFOMailBox_TypeDef;
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117 } CAN_FilterRegister_TypeDef;
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130 CAN_TxMailBox_TypeDef sTxMailBox[3];
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131 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
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142 CAN_FilterRegister_TypeDef sFilterRegister[14];
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145 /*------------------------ DMA Controller ------------------------------------*/
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152 } DMA_Channel_TypeDef;
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160 /*------------------------ External Interrupt/Event Controller ---------------*/
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171 /*------------------------ FLASH and Option Bytes Registers ------------------*/
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197 /*------------------------ General Purpose and Alternate Function IO ---------*/
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216 /*------------------------ Inter-integrated Circuit Interface ----------------*/
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239 /*------------------------ Independent WATCHDOG ------------------------------*/
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248 /*------------------------ Nested Vectored Interrupt Controller --------------*/
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267 vu32 IRQControlState;
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268 vu32 ExceptionTableOffset;
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272 vu32 SystemPriority[3];
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273 vu32 SysHandlerCtrl;
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274 vu32 ConfigFaultStatus;
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275 vu32 HardFaultStatus;
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276 vu32 DebugFaultStatus;
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277 vu32 MemoryManageFaultAddr;
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281 /*------------------------ Power Controller ----------------------------------*/
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288 /*------------------------ Reset and Clock Controller ------------------------*/
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303 /*------------------------ Real-Time Clock -----------------------------------*/
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328 /*------------------------ Serial Peripheral Interface -----------------------*/
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347 /*------------------------ SystemTick ----------------------------------------*/
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356 /*------------------------ Advanced Control Timer ----------------------------*/
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401 /*------------------------ General Purpose Timer -----------------------------*/
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442 /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
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461 /*------------------------ Window WATCHDOG -----------------------------------*/
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469 /******************************************************************************/
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470 /* Peripheral memory map */
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471 /******************************************************************************/
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472 /* Peripheral and SRAM base address in the alias region */
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473 #define PERIPH_BB_BASE ((u32)0x42000000)
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474 #define SRAM_BB_BASE ((u32)0x22000000)
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476 /* Peripheral and SRAM base address in the bit-band region */
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477 #define SRAM_BASE ((u32)0x20000000)
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478 #define PERIPH_BASE ((u32)0x40000000)
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480 /* Flash refisters base address */
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481 #define FLASH_BASE ((u32)0x40022000)
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482 /* Flash Option Bytes base address */
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483 #define OB_BASE ((u32)0x1FFFF800)
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485 /* Peripheral memory map */
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486 #define APB1PERIPH_BASE PERIPH_BASE
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487 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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488 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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490 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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491 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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492 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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493 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
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494 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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495 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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496 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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497 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
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498 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
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499 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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500 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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501 #define CAN_BASE (APB1PERIPH_BASE + 0x6400)
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502 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
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503 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
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505 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
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506 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
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507 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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508 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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509 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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510 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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511 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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512 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
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513 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
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514 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
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515 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
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516 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
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518 #define DMA_BASE (AHBPERIPH_BASE + 0x0000)
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519 #define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
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520 #define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
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521 #define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
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522 #define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
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523 #define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
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524 #define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
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525 #define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
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526 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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528 /* System Control Space memory map */
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529 #define SCS_BASE ((u32)0xE000E000)
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531 #define SysTick_BASE (SCS_BASE + 0x0010)
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532 #define NVIC_BASE (SCS_BASE + 0x0100)
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533 #define SCB_BASE (SCS_BASE + 0x0D00)
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536 /******************************************************************************/
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537 /* IPs' declaration */
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538 /******************************************************************************/
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540 /*------------------- Non Debug Mode -----------------------------------------*/
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543 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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547 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
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551 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
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555 #define RTC ((RTC_TypeDef *) RTC_BASE)
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559 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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563 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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567 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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571 #define USART2 ((USART_TypeDef *) USART2_BASE)
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572 #endif /*_USART2 */
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575 #define USART3 ((USART_TypeDef *) USART3_BASE)
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576 #endif /*_USART3 */
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579 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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583 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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587 #define CAN ((CAN_TypeDef *) CAN_BASE)
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591 #define BKP ((BKP_TypeDef *) BKP_BASE)
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595 #define PWR ((PWR_TypeDef *) PWR_BASE)
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599 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
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603 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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607 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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611 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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615 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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619 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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623 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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627 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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631 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
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635 #define TIM1 ((TIM1_TypeDef *) TIM1_BASE)
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639 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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643 #define USART1 ((USART_TypeDef *) USART1_BASE)
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644 #endif /*_USART1 */
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647 #define DMA ((DMA_TypeDef *) DMA_BASE)
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650 #ifdef _DMA_Channel1
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651 #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
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652 #endif /*_DMA_Channel1 */
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654 #ifdef _DMA_Channel2
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655 #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
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656 #endif /*_DMA_Channel2 */
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658 #ifdef _DMA_Channel3
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659 #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
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660 #endif /*_DMA_Channel3 */
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662 #ifdef _DMA_Channel4
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663 #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
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664 #endif /*_DMA_Channel4 */
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666 #ifdef _DMA_Channel5
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667 #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
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668 #endif /*_DMA_Channel5 */
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670 #ifdef _DMA_Channel6
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671 #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
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672 #endif /*_DMA_Channel6 */
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674 #ifdef _DMA_Channel7
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675 #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
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676 #endif /*_DMA_Channel7 */
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679 #define FLASH ((FLASH_TypeDef *) FLASH_BASE)
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680 #define OB ((OB_TypeDef *) OB_BASE)
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684 #define RCC ((RCC_TypeDef *) RCC_BASE)
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688 #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
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689 #endif /*_SysTick */
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692 #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
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696 #define SCB ((SCB_TypeDef *) SCB_BASE)
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698 /*---------------------- Debug Mode -----------------------------------------*/
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701 EXT TIM_TypeDef *TIM2;
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705 EXT TIM_TypeDef *TIM3;
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709 EXT TIM_TypeDef *TIM4;
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713 EXT RTC_TypeDef *RTC;
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717 EXT WWDG_TypeDef *WWDG;
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721 EXT IWDG_TypeDef *IWDG;
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725 EXT SPI_TypeDef *SPI2;
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729 EXT USART_TypeDef *USART2;
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730 #endif /*_USART2 */
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733 EXT USART_TypeDef *USART3;
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734 #endif /*_USART3 */
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737 EXT I2C_TypeDef *I2C1;
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741 EXT I2C_TypeDef *I2C2;
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745 EXT CAN_TypeDef *CAN;
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749 EXT BKP_TypeDef *BKP;
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753 EXT PWR_TypeDef *PWR;
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757 EXT AFIO_TypeDef *AFIO;
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761 EXT EXTI_TypeDef *EXTI;
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765 EXT GPIO_TypeDef *GPIOA;
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769 EXT GPIO_TypeDef *GPIOB;
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773 EXT GPIO_TypeDef *GPIOC;
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777 EXT GPIO_TypeDef *GPIOD;
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781 EXT GPIO_TypeDef *GPIOE;
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785 EXT ADC_TypeDef *ADC1;
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789 EXT ADC_TypeDef *ADC2;
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793 EXT TIM1_TypeDef *TIM1;
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797 EXT SPI_TypeDef *SPI1;
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801 EXT USART_TypeDef *USART1;
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802 #endif /*_USART1 */
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805 EXT DMA_TypeDef *DMA;
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808 #ifdef _DMA_Channel1
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809 EXT DMA_Channel_TypeDef *DMA_Channel1;
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810 #endif /*_DMA_Channel1 */
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812 #ifdef _DMA_Channel2
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813 EXT DMA_Channel_TypeDef *DMA_Channel2;
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814 #endif /*_DMA_Channel2 */
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816 #ifdef _DMA_Channel3
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817 EXT DMA_Channel_TypeDef *DMA_Channel3;
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818 #endif /*_DMA_Channel3 */
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820 #ifdef _DMA_Channel4
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821 EXT DMA_Channel_TypeDef *DMA_Channel4;
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822 #endif /*_DMA_Channel4 */
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824 #ifdef _DMA_Channel5
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825 EXT DMA_Channel_TypeDef *DMA_Channel5;
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826 #endif /*_DMA_Channel5 */
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828 #ifdef _DMA_Channel6
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829 EXT DMA_Channel_TypeDef *DMA_Channel6;
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830 #endif /*_DMA_Channel6 */
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832 #ifdef _DMA_Channel7
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833 EXT DMA_Channel_TypeDef *DMA_Channel7;
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834 #endif /*_DMA_Channel7 */
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837 EXT FLASH_TypeDef *FLASH;
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838 EXT OB_TypeDef *OB;
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842 EXT RCC_TypeDef *RCC;
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846 EXT SysTick_TypeDef *SysTick;
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847 #endif /*_SysTick */
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850 EXT NVIC_TypeDef *NVIC;
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854 EXT SCB_TypeDef *SCB;
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859 /* Exported constants --------------------------------------------------------*/
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860 /* Exported macro ------------------------------------------------------------*/
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861 /* Exported functions ------------------------------------------------------- */
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863 #endif /* __STM32F10x_MAP_H */
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865 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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