2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* FreeRTOS includes. */
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30 #include "FreeRTOS.h"
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35 /* Library includes. */
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36 #include "stm32fxxx_eth.h"
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37 #include "stm32f10x_gpio.h"
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38 #include "stm32f10x_rcc.h"
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39 #include "stm32f10x_nvic.h"
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41 /*-----------------------------------------------------------*/
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43 /* Hardware specifics. */
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44 #define uipRCC_MAC_CLOCK ( 1UL << 14UL )
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45 #define uipRCC_MAC_TX_CLOCK ( 1UL << 15UL )
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46 #define uipRCC_MAC_RX_CLOCK ( 1UL << 16UL )
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47 #define uipPHY_ADDRESS ( 1 )
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48 #define uipENET_IRQ_NUM ( 61 )
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49 #define uipMODE_MII ( 1UL << 23UL )
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50 #define uipREMAP_MAC_IO ( 1UL << 21UL )
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52 /* The number of descriptors to chain together for use by the Rx DMA. */
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53 #define uipNUM_RX_DESCRIPTORS 4
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55 /* The total number of buffers to be available. At most (?) there should be
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56 one available for each Rx descriptor, one for current use, and one that is
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57 in the process of being transmitted. */
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58 #define uipNUM_BUFFERS ( uipNUM_RX_DESCRIPTORS + 2 )
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60 /* Each buffer is sized to fit an entire Ethernet packet. This is for
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61 simplicity and speed, but could waste RAM. */
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62 #define uipMAX_PACKET_SIZE 1520
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64 /* The field in the descriptor that is unused by this configuration is used to
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65 hold the send count. This is just #defined to a meaningful name. */
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66 #define SendCount Buffer2NextDescAddr
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68 /* If no buffers are available, then wait this long before looking again.... */
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69 #define uipBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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71 /* ...and don't look more than this many times. */
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72 #define uipBUFFER_WAIT_ATTEMPTS ( 30 )
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74 /* Let the DMA know that a new descriptor has been made available to it. */
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75 #define prvRxDescriptorAvailable() ETH_DMA->DMARPDR = 0
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77 /*-----------------------------------------------------------*/
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80 * Configure the IO for Ethernet use.
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82 static void prvSetupEthGPIO( void );
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85 * Return a pointer to an unused buffer, marking the returned buffer as now
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88 static unsigned char *prvGetNextBuffer( void );
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90 /*-----------------------------------------------------------*/
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92 /* Allocate the Rx descriptors used by the DMA. */
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93 static ETH_DMADESCTypeDef xRxDescriptors[ uipNUM_RX_DESCRIPTORS ] __attribute__((aligned(4)));
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95 /* Allocate the descriptor used for transmitting. It might be that better
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96 performance could be achieved by having more than one Tx descriptor, but
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97 in this simple case only one is used. */
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98 static volatile ETH_DMADESCTypeDef xTxDescriptor __attribute__((aligned(4)));
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100 /* Buffers used for receiving and transmitting data. */
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101 static unsigned char ucMACBuffers[ uipNUM_BUFFERS ][ uipMAX_PACKET_SIZE ] __attribute__((aligned(4)));
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103 /* Each ucBufferInUse index corresponds to a position in the same index in the
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104 ucMACBuffers array. If the index contains a 1 then the buffer withn
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105 ucMACBuffers is in use, if it contains a 0 then the buffer is free. */
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106 static unsigned char ucBufferInUse[ uipNUM_BUFFERS ] = { 0 };
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108 /* Index to the Rx descriptor to inspect next when looking for a received
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110 static unsigned long ulNextDescriptor;
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112 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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113 allocated within this file. */
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114 extern unsigned char * uip_buf;
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116 /*-----------------------------------------------------------*/
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118 portBASE_TYPE xEthInitialise( void )
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120 static ETH_InitTypeDef xEthInit; /* Static so as not to take up too much stack space. */
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121 NVIC_InitTypeDef xNVICInit;
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122 const unsigned char ucMACAddress[] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };
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123 portBASE_TYPE xReturn;
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126 /* Start with things in a safe known state. */
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128 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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130 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), DISABLE );
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133 /* Route clock to the peripheral. */
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134 RCC->AHBENR |= ( uipRCC_MAC_CLOCK | uipRCC_MAC_TX_CLOCK | uipRCC_MAC_RX_CLOCK );
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136 /* Set the MAC address. */
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137 ETH_MACAddressConfig( ETH_MAC_Address0, ( unsigned char * ) ucMACAddress );
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139 /* Use MII mode. */
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140 AFIO->MAPR &= ~( uipMODE_MII );
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142 /* Configure all the GPIO as required for MAC/PHY interfacing. */
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145 /* Reset the peripheral. */
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146 ETH_SoftwareReset();
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147 while( ETH_GetSoftwareResetStatus() == SET );
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149 /* Initialise using the whopping big structure. Code space could be saved
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150 by making this a const struct, however that would mean changes to the
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151 structure within the library header files could break the code, so for now
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152 just set everything manually at run time. */
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153 xEthInit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
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154 xEthInit.ETH_Watchdog = ETH_Watchdog_Disable;
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155 xEthInit.ETH_Jabber = ETH_Jabber_Disable;
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156 xEthInit.ETH_JumboFrame = ETH_JumboFrame_Disable;
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157 xEthInit.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
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158 xEthInit.ETH_CarrierSense = ETH_CarrierSense_Enable;
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159 xEthInit.ETH_Speed = ETH_Speed_10M;
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160 xEthInit.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;
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161 xEthInit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
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162 xEthInit.ETH_Mode = ETH_Mode_HalfDuplex;
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163 xEthInit.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
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164 xEthInit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
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165 xEthInit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
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166 xEthInit.ETH_BackOffLimit = ETH_BackOffLimit_10;
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167 xEthInit.ETH_DeferralCheck = ETH_DeferralCheck_Disable;
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168 xEthInit.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
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169 xEthInit.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
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170 xEthInit.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;
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171 xEthInit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
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172 xEthInit.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
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173 xEthInit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
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174 xEthInit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
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175 xEthInit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
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176 xEthInit.ETH_HashTableHigh = 0x0;
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177 xEthInit.ETH_HashTableLow = 0x0;
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178 xEthInit.ETH_PauseTime = 0x0;
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179 xEthInit.ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
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180 xEthInit.ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
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181 xEthInit.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
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182 xEthInit.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
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183 xEthInit.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
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184 xEthInit.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
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185 xEthInit.ETH_VLANTagIdentifier = 0x0;
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186 xEthInit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
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187 xEthInit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
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188 xEthInit.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
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189 xEthInit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
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190 xEthInit.ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
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191 xEthInit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
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192 xEthInit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
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193 xEthInit.ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
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194 xEthInit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
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195 xEthInit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
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196 xEthInit.ETH_FixedBurst = ETH_FixedBurst_Disable;
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197 xEthInit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
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198 xEthInit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
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199 xEthInit.ETH_DescriptorSkipLength = 0x0;
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200 xEthInit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
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202 xReturn = ETH_Init( &xEthInit, uipPHY_ADDRESS );
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204 /* Check a link was established. */
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205 if( xReturn != pdFAIL )
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207 /* Rx and Tx interrupts are used. */
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208 ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE );
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210 /* Only a single Tx descriptor is used. For now it is set to use an Rx
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211 buffer, but will get updated to point to where ever uip_buf is
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212 pointing prior to its use. */
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213 ETH_DMATxDescChainInit( ( void * ) &xTxDescriptor, ( void * ) ucMACBuffers, 1 );
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214 ETH_DMARxDescChainInit( xRxDescriptors, ( void * ) ucMACBuffers, uipNUM_RX_DESCRIPTORS );
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215 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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217 /* Ensure received data generates an interrupt. */
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218 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), ENABLE );
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220 /* Fix up the addresses used by the descriptors.
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221 The way ETH_DMARxDescChainInit() is not compatible with the buffer
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222 declarations in this file. */
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223 xRxDescriptors[ ul ].Buffer1Addr = ( unsigned long ) &( ucMACBuffers[ ul ][ 0 ] );
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225 /* Mark the buffer used by this descriptor as in use. */
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226 ucBufferInUse[ ul ] = pdTRUE;
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229 /* When receiving data, start at the first descriptor. */
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230 ulNextDescriptor = 0;
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232 /* Initialise uip_buf to ensure it points somewhere valid. */
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233 uip_buf = prvGetNextBuffer();
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235 /* SendCount must be initialised to 2 to ensure the Tx descriptor looks
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236 as if its available (as if it has already been sent twice. */
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237 xTxDescriptor.SendCount = 2;
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239 /* Switch on the interrupts in the NVIC. */
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240 xNVICInit.NVIC_IRQChannel = uipENET_IRQ_NUM;
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241 xNVICInit.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
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242 xNVICInit.NVIC_IRQChannelSubPriority = 0;
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243 xNVICInit.NVIC_IRQChannelCmd = ENABLE;
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244 NVIC_Init( &xNVICInit );
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246 /* Buffers and descriptors are all set up, now enable the MAC. */
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249 /* Let the DMA know there are Rx descriptors available. */
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250 prvRxDescriptorAvailable();
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255 /*-----------------------------------------------------------*/
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257 static unsigned char *prvGetNextBuffer( void )
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260 unsigned char *ucReturn = NULL;
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261 unsigned long ulAttempts = 0;
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263 while( ucReturn == NULL )
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265 /* Look through the buffers to find one that is not in use by
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267 for( x = 0; x < uipNUM_BUFFERS; x++ )
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269 if( ucBufferInUse[ x ] == pdFALSE )
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271 ucBufferInUse[ x ] = pdTRUE;
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272 ucReturn = &( ucMACBuffers[ x ][ 0 ] );
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277 /* Was a buffer found? */
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278 if( ucReturn == NULL )
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282 if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
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287 /* Wait then look again. */
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288 vTaskDelay( uipBUFFER_WAIT_DELAY );
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294 /*-----------------------------------------------------------*/
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296 unsigned short usGetMACRxData( void )
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298 unsigned short usReturn;
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300 if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_ES ) != 0 )
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302 /* Error in Rx. Discard the frame and give it back to the DMA. */
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303 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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304 prvRxDescriptorAvailable();
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306 /* No data to return. */
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309 /* Start from the next descriptor the next time this function is called. */
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310 ulNextDescriptor++;
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311 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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313 ulNextDescriptor = 0UL;
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316 else if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_OWN ) == 0 )
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318 /* Mark the current buffer as free as uip_buf is going to be set to
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319 the buffer that contains the received data. */
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320 vReturnBuffer( uip_buf );
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322 /* Get the received data length from the top 2 bytes of the Status
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323 word and the data itself. */
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324 usReturn = ( unsigned short ) ( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_FL ) >> 16UL );
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325 uip_buf = ( unsigned char * ) ( xRxDescriptors[ ulNextDescriptor ].Buffer1Addr );
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327 /* Allocate a new buffer to the descriptor. */
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328 xRxDescriptors[ ulNextDescriptor ].Buffer1Addr = ( unsigned long ) prvGetNextBuffer();
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330 /* Give the descriptor back to the DMA. */
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331 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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332 prvRxDescriptorAvailable();
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334 /* Start from the next descriptor the next time this function is called. */
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335 ulNextDescriptor++;
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336 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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338 ulNextDescriptor = 0UL;
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343 /* No received data at all. */
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349 /*-----------------------------------------------------------*/
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351 void vSendMACData( unsigned short usDataLen )
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353 unsigned long ulAttempts = 0UL;
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355 /* Check to see if the Tx descriptor is free. The check against <2 is to
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356 ensure the buffer has been sent twice and in so doing preventing a race
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357 condition with the DMA on the ETH_DMATxDesc_OWN bit. */
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358 while( ( xTxDescriptor.SendCount < 2 ) && ( xTxDescriptor.Status & ETH_DMATxDesc_OWN ) == ETH_DMATxDesc_OWN )
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360 /* Wait for the Tx descriptor to become available. */
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361 vTaskDelay( uipBUFFER_WAIT_DELAY );
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364 if( ulAttempts > uipBUFFER_WAIT_ATTEMPTS )
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366 /* Something has gone wrong as the Tx descriptor is still in use.
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367 Clear it down manually, the data it was sending will probably be
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369 xTxDescriptor.Status &= ~ETH_DMATxDesc_OWN;
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370 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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375 /* Setup the Tx descriptor for transmission. */
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376 xTxDescriptor.SendCount = 0;
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377 xTxDescriptor.Buffer1Addr = ( unsigned long ) uip_buf;
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378 xTxDescriptor.ControlBufferSize = ( unsigned long ) usDataLen;
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379 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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380 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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381 ETH_DMA->DMATPDR = 0;
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383 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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384 uip_buf = prvGetNextBuffer();
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386 /*-----------------------------------------------------------*/
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388 static void prvSetupEthGPIO( void )
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390 GPIO_InitTypeDef xEthInit;
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392 /* Remap MAC IO. */
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393 AFIO->MAPR |= ( uipREMAP_MAC_IO );
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395 /* Set PA2, PA8, PB5, PB8, PB11, PB12, PB13, PC1 and PC2 for Ethernet
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397 xEthInit.GPIO_Pin = GPIO_Pin_2;/* | GPIO_Pin_8; This should be set when the 25MHz is generated by MCO. */
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398 xEthInit.GPIO_Speed = GPIO_Speed_50MHz;
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399 xEthInit.GPIO_Mode = GPIO_Mode_AF_PP;
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400 GPIO_Init( GPIOA, &xEthInit );
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402 xEthInit.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; /*5*/
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403 GPIO_Init( GPIOB, &xEthInit );
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405 xEthInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
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406 GPIO_Init( GPIOC, &xEthInit );
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409 /* Configure PA0, PA1, PA3, PB10, PC3, PD8, PD9, PD10, PD11 and PD12 as
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411 xEthInit.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
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412 xEthInit.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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413 GPIO_Init( GPIOA, &xEthInit );
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415 xEthInit.GPIO_Pin = GPIO_Pin_10;
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416 GPIO_Init( GPIOB, &xEthInit );
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418 xEthInit.GPIO_Pin = GPIO_Pin_3;
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419 GPIO_Init( GPIOC, &xEthInit );
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421 xEthInit.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
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422 GPIO_Init( GPIOD, &xEthInit );
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424 /*-----------------------------------------------------------*/
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426 void vReturnBuffer( unsigned char *pucBuffer )
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430 /* Mark a buffer as free for use. */
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431 for( ul = 0; ul < uipNUM_BUFFERS; ul++ )
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433 if( ucMACBuffers[ ul ] == pucBuffer )
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435 ucBufferInUse[ ul ] = pdFALSE;
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440 /*-----------------------------------------------------------*/
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442 void vMAC_ISR( void )
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444 unsigned long ulStatus;
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445 extern xSemaphoreHandle xEMACSemaphore;
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446 long xHigherPriorityTaskWoken = pdFALSE;
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448 /* What caused the interrupt? */
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449 ulStatus = ETH_DMA->DMASR;
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451 /* Clear everything before leaving. */
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452 ETH_DMA->DMASR = ulStatus;
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454 if( ulStatus & ETH_DMA_IT_R )
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456 /* Data was received. Ensure the uIP task is not blocked as data has
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458 xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
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461 if( ulStatus & ETH_DMA_IT_T )
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463 /* Data was transmitted. */
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464 if( xTxDescriptor.SendCount == 0 )
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467 ( xTxDescriptor.SendCount )++;
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469 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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470 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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471 ETH_DMA->DMATPDR = 0;
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475 /* The Tx buffer is no longer required. */
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476 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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480 /* If xSemaphoreGiveFromISR() unblocked a task, and the unblocked task has
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481 a higher priority than the currently executing task, then
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482 xHigherPriorityTaskWoken will have been set to pdTRUE and this ISR should
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483 return directly to the higher priority unblocked task. */
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484 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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