git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h

   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32l1xx_tim.h\r
   4   * @author  MCD Application Team\r
   5   * @version V1.1.1\r
   6   * @date    05-March-2012\r
   7   * @brief   This file contains all the functions prototypes for the TIM firmware \r
   8   *          library.\r
   9   ******************************************************************************\r
  10   * @attention\r
  11   *\r
  12   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>\r
  13   *\r
  14   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
  15   * You may not use this file except in compliance with the License.\r
  16   * You may obtain a copy of the License at:\r
  17   *\r
  18   *        http://www.st.com/software_license_agreement_liberty_v2\r
  19   *\r
  20   * Unless required by applicable law or agreed to in writing, software \r
  21   * distributed under the License is distributed on an "AS IS" BASIS, \r
  22   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
  23   * See the License for the specific language governing permissions and\r
  24   * limitations under the License.\r
  25   *\r
  26   ******************************************************************************\r
  27   */\r
  28 \r
  29 /* Define to prevent recursive inclusion -------------------------------------*/\r
  30 #ifndef __STM32L1xx_TIM_H\r
  31 #define __STM32L1xx_TIM_H\r
  32 \r
  33 #ifdef __cplusplus\r
  34  extern "C" {\r
  35 #endif\r
  36 \r
  37 /* Includes ------------------------------------------------------------------*/\r
  38 #include "stm32l1xx.h"\r
  39 \r
  40 /** @addtogroup STM32L1xx_StdPeriph_Driver\r
  41   * @{\r
  42   */\r
  43 \r
  44 /** @addtogroup TIM\r
  45   * @{\r
  46   */ \r
  47 \r
  48 /* Exported types ------------------------------------------------------------*/\r
  49 \r
  50 /** \r
  51   * @brief  TIM Time Base Init structure definition\r
  52   * @note   This structure is used with all TIMx except for TIM6 and TIM7.    \r
  53   */\r
  54 \r
  55 typedef struct\r
  56 {\r
  57   uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r
  58                                        This parameter can be a number between 0x0000 and 0xFFFF */\r
  59 \r
  60   uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.\r
  61                                        This parameter can be a value of @ref TIM_Counter_Mode */\r
  62 \r
  63   uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active\r
  64                                        Auto-Reload Register at the next update event.\r
  65                                        This parameter must be a number between 0x0000 and 0xFFFF.  */ \r
  66 \r
  67   uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.\r
  68                                       This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
  69 \r
  70 } TIM_TimeBaseInitTypeDef;       \r
  71 \r
  72 /** \r
  73   * @brief  TIM Output Compare Init structure definition  \r
  74   */\r
  75 \r
  76 typedef struct\r
  77 {\r
  78   uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.\r
  79                                    This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
  80 \r
  81   uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.\r
  82                                    This parameter can be a value of @ref TIM_Output_Compare_state */\r
  83 \r
  84   uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
  85                                    This parameter can be a number between 0x0000 and 0xFFFF */\r
  86 \r
  87   uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.\r
  88                                    This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
  89 \r
  90 } TIM_OCInitTypeDef;\r
  91 \r
  92 /** \r
  93   * @brief  TIM Input Capture Init structure definition  \r
  94   */\r
  95 \r
  96 typedef struct\r
  97 {\r
  98 \r
  99   uint16_t TIM_Channel;      /*!< Specifies the TIM channel.\r
 100                                   This parameter can be a value of @ref TIM_Channel */\r
 101 \r
 102   uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.\r
 103                                   This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
 104 \r
 105   uint16_t TIM_ICSelection;  /*!< Specifies the input.\r
 106                                   This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
 107 \r
 108   uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r
 109                                   This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
 110 \r
 111   uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.\r
 112                                   This parameter can be a number between 0x0 and 0xF */\r
 113 } TIM_ICInitTypeDef;\r
 114 \r
 115 /* Exported constants --------------------------------------------------------*/\r
 116 \r
 117   \r
 118 /** @defgroup TIM_Exported_constants \r
 119   * @{\r
 120   */\r
 121 \r
 122 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 123                                    ((PERIPH) == TIM3) || \\r
 124                                    ((PERIPH) == TIM4) || \\r
 125                                    ((PERIPH) == TIM5) || \\r
 126                                    ((PERIPH) == TIM6) || \\r
 127                                    ((PERIPH) == TIM7) || \\r
 128                                    ((PERIPH) == TIM9) || \\r
 129                                    ((PERIPH) == TIM10) || \\r
 130                                    ((PERIPH) == TIM11))\r
 131 \r
 132 /* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */\r
 133 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 134                                      ((PERIPH) == TIM3) || \\r
 135                                      ((PERIPH) == TIM4) || \\r
 136                                      ((PERIPH) == TIM5) || \\r
 137                                      ((PERIPH) == TIM9) || \\r
 138                                      ((PERIPH) == TIM10) || \\r
 139                                      ((PERIPH) == TIM11))\r
 140 \r
 141 /* LIST3: TIM2, TIM3, TIM4 and TIM5 */\r
 142 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 143                                      ((PERIPH) == TIM3) || \\r
 144                                      ((PERIPH) == TIM4) || \\r
 145                                      ((PERIPH) == TIM5))\r
 146 \r
 147 /* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */\r
 148 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 149                                      ((PERIPH) == TIM3) || \\r
 150                                      ((PERIPH) == TIM4) || \\r
 151                                      ((PERIPH) == TIM5) || \\r
 152                                      ((PERIPH) == TIM9))\r
 153 \r
 154 /* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */\r
 155 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 156                                      ((PERIPH) == TIM3) || \\r
 157                                      ((PERIPH) == TIM4) || \\r
 158                                      ((PERIPH) == TIM5) ||\\r
 159                                      ((PERIPH) == TIM6) || \\r
 160                                      ((PERIPH) == TIM7) ||\\r
 161                                      ((PERIPH) == TIM9))\r
 162 \r
 163 /* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */\r
 164 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 165                                      ((PERIPH) == TIM3) || \\r
 166                                      ((PERIPH) == TIM4) || \\r
 167                                      ((PERIPH) == TIM5) ||\\r
 168                                      ((PERIPH) == TIM6) || \\r
 169                                      ((PERIPH) == TIM7))\r
 170 \r
 171 /* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */\r
 172 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
 173                                      ((PERIPH) == TIM3) || \\r
 174                                      ((PERIPH) == TIM9) || \\r
 175                                      ((PERIPH) == TIM10) || \\r
 176                                      ((PERIPH) == TIM11))\r
 177 \r
 178 \r
 179 \r
 180 /** @defgroup TIM_Output_Compare_and_PWM_modes \r
 181   * @{\r
 182   */\r
 183 \r
 184 #define TIM_OCMode_Timing                  ((uint16_t)0x0000)\r
 185 #define TIM_OCMode_Active                  ((uint16_t)0x0010)\r
 186 #define TIM_OCMode_Inactive                ((uint16_t)0x0020)\r
 187 #define TIM_OCMode_Toggle                  ((uint16_t)0x0030)\r
 188 #define TIM_OCMode_PWM1                    ((uint16_t)0x0060)\r
 189 #define TIM_OCMode_PWM2                    ((uint16_t)0x0070)\r
 190 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
 191                               ((MODE) == TIM_OCMode_Active) || \\r
 192                               ((MODE) == TIM_OCMode_Inactive) || \\r
 193                               ((MODE) == TIM_OCMode_Toggle)|| \\r
 194                               ((MODE) == TIM_OCMode_PWM1) || \\r
 195                               ((MODE) == TIM_OCMode_PWM2))\r
 196 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
 197                           ((MODE) == TIM_OCMode_Active) || \\r
 198                           ((MODE) == TIM_OCMode_Inactive) || \\r
 199                           ((MODE) == TIM_OCMode_Toggle)|| \\r
 200                           ((MODE) == TIM_OCMode_PWM1) || \\r
 201                           ((MODE) == TIM_OCMode_PWM2) ||        \\r
 202                           ((MODE) == TIM_ForcedAction_Active) || \\r
 203                           ((MODE) == TIM_ForcedAction_InActive))\r
 204 /**\r
 205   * @}\r
 206   */\r
 207 \r
 208 /** @defgroup TIM_One_Pulse_Mode \r
 209   * @{\r
 210   */\r
 211 \r
 212 #define TIM_OPMode_Single                  ((uint16_t)0x0008)\r
 213 #define TIM_OPMode_Repetitive              ((uint16_t)0x0000)\r
 214 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
 215                                ((MODE) == TIM_OPMode_Repetitive))\r
 216 /**\r
 217   * @}\r
 218   */ \r
 219 \r
 220 /** @defgroup TIM_Channel \r
 221   * @{\r
 222   */\r
 223 \r
 224 #define TIM_Channel_1                      ((uint16_t)0x0000)\r
 225 #define TIM_Channel_2                      ((uint16_t)0x0004)\r
 226 #define TIM_Channel_3                      ((uint16_t)0x0008)\r
 227 #define TIM_Channel_4                      ((uint16_t)0x000C)\r
 228 \r
 229 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
 230                                  ((CHANNEL) == TIM_Channel_2) || \\r
 231                                  ((CHANNEL) == TIM_Channel_3) || \\r
 232                                  ((CHANNEL) == TIM_Channel_4))\r
 233                                  \r
 234 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
 235                                       ((CHANNEL) == TIM_Channel_2))\r
 236 \r
 237 /**\r
 238   * @}\r
 239   */ \r
 240 \r
 241 /** @defgroup TIM_Clock_Division_CKD \r
 242   * @{\r
 243   */\r
 244 \r
 245 #define TIM_CKD_DIV1                       ((uint16_t)0x0000)\r
 246 #define TIM_CKD_DIV2                       ((uint16_t)0x0100)\r
 247 #define TIM_CKD_DIV4                       ((uint16_t)0x0200)\r
 248 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
 249                              ((DIV) == TIM_CKD_DIV2) || \\r
 250                              ((DIV) == TIM_CKD_DIV4))\r
 251 /**\r
 252   * @}\r
 253   */\r
 254 \r
 255 /** @defgroup TIM_Counter_Mode \r
 256   * @{\r
 257   */\r
 258 \r
 259 #define TIM_CounterMode_Up                 ((uint16_t)0x0000)\r
 260 #define TIM_CounterMode_Down               ((uint16_t)0x0010)\r
 261 #define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)\r
 262 #define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)\r
 263 #define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)\r
 264 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \\r
 265                                    ((MODE) == TIM_CounterMode_Down) || \\r
 266                                    ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
 267                                    ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
 268                                    ((MODE) == TIM_CounterMode_CenterAligned3))\r
 269 /**\r
 270   * @}\r
 271   */ \r
 272 \r
 273 /** @defgroup TIM_Output_Compare_Polarity \r
 274   * @{\r
 275   */\r
 276 \r
 277 #define TIM_OCPolarity_High                ((uint16_t)0x0000)\r
 278 #define TIM_OCPolarity_Low                 ((uint16_t)0x0002)\r
 279 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
 280                                       ((POLARITY) == TIM_OCPolarity_Low))\r
 281 /**\r
 282   * @}\r
 283   */\r
 284 \r
 285 \r
 286 /** @defgroup TIM_Output_Compare_state\r
 287   * @{\r
 288   */\r
 289 \r
 290 #define TIM_OutputState_Disable            ((uint16_t)0x0000)\r
 291 #define TIM_OutputState_Enable             ((uint16_t)0x0001)\r
 292 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
 293                                     ((STATE) == TIM_OutputState_Enable))\r
 294 /**\r
 295   * @}\r
 296   */ \r
 297 \r
 298 \r
 299 /** @defgroup TIM_Capture_Compare_state \r
 300   * @{\r
 301   */\r
 302 \r
 303 #define TIM_CCx_Enable                      ((uint16_t)0x0001)\r
 304 #define TIM_CCx_Disable                     ((uint16_t)0x0000)\r
 305 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
 306                          ((CCX) == TIM_CCx_Disable))\r
 307 /**\r
 308   * @}\r
 309   */ \r
 310 \r
 311 /** @defgroup TIM_Input_Capture_Polarity \r
 312   * @{\r
 313   */\r
 314 \r
 315 #define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)\r
 316 #define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)\r
 317 #define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)\r
 318 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
 319                                       ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
 320                                       ((POLARITY) == TIM_ICPolarity_BothEdge))\r
 321 /**\r
 322   * @}\r
 323   */ \r
 324 \r
 325 /** @defgroup TIM_Input_Capture_Selection \r
 326   * @{\r
 327   */\r
 328 \r
 329 #define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
 330                                                                    connected to IC1, IC2, IC3 or IC4, respectively */\r
 331 #define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
 332                                                                    connected to IC2, IC1, IC4 or IC3, respectively. */\r
 333 #define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
 334 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
 335                                         ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
 336                                         ((SELECTION) == TIM_ICSelection_TRC))\r
 337 /**\r
 338   * @}\r
 339   */ \r
 340 \r
 341 /** @defgroup TIM_Input_Capture_Prescaler \r
 342   * @{\r
 343   */\r
 344 \r
 345 #define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
 346 #define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
 347 #define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
 348 #define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
 349 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
 350                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
 351                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
 352                                         ((PRESCALER) == TIM_ICPSC_DIV8))\r
 353 /**\r
 354   * @}\r
 355   */ \r
 356 \r
 357 /** @defgroup TIM_interrupt_sources \r
 358   * @{\r
 359   */\r
 360 \r
 361 #define TIM_IT_Update                      ((uint16_t)0x0001)\r
 362 #define TIM_IT_CC1                         ((uint16_t)0x0002)\r
 363 #define TIM_IT_CC2                         ((uint16_t)0x0004)\r
 364 #define TIM_IT_CC3                         ((uint16_t)0x0008)\r
 365 #define TIM_IT_CC4                         ((uint16_t)0x0010)\r
 366 #define TIM_IT_Trigger                     ((uint16_t)0x0040)\r
 367 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
 368 \r
 369 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
 370                            ((IT) == TIM_IT_CC1) || \\r
 371                            ((IT) == TIM_IT_CC2) || \\r
 372                            ((IT) == TIM_IT_CC3) || \\r
 373                            ((IT) == TIM_IT_CC4) || \\r
 374                            ((IT) == TIM_IT_Trigger))\r
 375 /**\r
 376   * @}\r
 377   */ \r
 378 \r
 379 /** @defgroup TIM_DMA_Base_address \r
 380   * @{\r
 381   */\r
 382 \r
 383 #define TIM_DMABase_CR1                    ((uint16_t)0x0000)\r
 384 #define TIM_DMABase_CR2                    ((uint16_t)0x0001)\r
 385 #define TIM_DMABase_SMCR                   ((uint16_t)0x0002)\r
 386 #define TIM_DMABase_DIER                   ((uint16_t)0x0003)\r
 387 #define TIM_DMABase_SR                     ((uint16_t)0x0004)\r
 388 #define TIM_DMABase_EGR                    ((uint16_t)0x0005)\r
 389 #define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)\r
 390 #define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)\r
 391 #define TIM_DMABase_CCER                   ((uint16_t)0x0008)\r
 392 #define TIM_DMABase_CNT                    ((uint16_t)0x0009)\r
 393 #define TIM_DMABase_PSC                    ((uint16_t)0x000A)\r
 394 #define TIM_DMABase_ARR                    ((uint16_t)0x000B)\r
 395 #define TIM_DMABase_CCR1                   ((uint16_t)0x000D)\r
 396 #define TIM_DMABase_CCR2                   ((uint16_t)0x000E)\r
 397 #define TIM_DMABase_CCR3                   ((uint16_t)0x000F)\r
 398 #define TIM_DMABase_CCR4                   ((uint16_t)0x0010)\r
 399 #define TIM_DMABase_DCR                    ((uint16_t)0x0012)\r
 400 #define TIM_DMABase_OR                     ((uint16_t)0x0013)\r
 401 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
 402                                ((BASE) == TIM_DMABase_CR2) || \\r
 403                                ((BASE) == TIM_DMABase_SMCR) || \\r
 404                                ((BASE) == TIM_DMABase_DIER) || \\r
 405                                ((BASE) == TIM_DMABase_SR) || \\r
 406                                ((BASE) == TIM_DMABase_EGR) || \\r
 407                                ((BASE) == TIM_DMABase_CCMR1) || \\r
 408                                ((BASE) == TIM_DMABase_CCMR2) || \\r
 409                                ((BASE) == TIM_DMABase_CCER) || \\r
 410                                ((BASE) == TIM_DMABase_CNT) || \\r
 411                                ((BASE) == TIM_DMABase_PSC) || \\r
 412                                ((BASE) == TIM_DMABase_ARR) || \\r
 413                                ((BASE) == TIM_DMABase_CCR1) || \\r
 414                                ((BASE) == TIM_DMABase_CCR2) || \\r
 415                                ((BASE) == TIM_DMABase_CCR3) || \\r
 416                                ((BASE) == TIM_DMABase_CCR4) || \\r
 417                                ((BASE) == TIM_DMABase_DCR) || \\r
 418                                ((BASE) == TIM_DMABase_OR))\r
 419 /**\r
 420   * @}\r
 421   */ \r
 422 \r
 423 /** @defgroup TIM_DMA_Burst_Length \r
 424   * @{\r
 425   */\r
 426 \r
 427 #define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)\r
 428 #define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)\r
 429 #define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)\r
 430 #define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)\r
 431 #define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)\r
 432 #define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)\r
 433 #define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)\r
 434 #define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)\r
 435 #define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)\r
 436 #define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)\r
 437 #define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)\r
 438 #define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)\r
 439 #define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)\r
 440 #define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)\r
 441 #define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)\r
 442 #define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)\r
 443 #define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)\r
 444 #define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)\r
 445 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \\r
 446                                    ((LENGTH) == TIM_DMABurstLength_2Transfers) || \\r
 447                                    ((LENGTH) == TIM_DMABurstLength_3Transfers) || \\r
 448                                    ((LENGTH) == TIM_DMABurstLength_4Transfers) || \\r
 449                                    ((LENGTH) == TIM_DMABurstLength_5Transfers) || \\r
 450                                    ((LENGTH) == TIM_DMABurstLength_6Transfers) || \\r
 451                                    ((LENGTH) == TIM_DMABurstLength_7Transfers) || \\r
 452                                    ((LENGTH) == TIM_DMABurstLength_8Transfers) || \\r
 453                                    ((LENGTH) == TIM_DMABurstLength_9Transfers) || \\r
 454                                    ((LENGTH) == TIM_DMABurstLength_10Transfers) || \\r
 455                                    ((LENGTH) == TIM_DMABurstLength_11Transfers) || \\r
 456                                    ((LENGTH) == TIM_DMABurstLength_12Transfers) || \\r
 457                                    ((LENGTH) == TIM_DMABurstLength_13Transfers) || \\r
 458                                    ((LENGTH) == TIM_DMABurstLength_14Transfers) || \\r
 459                                    ((LENGTH) == TIM_DMABurstLength_15Transfers) || \\r
 460                                    ((LENGTH) == TIM_DMABurstLength_16Transfers) || \\r
 461                                    ((LENGTH) == TIM_DMABurstLength_17Transfers) || \\r
 462                                    ((LENGTH) == TIM_DMABurstLength_18Transfers))\r
 463 /**\r
 464   * @}\r
 465   */ \r
 466 \r
 467 /** @defgroup TIM_DMA_sources \r
 468   * @{\r
 469   */\r
 470 \r
 471 #define TIM_DMA_Update                     ((uint16_t)0x0100)\r
 472 #define TIM_DMA_CC1                        ((uint16_t)0x0200)\r
 473 #define TIM_DMA_CC2                        ((uint16_t)0x0400)\r
 474 #define TIM_DMA_CC3                        ((uint16_t)0x0800)\r
 475 #define TIM_DMA_CC4                        ((uint16_t)0x1000)\r
 476 #define TIM_DMA_Trigger                    ((uint16_t)0x4000)\r
 477 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
 478 \r
 479 /**\r
 480   * @}\r
 481   */ \r
 482 \r
 483 /** @defgroup TIM_External_Trigger_Prescaler \r
 484   * @{\r
 485   */\r
 486 \r
 487 #define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)\r
 488 #define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)\r
 489 #define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)\r
 490 #define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)\r
 491 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
 492                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
 493                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
 494                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
 495 /**\r
 496   * @}\r
 497   */ \r
 498 \r
 499 /** @defgroup TIM_Internal_Trigger_Selection \r
 500   * @{\r
 501   */\r
 502 \r
 503 #define TIM_TS_ITR0                        ((uint16_t)0x0000)\r
 504 #define TIM_TS_ITR1                        ((uint16_t)0x0010)\r
 505 #define TIM_TS_ITR2                        ((uint16_t)0x0020)\r
 506 #define TIM_TS_ITR3                        ((uint16_t)0x0030)\r
 507 #define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)\r
 508 #define TIM_TS_TI1FP1                      ((uint16_t)0x0050)\r
 509 #define TIM_TS_TI2FP2                      ((uint16_t)0x0060)\r
 510 #define TIM_TS_ETRF                        ((uint16_t)0x0070)\r
 511 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
 512                                              ((SELECTION) == TIM_TS_ITR1) || \\r
 513                                              ((SELECTION) == TIM_TS_ITR2) || \\r
 514                                              ((SELECTION) == TIM_TS_ITR3) || \\r
 515                                              ((SELECTION) == TIM_TS_TI1F_ED) || \\r
 516                                              ((SELECTION) == TIM_TS_TI1FP1) || \\r
 517                                              ((SELECTION) == TIM_TS_TI2FP2) || \\r
 518                                              ((SELECTION) == TIM_TS_ETRF))\r
 519 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
 520                                                       ((SELECTION) == TIM_TS_ITR1) || \\r
 521                                                       ((SELECTION) == TIM_TS_ITR2) || \\r
 522                                                       ((SELECTION) == TIM_TS_ITR3))\r
 523 /**\r
 524   * @}\r
 525   */ \r
 526 \r
 527 /** @defgroup TIM_TIx_External_Clock_Source \r
 528   * @{\r
 529   */\r
 530 \r
 531 #define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)\r
 532 #define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)\r
 533 #define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)\r
 534 \r
 535 /**\r
 536   * @}\r
 537   */ \r
 538 \r
 539 /** @defgroup TIM_External_Trigger_Polarity \r
 540   * @{\r
 541   */ \r
 542 #define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)\r
 543 #define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)\r
 544 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
 545                                        ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
 546 /**\r
 547   * @}\r
 548   */\r
 549 \r
 550 /** @defgroup TIM_Prescaler_Reload_Mode \r
 551   * @{\r
 552   */\r
 553 \r
 554 #define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)\r
 555 #define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)\r
 556 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
 557                                          ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
 558 /**\r
 559   * @}\r
 560   */ \r
 561 \r
 562 /** @defgroup TIM_Forced_Action \r
 563   * @{\r
 564   */\r
 565 \r
 566 #define TIM_ForcedAction_Active            ((uint16_t)0x0050)\r
 567 #define TIM_ForcedAction_InActive          ((uint16_t)0x0040)\r
 568 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
 569                                       ((ACTION) == TIM_ForcedAction_InActive))\r
 570 /**\r
 571   * @}\r
 572   */ \r
 573 \r
 574 /** @defgroup TIM_Encoder_Mode \r
 575   * @{\r
 576   */\r
 577 \r
 578 #define TIM_EncoderMode_TI1                ((uint16_t)0x0001)\r
 579 #define TIM_EncoderMode_TI2                ((uint16_t)0x0002)\r
 580 #define TIM_EncoderMode_TI12               ((uint16_t)0x0003)\r
 581 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
 582                                    ((MODE) == TIM_EncoderMode_TI2) || \\r
 583                                    ((MODE) == TIM_EncoderMode_TI12))\r
 584 /**\r
 585   * @}\r
 586   */ \r
 587 \r
 588 \r
 589 /** @defgroup TIM_Event_Source \r
 590   * @{\r
 591   */\r
 592 \r
 593 #define TIM_EventSource_Update             ((uint16_t)0x0001)\r
 594 #define TIM_EventSource_CC1                ((uint16_t)0x0002)\r
 595 #define TIM_EventSource_CC2                ((uint16_t)0x0004)\r
 596 #define TIM_EventSource_CC3                ((uint16_t)0x0008)\r
 597 #define TIM_EventSource_CC4                ((uint16_t)0x0010)\r
 598 #define TIM_EventSource_Trigger            ((uint16_t)0x0040)\r
 599 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))                                          \r
 600    \r
 601 /**\r
 602   * @}\r
 603   */ \r
 604 \r
 605 /** @defgroup TIM_Update_Source \r
 606   * @{\r
 607   */\r
 608 \r
 609 #define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
 610                                                                    or the setting of UG bit, or an update generation\r
 611                                                                    through the slave mode controller. */\r
 612 #define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
 613 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
 614                                       ((SOURCE) == TIM_UpdateSource_Regular))\r
 615 /**\r
 616   * @}\r
 617   */ \r
 618 \r
 619 /** @defgroup TIM_Output_Compare_Preload_State \r
 620   * @{\r
 621   */\r
 622 \r
 623 #define TIM_OCPreload_Enable               ((uint16_t)0x0008)\r
 624 #define TIM_OCPreload_Disable              ((uint16_t)0x0000)\r
 625 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
 626                                        ((STATE) == TIM_OCPreload_Disable))\r
 627 /**\r
 628   * @}\r
 629   */ \r
 630 \r
 631 /** @defgroup TIM_Output_Compare_Fast_State \r
 632   * @{\r
 633   */\r
 634 \r
 635 #define TIM_OCFast_Enable                  ((uint16_t)0x0004)\r
 636 #define TIM_OCFast_Disable                 ((uint16_t)0x0000)\r
 637 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
 638                                     ((STATE) == TIM_OCFast_Disable))\r
 639                                      \r
 640 /**\r
 641   * @}\r
 642   */ \r
 643 \r
 644 /** @defgroup TIM_Output_Compare_Clear_State \r
 645   * @{\r
 646   */\r
 647 \r
 648 #define TIM_OCClear_Enable                 ((uint16_t)0x0080)\r
 649 #define TIM_OCClear_Disable                ((uint16_t)0x0000)\r
 650 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
 651                                      ((STATE) == TIM_OCClear_Disable))\r
 652 /**\r
 653   * @}\r
 654   */ \r
 655 \r
 656 /** @defgroup TIM_Trigger_Output_Source \r
 657   * @{\r
 658   */\r
 659 \r
 660 #define TIM_TRGOSource_Reset               ((uint16_t)0x0000)\r
 661 #define TIM_TRGOSource_Enable              ((uint16_t)0x0010)\r
 662 #define TIM_TRGOSource_Update              ((uint16_t)0x0020)\r
 663 #define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)\r
 664 #define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)\r
 665 #define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)\r
 666 #define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)\r
 667 #define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)\r
 668 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
 669                                     ((SOURCE) == TIM_TRGOSource_Enable) || \\r
 670                                     ((SOURCE) == TIM_TRGOSource_Update) || \\r
 671                                     ((SOURCE) == TIM_TRGOSource_OC1) || \\r
 672                                     ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
 673                                     ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
 674                                     ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
 675                                     ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
 676 /**\r
 677   * @}\r
 678   */ \r
 679 \r
 680 /** @defgroup TIM_Slave_Mode \r
 681   * @{\r
 682   */\r
 683 \r
 684 #define TIM_SlaveMode_Reset                ((uint16_t)0x0004)\r
 685 #define TIM_SlaveMode_Gated                ((uint16_t)0x0005)\r
 686 #define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)\r
 687 #define TIM_SlaveMode_External1            ((uint16_t)0x0007)\r
 688 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
 689                                  ((MODE) == TIM_SlaveMode_Gated) || \\r
 690                                  ((MODE) == TIM_SlaveMode_Trigger) || \\r
 691                                  ((MODE) == TIM_SlaveMode_External1))\r
 692 /**\r
 693   * @}\r
 694   */ \r
 695 \r
 696 /** @defgroup TIM_Master_Slave_Mode \r
 697   * @{\r
 698   */\r
 699 \r
 700 #define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)\r
 701 #define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)\r
 702 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
 703                                  ((STATE) == TIM_MasterSlaveMode_Disable))\r
 704 /**\r
 705   * @}\r
 706   */ \r
 707   \r
 708 /** @defgroup TIM_Flags \r
 709   * @{\r
 710   */\r
 711 \r
 712 #define TIM_FLAG_Update                    ((uint16_t)0x0001)\r
 713 #define TIM_FLAG_CC1                       ((uint16_t)0x0002)\r
 714 #define TIM_FLAG_CC2                       ((uint16_t)0x0004)\r
 715 #define TIM_FLAG_CC3                       ((uint16_t)0x0008)\r
 716 #define TIM_FLAG_CC4                       ((uint16_t)0x0010)\r
 717 #define TIM_FLAG_Trigger                   ((uint16_t)0x0040)\r
 718 #define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)\r
 719 #define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)\r
 720 #define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)\r
 721 #define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)\r
 722 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
 723                                ((FLAG) == TIM_FLAG_CC1) || \\r
 724                                ((FLAG) == TIM_FLAG_CC2) || \\r
 725                                ((FLAG) == TIM_FLAG_CC3) || \\r
 726                                ((FLAG) == TIM_FLAG_CC4) || \\r
 727                                ((FLAG) == TIM_FLAG_Trigger) || \\r
 728                                ((FLAG) == TIM_FLAG_CC1OF) || \\r
 729                                ((FLAG) == TIM_FLAG_CC2OF) || \\r
 730                                ((FLAG) == TIM_FLAG_CC3OF) || \\r
 731                                ((FLAG) == TIM_FLAG_CC4OF))\r
 732 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
 733 \r
 734 /**\r
 735   * @}\r
 736   */ \r
 737 \r
 738 /** @defgroup TIM_Input_Capture_Filer_Value \r
 739   * @{\r
 740   */\r
 741 \r
 742 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
 743 /**\r
 744   * @}\r
 745   */ \r
 746 \r
 747 /** @defgroup TIM_External_Trigger_Filter \r
 748   * @{\r
 749   */\r
 750 \r
 751 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
 752 /**\r
 753   * @}\r
 754   */\r
 755 \r
 756 /** @defgroup TIM_OCReferenceClear \r
 757   * @{\r
 758   */\r
 759 #define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)\r
 760 #define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)\r
 761 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
 762                                               ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
 763 \r
 764 /**\r
 765   * @}\r
 766   */\r
 767 \r
 768 /** @defgroup TIM_Remap \r
 769   * @{\r
 770   */\r
 771 \r
 772 #define TIM2_TIM10_OC                      ((uint32_t)0xFFFE0000)\r
 773 #define TIM2_TIM5_TRGO                     ((uint32_t)0xFFFE0001)\r
 774 \r
 775 #define TIM3_TIM11_OC                      ((uint32_t)0xFFFE0000)\r
 776 #define TIM3_TIM5_TRGO                     ((uint32_t)0xFFFE0001)\r
 777 \r
 778 #define TIM9_GPIO                          ((uint32_t)0xFFFC0000)\r
 779 #define TIM9_LSE                           ((uint32_t)0xFFFC0001)\r
 780 \r
 781 #define TIM9_TIM3_TRGO                     ((uint32_t)0xFFFB0000)\r
 782 #define TIM9_TS_IO                         ((uint32_t)0xFFFB0004)\r
 783 \r
 784 #define TIM10_GPIO                         ((uint32_t)0xFFF40000)\r
 785 #define TIM10_LSI                          ((uint32_t)0xFFF40001)\r
 786 #define TIM10_LSE                          ((uint32_t)0xFFF40002)\r
 787 #define TIM10_RTC                          ((uint32_t)0xFFF40003)\r
 788 #define TIM10_RI                           ((uint32_t)0xFFF40008)\r
 789 \r
 790 #define TIM10_ETR_LSE                      ((uint32_t)0xFFFB0000)\r
 791 #define TIM10_ETR_TIM9_TRGO                ((uint32_t)0xFFFB0004)\r
 792 \r
 793 #define TIM11_GPIO                         ((uint32_t)0xFFF40000)\r
 794 #define TIM11_MSI                          ((uint32_t)0xFFF40001)\r
 795 #define TIM11_HSE_RTC                      ((uint32_t)0xFFF40002)\r
 796 #define TIM11_RI                           ((uint32_t)0xFFF40008)\r
 797 \r
 798 #define TIM11_ETR_LSE                      ((uint32_t)0xFFFB0000)\r
 799 #define TIM11_ETR_TIM9_TRGO                ((uint32_t)0xFFFB0004)\r
 800 \r
 801 #define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM2_TIM10_OC)|| \\r
 802                                   ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \\r
 803                                   ((TIM_REMAP) == TIM3_TIM11_OC)|| \\r
 804                                   ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \\r
 805                                   ((TIM_REMAP) == TIM9_GPIO)|| \\r
 806                                   ((TIM_REMAP) == TIM9_LSE)|| \\r
 807                                   ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \\r
 808                                   ((TIM_REMAP) == TIM9_TS_IO)|| \\r
 809                                   ((TIM_REMAP) == TIM10_GPIO)|| \\r
 810                                   ((TIM_REMAP) == TIM10_LSI)|| \\r
 811                                   ((TIM_REMAP) == TIM10_LSE)|| \\r
 812                                   ((TIM_REMAP) == TIM10_RTC)|| \\r
 813                                   ((TIM_REMAP) == TIM10_RI)|| \\r
 814                                   ((TIM_REMAP) == TIM10_ETR_LSE)|| \\r
 815                                   ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \\r
 816                                   ((TIM_REMAP) == TIM11_GPIO)|| \\r
 817                                   ((TIM_REMAP) == TIM11_MSI)|| \\r
 818                                   ((TIM_REMAP) == TIM11_HSE_RTC)|| \\r
 819                                   ((TIM_REMAP) == TIM11_RI)|| \\r
 820                                   ((TIM_REMAP) == TIM11_ETR_LSE)|| \\r
 821                                   ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))\r
 822 \r
 823 /**\r
 824   * @}\r
 825   */\r
 826 \r
 827 /** @defgroup TIM_Legacy \r
 828   * @{\r
 829   */\r
 830 \r
 831 #define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer\r
 832 #define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers\r
 833 #define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers\r
 834 #define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers\r
 835 #define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers\r
 836 #define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers\r
 837 #define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers\r
 838 #define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers\r
 839 #define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers\r
 840 #define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers\r
 841 #define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers\r
 842 #define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers\r
 843 #define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers\r
 844 #define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers\r
 845 #define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers\r
 846 #define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers\r
 847 #define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers\r
 848 #define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers\r
 849 /**\r
 850   * @}\r
 851   */\r
 852 \r
 853 /**\r
 854   * @}\r
 855   */\r
 856   \r
 857 /* Exported macro ------------------------------------------------------------*/\r
 858 /* Exported functions ------------------------------------------------------- */ \r
 859 \r
 860 /* TimeBase management ********************************************************/\r
 861 void TIM_DeInit(TIM_TypeDef* TIMx);\r
 862 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
 863 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
 864 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
 865 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
 866 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
 867 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
 868 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
 869 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
 870 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
 871 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
 872 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
 873 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
 874 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
 875 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
 876 \r
 877 /* Output Compare management **************************************************/\r
 878 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
 879 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
 880 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
 881 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
 882 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
 883 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
 884 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
 885 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
 886 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
 887 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
 888 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
 889 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
 890 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
 891 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
 892 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
 893 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
 894 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
 895 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
 896 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
 897 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
 898 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
 899 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
 900 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
 901 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
 902 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
 903 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
 904 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
 905 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
 906 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
 907 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
 908 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
 909 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
 910 \r
 911 /* Input Capture management ***************************************************/\r
 912 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
 913 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
 914 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
 915 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
 916 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
 917 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
 918 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
 919 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
 920 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
 921 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
 922 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
 923 \r
 924 /* Interrupts, DMA and flags management ***************************************/\r
 925 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
 926 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
 927 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
 928 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
 929 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
 930 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
 931 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
 932 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
 933 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
 934 \r
 935 /* Clocks management **********************************************************/\r
 936 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
 937 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
 938 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
 939                                 uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
 940 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
 941                              uint16_t ExtTRGFilter);\r
 942 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
 943                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
 944 \r
 945 \r
 946 /* Synchronization management *************************************************/\r
 947 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
 948 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
 949 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
 950 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
 951 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
 952                    uint16_t ExtTRGFilter);\r
 953 \r
 954 /* Specific interface management **********************************************/                   \r
 955 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
 956                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
 957 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
 958 \r
 959 /* Specific remapping management **********************************************/\r
 960 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);\r
 961 \r
 962 \r
 963 #ifdef __cplusplus\r
 964 }\r
 965 #endif\r
 966 \r
 967 #endif /*__STM32L1xx_TIM_H */\r
 968 \r
 969 /**\r
 970   * @}\r
 971   */ \r
 972 \r
 973 /**\r
 974   * @}\r
 975   */\r
 976 \r
 977 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r