2 ******************************************************************************
\r
4 * @author MCD Application Team
\r
6 * @date 05-March-2012
\r
7 * @brief This file provides all the miscellaneous firmware functions (add-on
\r
8 * to CMSIS functions).
\r
9 ******************************************************************************
\r
12 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
\r
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
\r
15 * You may not use this file except in compliance with the License.
\r
16 * You may obtain a copy of the License at:
\r
18 * http://www.st.com/software_license_agreement_liberty_v2
\r
20 * Unless required by applicable law or agreed to in writing, software
\r
21 * distributed under the License is distributed on an "AS IS" BASIS,
\r
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
\r
23 * See the License for the specific language governing permissions and
\r
24 * limitations under the License.
\r
26 ******************************************************************************
\r
29 /* Includes ------------------------------------------------------------------*/
\r
32 /** @addtogroup STM32L1xx_StdPeriph_Driver
\r
37 * @brief MISC driver modules
\r
41 /* Private typedef -----------------------------------------------------------*/
\r
42 /* Private define ------------------------------------------------------------*/
\r
43 #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
\r
45 /* Private macro -------------------------------------------------------------*/
\r
46 /* Private variables ---------------------------------------------------------*/
\r
47 /* Private function prototypes -----------------------------------------------*/
\r
48 /* Private functions ---------------------------------------------------------*/
\r
50 /** @defgroup MISC_Private_Functions
\r
56 *******************************************************************************
\r
57 ##### Interrupts configuration functions #####
\r
58 *******************************************************************************
\r
59 [..] This section provide functions allowing to configure the NVIC interrupts
\r
60 (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
\r
61 (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
\r
62 function according to the following table.
\r
63 The table below gives the allowed values of the preemption priority
\r
64 and subpriority according to the Priority Grouping configuration
\r
65 performed by NVIC_PriorityGroupConfig function.
\r
66 ============================================================================================================================
\r
67 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
\r
68 ============================================================================================================================
\r
69 NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority
\r
70 | | | 4 bits for subpriority
\r
71 ----------------------------------------------------------------------------------------------------------------------------
\r
72 NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority
\r
73 | | | 3 bits for subpriority
\r
74 ----------------------------------------------------------------------------------------------------------------------------
\r
75 NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority
\r
76 | | | 2 bits for subpriority
\r
77 ----------------------------------------------------------------------------------------------------------------------------
\r
78 NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority
\r
79 | | | 1 bits for subpriority
\r
80 ----------------------------------------------------------------------------------------------------------------------------
\r
81 NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority
\r
82 | | | 0 bits for subpriority
\r
83 ============================================================================================================================
\r
86 (#) Enable and Configure the priority of the selected IRQ Channels.
\r
88 -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
\r
89 the IRQ priority will be managed only by subpriority.
\r
90 The sub-priority is only used to sort pending exception priorities,
\r
91 and does not affect active exceptions.
\r
92 -@- Lower priority values gives higher priority.
\r
94 (#@) Lowest Preemption priority.
\r
95 (#@) Lowest Subpriority.
\r
96 (#@) Lowest hardware priority (IRQn position).
\r
102 * @brief Configures the priority grouping: preemption priority and subpriority.
\r
103 * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
\r
104 * This parameter can be one of the following values:
\r
105 * @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
\r
106 * 4 bits for subpriority.
\r
107 * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
\r
108 * interrupt. This interrupts priority is managed only with subpriority.
\r
109 * @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
\r
110 * 3 bits for subpriority.
\r
111 * @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
\r
112 * 2 bits for subpriority.
\r
113 * @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
\r
114 * 1 bits for subpriority.
\r
115 * @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
\r
116 * 0 bits for subpriority.
\r
119 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
\r
121 /* Check the parameters */
\r
122 assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
\r
124 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
\r
125 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
\r
129 * @brief Initializes the NVIC peripheral according to the specified
\r
130 * parameters in the NVIC_InitStruct.
\r
131 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
\r
132 * function should be called before.
\r
133 * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
\r
134 * the configuration information for the specified NVIC peripheral.
\r
137 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
\r
139 uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
\r
141 /* Check the parameters */
\r
142 assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
\r
143 assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
\r
144 assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
\r
146 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
\r
148 /* Compute the Corresponding IRQ Priority --------------------------------*/
\r
149 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
\r
150 tmppre = (0x4 - tmppriority);
\r
151 tmpsub = tmpsub >> tmppriority;
\r
153 tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
\r
154 tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
\r
155 tmppriority = tmppriority << 0x04;
\r
157 NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
\r
159 /* Enable the Selected IRQ Channels --------------------------------------*/
\r
160 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
\r
161 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
\r
165 /* Disable the Selected IRQ Channels -------------------------------------*/
\r
166 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
\r
167 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
\r
172 * @brief Sets the vector table location and Offset.
\r
173 * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
\r
174 * This parameter can be one of the following values:
\r
175 * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
\r
176 * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
\r
177 * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
\r
180 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
\r
182 /* Check the parameters */
\r
183 assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
\r
184 assert_param(IS_NVIC_OFFSET(Offset));
\r
186 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
\r
190 * @brief Selects the condition for the system to enter low power mode.
\r
191 * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
\r
192 * This parameter can be one of the following values:
\r
193 * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
\r
194 * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
\r
195 * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
\r
196 * @param NewState: new state of LP condition.
\r
197 * This parameter can be: ENABLE or DISABLE.
\r
200 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
\r
202 /* Check the parameters */
\r
203 assert_param(IS_NVIC_LP(LowPowerMode));
\r
204 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
206 if (NewState != DISABLE)
\r
208 SCB->SCR |= LowPowerMode;
\r
212 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
\r
217 * @brief Configures the SysTick clock source.
\r
218 * @param SysTick_CLKSource: specifies the SysTick clock source.
\r
219 * This parameter can be one of the following values:
\r
220 * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
\r
221 * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
\r
224 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
\r
226 /* Check the parameters */
\r
227 assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
\r
229 if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
\r
231 SysTick->CTRL |= SysTick_CLKSource_HCLK;
\r
235 SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
\r
251 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r