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[freertos] / FreeRTOS / Demo / ColdFire_MCF51CN128_CodeWarrior / Sources / main.c
1 /*\r
2  * FreeRTOS Kernel V10.2.1\r
3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
4  *\r
5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
6  * this software and associated documentation files (the "Software"), to deal in\r
7  * the Software without restriction, including without limitation the rights to\r
8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
10  * subject to the following conditions:\r
11  *\r
12  * The above copyright notice and this permission notice shall be included in all\r
13  * copies or substantial portions of the Software.\r
14  *\r
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
21  *\r
22  * http://www.FreeRTOS.org\r
23  * http://aws.amazon.com/freertos\r
24  *\r
25  * 1 tab == 4 spaces!\r
26  */\r
27 \r
28 \r
29 /*\r
30  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
31  * documentation provides more details of the standard demo application tasks.\r
32  * In addition to the standard demo tasks, the following tasks and tests are\r
33  * defined and/or created within this file:\r
34  *\r
35  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
36  * simply generates a page that shows the current state of all the tasks within\r
37  * the system, including the high water mark of each task stack. The high water\r
38  * mark is displayed as the amount of stack that has never been used, so the\r
39  * closer the value is to zero the closer the task has come to overflowing its\r
40  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
41  * pages display some TCP/IP status information and permit LED3 to be turned on\r
42  * and off using a check box.\r
43  *\r
44  * Tick hook function that implements a "Check" function -  This is executed\r
45  * every 5 seconds from the tick hook function.  It checks to ensure that all\r
46  * the standard demo tasks are still operational and running without error.\r
47  * The system status (pass/fail) is then displayed underneith the task table on\r
48  * the served WEB pages.\r
49  *\r
50  * "Reg test" tasks - These fill the registers with known values, then check\r
51  * that each register still contains its expected value.  Each task uses\r
52  * different values.  The tasks run with very low priority so get preempted very\r
53  * frequently.  A register containing an unexpected value is indicative of an\r
54  * error in the context switching mechanism.\r
55  *\r
56  */\r
57 \r
58 /* Standard includes. */\r
59 #include <stdio.h>\r
60 \r
61 /* Scheduler includes. */\r
62 #include "FreeRTOS.h"\r
63 #include "task.h"\r
64 #include "queue.h"\r
65 #include "semphr.h"\r
66 \r
67 /* Demo app includes. */\r
68 #include "BlockQ.h"\r
69 #include "death.h"\r
70 #include "flash.h"\r
71 #include "partest.h"\r
72 #include "GenQTest.h"\r
73 #include "QPeek.h"\r
74 #include "recmutex.h"\r
75 \r
76 /*-----------------------------------------------------------*/\r
77 \r
78 /* ComTest constants - there is no free LED for the comtest tasks. */\r
79 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
80 #define mainCOM_TEST_LED                                        ( 5 )\r
81 \r
82 /* Task priorities. */\r
83 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
84 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
85 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
86 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
87 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
88 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
89 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
90 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
91 \r
92 /* WEB server requires enough stack for the string handling functions. */\r
93 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
94 \r
95 /*\r
96  * Configure the hardware for the demo.\r
97  */\r
98 static void prvSetupHardware( void );\r
99 \r
100 /*\r
101  * Implements the 'check' function as described at the top of this file.\r
102  */\r
103 static void prvCheckFunction( void );\r
104 \r
105 /*\r
106  * Implement the 'Reg test' functionality as described at the top of this file.\r
107  */\r
108 static void vRegTest1Task( void *pvParameters );\r
109 static void vRegTest2Task( void *pvParameters );\r
110 \r
111 /*\r
112  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
113  * this task.\r
114  */\r
115 extern void vuIP_Task( void *pvParameters );\r
116 \r
117 /*-----------------------------------------------------------*/\r
118 \r
119 /* Counters used to detect errors within the reg test tasks. */\r
120 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
121 \r
122 /* Flag that latches any errors detected in the system. */\r
123 unsigned long ulCheckErrors = 0;\r
124 \r
125 /*-----------------------------------------------------------*/\r
126 \r
127 int main( void )\r
128 {\r
129 extern void vBasicWEBServer( void *pv );\r
130 \r
131         /* Setup the hardware ready for this demo. */\r
132         prvSetupHardware();\r
133 \r
134         xTaskCreate( vuIP_Task, "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
135 \r
136         /* Start the standard demo tasks. */\r
137         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
138         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
139         vStartQueuePeekTasks();\r
140         vStartRecursiveMutexTasks();\r
141         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
142 \r
143         /* Start the reg test tasks - defined in this file. */\r
144         xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
145         xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
146 \r
147         /* Start the scheduler. */\r
148         vTaskStartScheduler();\r
149 \r
150     /* Will only get here if there was insufficient memory to create the idle\r
151     task. */\r
152         for( ;; )\r
153         {\r
154         }\r
155 }\r
156 /*-----------------------------------------------------------*/\r
157 \r
158 void vApplicationTickHook( void )\r
159 {\r
160 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
161 const unsigned long ulExecutionRate = 5000 / portTICK_PERIOD_MS;\r
162 \r
163     /* Increment the count of how many times the tick hook has been called. */\r
164     ulExecutionCount++;\r
165 \r
166     /* Is it time to perform the check again? */\r
167         if( ulExecutionCount >= ulExecutionRate )\r
168         {\r
169                 /* Reset the execution count so this function is called again in 5\r
170                 seconds time. */\r
171                 ulExecutionCount = 0;\r
172 \r
173                 /* Has an error been found in any task? */\r
174                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
175                 {\r
176                         ulCheckErrors |= 0x01UL;\r
177                 }\r
178 \r
179                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
180                 {\r
181                         ulCheckErrors |= 0x02UL;\r
182                 }\r
183 \r
184                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
185                 {\r
186                         ulCheckErrors |= 0x04UL;\r
187                 }\r
188 \r
189                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
190             {\r
191                 ulCheckErrors |= 0x200UL;\r
192             }\r
193 \r
194                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
195                 {\r
196                         ulCheckErrors |= 0x1000UL;\r
197                 }\r
198 \r
199                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
200                 {\r
201                         ulCheckErrors |= 0x1000UL;\r
202                 }\r
203 \r
204                 ulLastRegTest1Count = ulRegTest1Counter;\r
205                 ulLastRegTest2Count = ulRegTest2Counter;\r
206         }\r
207 }\r
208 /*-----------------------------------------------------------*/\r
209 \r
210 static void prvSetupHardware( void )\r
211 {\r
212         /* Disable the watchdog, STOP and WAIT modes. */\r
213         SOPT1 = 0;\r
214 \r
215         /* --- Setup clock to use external 25MHz source. --- */\r
216 \r
217         /* Extal and xtal pin ON. */\r
218         PTDPF1_D4 = 0x03;\r
219         PTDPF1_D5 = 0x03;\r
220 \r
221         /* Switch from FEI to FBE (FLL bypassed external)\r
222         enable external clock source */\r
223         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
224               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
225               | MCGC2_RANGE_MASK;   /* High range */\r
226 \r
227         /* Select clock mode and clear IREFs. */\r
228         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
229               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
230               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
231 \r
232         /* Wait for Reference and Clock status bits to update. */\r
233         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
234         {\r
235                 /* Nothing to do here. */\r
236         }\r
237 \r
238         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
239         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
240               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
241 \r
242         /* Wait for PLL status and lock bits to update. */\r
243         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
244         {\r
245                 /* Nothing to do here. */\r
246         }\r
247 \r
248 \r
249         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external\r
250         mode). */\r
251         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
252 \r
253         /* Wait for the clock status bits to update. */\r
254         while( MCGSC_CLKST != 0x03 )\r
255         {\r
256                 /* Nothing to do here. */\r
257         }\r
258 \r
259         /* Setup the IO for the LED outputs. */\r
260         vParTestInitialise();\r
261 }\r
262 /*-----------------------------------------------------------*/\r
263 \r
264 void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
265 {\r
266         /* This will get called if a stack overflow is detected during the context\r
267         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
268         problems within nested interrupts, but only do this for debug purposes as\r
269         it will increase the context switch time. */\r
270 \r
271         ( void ) pxTask;\r
272         ( void ) pcTaskName;\r
273 \r
274         for( ;; )\r
275         {\r
276         }\r
277 }\r
278 /*-----------------------------------------------------------*/\r
279 \r
280 static void vRegTest1Task( void *pvParameters )\r
281 {\r
282   /* Just to remove compiler warnings. */\r
283   ( void ) pvParameters;\r
284 \r
285         /* Set all the registers to known values, then check that each retains its\r
286         expected value - as described at the top of this file.  If an error is\r
287         found then the loop counter will no longer be incremented allowing the check\r
288         task to recognise the error. */\r
289         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
290                                                 "       moveq           #1, d0                                  \n\t"\r
291                                                 "       moveq           #2, d1                                  \n\t"\r
292                                                 "       moveq           #3, d2                                  \n\t"\r
293                                                 "       moveq           #4, d3                                  \n\t"\r
294                                                 "       moveq           #5, d4                                  \n\t"\r
295                                                 "       moveq           #6, d5                                  \n\t"\r
296                                                 "       moveq           #7, d6                                  \n\t"\r
297                                                 "       moveq           #8, d7                                  \n\t"\r
298                                                 "       move            #9, a0                                  \n\t"\r
299                                                 "       move            #10, a1                                 \n\t"\r
300                                                 "       move            #11, a2                                 \n\t"\r
301                                                 "       move            #12, a3                                 \n\t"\r
302                                                 "       move            #13, a4                                 \n\t"\r
303                                                 "       move            #15, a6                                 \n\t"\r
304                                                 "                                                                               \n\t"\r
305                                                 "       cmpi.l          #1, d0                                  \n\t"\r
306                                                 "       bne                     reg_test_1_error                \n\t"\r
307                                                 "       cmpi.l          #2, d1                                  \n\t"\r
308                                                 "       bne                     reg_test_1_error                \n\t"\r
309                                                 "       cmpi.l          #3, d2                                  \n\t"\r
310                                                 "       bne                     reg_test_1_error                \n\t"\r
311                                                 "       cmpi.l          #4, d3                                  \n\t"\r
312                                                 "       bne                     reg_test_1_error                \n\t"\r
313                                                 "       cmpi.l          #5, d4                                  \n\t"\r
314                                                 "       bne                     reg_test_1_error                \n\t"\r
315                                                 "       cmpi.l          #6, d5                                  \n\t"\r
316                                                 "       bne                     reg_test_1_error                \n\t"\r
317                                                 "       cmpi.l          #7, d6                                  \n\t"\r
318                                                 "       bne                     reg_test_1_error                \n\t"\r
319                                                 "       cmpi.l          #8, d7                                  \n\t"\r
320                                                 "       bne                     reg_test_1_error                \n\t"\r
321                                                 "       move            a0, d0                                  \n\t"\r
322                                                 "       cmpi.l          #9, d0                                  \n\t"\r
323                                                 "       bne                     reg_test_1_error                \n\t"\r
324                                                 "       move            a1, d0                                  \n\t"\r
325                                                 "       cmpi.l          #10, d0                                 \n\t"\r
326                                                 "       bne                     reg_test_1_error                \n\t"\r
327                                                 "       move            a2, d0                                  \n\t"\r
328                                                 "       cmpi.l          #11, d0                                 \n\t"\r
329                                                 "       bne                     reg_test_1_error                \n\t"\r
330                                                 "       move            a3, d0                                  \n\t"\r
331                                                 "       cmpi.l          #12, d0                                 \n\t"\r
332                                                 "       bne                     reg_test_1_error                \n\t"\r
333                                                 "       move            a4, d0                                  \n\t"\r
334                                                 "       cmpi.l          #13, d0                                 \n\t"\r
335                                                 "       bne                     reg_test_1_error                \n\t"\r
336                                                 "       move            a6, d0                                  \n\t"\r
337                                                 "       cmpi.l          #15, d0                                 \n\t"\r
338                                                 "       bne                     reg_test_1_error                \n\t"\r
339                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
340                                                 "       addq            #1, d0                                  \n\t"\r
341                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
342                                                 "       bra                     reg_test_1_start                \n\t"\r
343                                                 "reg_test_1_error:                                              \n\t"\r
344                                                 "       bra                     reg_test_1_error                \n\t"\r
345                                         );\r
346 }\r
347 /*-----------------------------------------------------------*/\r
348 \r
349 static void vRegTest2Task( void *pvParameters )\r
350 {\r
351   /* Just to remove compiler warnings. */\r
352   ( void ) pvParameters;\r
353 \r
354         /* Set all the registers to known values, then check that each retains its\r
355         expected value - as described at the top of this file.  If an error is\r
356         found then the loop counter will no longer be incremented allowing the check\r
357         task to recognise the error. */\r
358         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
359                                                 "       moveq           #10, d0                                 \n\t"\r
360                                                 "       moveq           #20, d1                                 \n\t"\r
361                                                 "       moveq           #30, d2                                 \n\t"\r
362                                                 "       moveq           #40, d3                                 \n\t"\r
363                                                 "       moveq           #50, d4                                 \n\t"\r
364                                                 "       moveq           #60, d5                                 \n\t"\r
365                                                 "       moveq           #70, d6                                 \n\t"\r
366                                                 "       moveq           #80, d7                                 \n\t"\r
367                                                 "       move            #90, a0                                 \n\t"\r
368                                                 "       move            #100, a1                                \n\t"\r
369                                                 "       move            #110, a2                                \n\t"\r
370                                                 "       move            #120, a3                                \n\t"\r
371                                                 "       move            #130, a4                                \n\t"\r
372                                                 "       move            #150, a6                                \n\t"\r
373                                                 "                                                                               \n\t"\r
374                                                 "       cmpi.l          #10, d0                                 \n\t"\r
375                                                 "       bne                     reg_test_2_error                \n\t"\r
376                                                 "       cmpi.l          #20, d1                                 \n\t"\r
377                                                 "       bne                     reg_test_2_error                \n\t"\r
378                                                 "       cmpi.l          #30, d2                                 \n\t"\r
379                                                 "       bne                     reg_test_2_error                \n\t"\r
380                                                 "       cmpi.l          #40, d3                                 \n\t"\r
381                                                 "       bne                     reg_test_2_error                \n\t"\r
382                                                 "       cmpi.l          #50, d4                                 \n\t"\r
383                                                 "       bne                     reg_test_2_error                \n\t"\r
384                                                 "       cmpi.l          #60, d5                                 \n\t"\r
385                                                 "       bne                     reg_test_2_error                \n\t"\r
386                                                 "       cmpi.l          #70, d6                                 \n\t"\r
387                                                 "       bne                     reg_test_2_error                \n\t"\r
388                                                 "       cmpi.l          #80, d7                                 \n\t"\r
389                                                 "       bne                     reg_test_2_error                \n\t"\r
390                                                 "       move            a0, d0                                  \n\t"\r
391                                                 "       cmpi.l          #90, d0                                 \n\t"\r
392                                                 "       bne                     reg_test_2_error                \n\t"\r
393                                                 "       move            a1, d0                                  \n\t"\r
394                                                 "       cmpi.l          #100, d0                                \n\t"\r
395                                                 "       bne                     reg_test_2_error                \n\t"\r
396                                                 "       move            a2, d0                                  \n\t"\r
397                                                 "       cmpi.l          #110, d0                                \n\t"\r
398                                                 "       bne                     reg_test_2_error                \n\t"\r
399                                                 "       move            a3, d0                                  \n\t"\r
400                                                 "       cmpi.l          #120, d0                                \n\t"\r
401                                                 "       bne                     reg_test_2_error                \n\t"\r
402                                                 "       move            a4, d0                                  \n\t"\r
403                                                 "       cmpi.l          #130, d0                                \n\t"\r
404                                                 "       bne                     reg_test_2_error                \n\t"\r
405                                                 "       move            a6, d0                                  \n\t"\r
406                                                 "       cmpi.l          #150, d0                                \n\t"\r
407                                                 "       bne                     reg_test_2_error                \n\t"\r
408                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
409                                                 "       addq            #1, d0                                  \n\t"\r
410                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
411                                                 "       bra                     reg_test_2_start                \n\t"\r
412                                                 "reg_test_2_error:                                              \n\t"\r
413                                                 "       bra                     reg_test_2_error                \n\t"\r
414                                         );\r
415 }\r
416 /*-----------------------------------------------------------*/\r
417 \r