git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/main.c

   1 /*\r
   2     FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    FreeRTOS provides completely free yet professionally developed,    *\r
  28      *    robust, strictly quality controlled, supported, and cross          *\r
  29      *    platform software that is more than just the market leader, it     *\r
  30      *    is the industry's de facto standard.                               *\r
  31      *                                                                       *\r
  32      *    Help yourself get started quickly while simultaneously helping     *\r
  33      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  34      *    tutorial book, reference manual, or both:                          *\r
  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality\r
  44     embedded software for free we request you assist our global community by\r
  45     participating in the support forum.\r
  46 \r
  47     http://www.FreeRTOS.org/training - Investing in training allows your team to\r
  48     be as productive as possible as early as possible.  Now you can receive\r
  49     FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
  50     Ltd, and the world's leading authority on the world's leading RTOS.\r
  51 \r
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  55 \r
  56     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  58 \r
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 \r
  71 /*\r
  72  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
  73  * documentation provides more details of the standard demo application tasks.\r
  74  * In addition to the standard demo tasks, the following tasks and tests are\r
  75  * defined and/or created within this file:\r
  76  *\r
  77  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
  78  * simply generates a page that shows the current state of all the tasks within\r
  79  * the system, including the high water mark of each task stack. The high water\r
  80  * mark is displayed as the amount of stack that has never been used, so the\r
  81  * closer the value is to zero the closer the task has come to overflowing its\r
  82  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
  83  * pages display some TCP/IP status information and permit LED3 to be turned on\r
  84  * and off using a check box.\r
  85  *\r
  86  * Tick hook function that implements a "Check" function -  This is executed\r
  87  * every 5 seconds from the tick hook function.  It checks to ensure that all\r
  88  * the standard demo tasks are still operational and running without error.\r
  89  * The system status (pass/fail) is then displayed underneith the task table on\r
  90  * the served WEB pages.\r
  91  *\r
  92  * "Reg test" tasks - These fill the registers with known values, then check\r
  93  * that each register still contains its expected value.  Each task uses\r
  94  * different values.  The tasks run with very low priority so get preempted very\r
  95  * frequently.  A register containing an unexpected value is indicative of an\r
  96  * error in the context switching mechanism.\r
  97  *\r
  98  */\r
  99 \r
 100 /* Standard includes. */\r
 101 #include <stdio.h>\r
 102 \r
 103 /* Scheduler includes. */\r
 104 #include "FreeRTOS.h"\r
 105 #include "task.h"\r
 106 #include "queue.h"\r
 107 #include "semphr.h"\r
 108 \r
 109 /* Demo app includes. */\r
 110 #include "BlockQ.h"\r
 111 #include "death.h"\r
 112 #include "flash.h"\r
 113 #include "partest.h"\r
 114 #include "GenQTest.h"\r
 115 #include "QPeek.h"\r
 116 #include "recmutex.h"\r
 117 \r
 118 /*-----------------------------------------------------------*/\r
 119 \r
 120 /* ComTest constants - there is no free LED for the comtest tasks. */\r
 121 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
 122 #define mainCOM_TEST_LED                                        ( 5 )\r
 123 \r
 124 /* Task priorities. */\r
 125 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
 126 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
 127 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
 128 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
 129 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
 130 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
 131 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
 132 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
 133 \r
 134 /* WEB server requires enough stack for the string handling functions. */\r
 135 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
 136 \r
 137 /*\r
 138  * Configure the hardware for the demo.\r
 139  */\r
 140 static void prvSetupHardware( void );\r
 141 \r
 142 /*\r
 143  * Implements the 'check' function as described at the top of this file.\r
 144  */\r
 145 static void prvCheckFunction( void );\r
 146 \r
 147 /*\r
 148  * Implement the 'Reg test' functionality as described at the top of this file.\r
 149  */\r
 150 static void vRegTest1Task( void *pvParameters );\r
 151 static void vRegTest2Task( void *pvParameters );\r
 152 \r
 153 /*\r
 154  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
 155  * this task.\r
 156  */\r
 157 extern void vuIP_Task( void *pvParameters );\r
 158 \r
 159 /*-----------------------------------------------------------*/\r
 160 \r
 161 /* Counters used to detect errors within the reg test tasks. */\r
 162 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 163 \r
 164 /* Flag that latches any errors detected in the system. */\r
 165 unsigned long ulCheckErrors = 0;\r
 166 \r
 167 /*-----------------------------------------------------------*/\r
 168 \r
 169 int main( void )\r
 170 {\r
 171 extern void vBasicWEBServer( void *pv );\r
 172 \r
 173         /* Setup the hardware ready for this demo. */\r
 174         prvSetupHardware();\r
 175 \r
 176         xTaskCreate( vuIP_Task, "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
 177 \r
 178         /* Start the standard demo tasks. */\r
 179         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
 180         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
 181         vStartQueuePeekTasks();\r
 182         vStartRecursiveMutexTasks();\r
 183         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
 184 \r
 185         /* Start the reg test tasks - defined in this file. */\r
 186         xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
 187         xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 188 \r
 189         /* Start the scheduler. */\r
 190         vTaskStartScheduler();\r
 191 \r
 192     /* Will only get here if there was insufficient memory to create the idle\r
 193     task. */\r
 194         for( ;; )\r
 195         {\r
 196         }\r
 197 }\r
 198 /*-----------------------------------------------------------*/\r
 199 \r
 200 void vApplicationTickHook( void )\r
 201 {\r
 202 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 203 const unsigned long ulExecutionRate = 5000 / portTICK_PERIOD_MS;\r
 204 \r
 205     /* Increment the count of how many times the tick hook has been called. */\r
 206     ulExecutionCount++;\r
 207 \r
 208     /* Is it time to perform the check again? */\r
 209         if( ulExecutionCount >= ulExecutionRate )\r
 210         {\r
 211                 /* Reset the execution count so this function is called again in 5\r
 212                 seconds time. */\r
 213                 ulExecutionCount = 0;\r
 214 \r
 215                 /* Has an error been found in any task? */\r
 216                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
 217                 {\r
 218                         ulCheckErrors |= 0x01UL;\r
 219                 }\r
 220 \r
 221                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
 222                 {\r
 223                         ulCheckErrors |= 0x02UL;\r
 224                 }\r
 225 \r
 226                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
 227                 {\r
 228                         ulCheckErrors |= 0x04UL;\r
 229                 }\r
 230 \r
 231                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
 232             {\r
 233                 ulCheckErrors |= 0x200UL;\r
 234             }\r
 235 \r
 236                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
 237                 {\r
 238                         ulCheckErrors |= 0x1000UL;\r
 239                 }\r
 240 \r
 241                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
 242                 {\r
 243                         ulCheckErrors |= 0x1000UL;\r
 244                 }\r
 245 \r
 246                 ulLastRegTest1Count = ulRegTest1Counter;\r
 247                 ulLastRegTest2Count = ulRegTest2Counter;\r
 248         }\r
 249 }\r
 250 /*-----------------------------------------------------------*/\r
 251 \r
 252 static void prvSetupHardware( void )\r
 253 {\r
 254         /* Disable the watchdog, STOP and WAIT modes. */\r
 255         SOPT1 = 0;\r
 256 \r
 257         /* --- Setup clock to use external 25MHz source. --- */\r
 258 \r
 259         /* Extal and xtal pin ON. */\r
 260         PTDPF1_D4 = 0x03;\r
 261         PTDPF1_D5 = 0x03;\r
 262 \r
 263         /* Switch from FEI to FBE (FLL bypassed external)\r
 264         enable external clock source */\r
 265         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
 266               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
 267               | MCGC2_RANGE_MASK;   /* High range */\r
 268 \r
 269         /* Select clock mode and clear IREFs. */\r
 270         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
 271               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
 272               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
 273 \r
 274         /* Wait for Reference and Clock status bits to update. */\r
 275         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
 276         {\r
 277                 /* Nothing to do here. */\r
 278         }\r
 279 \r
 280         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
 281         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
 282               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
 283 \r
 284         /* Wait for PLL status and lock bits to update. */\r
 285         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
 286         {\r
 287                 /* Nothing to do here. */\r
 288         }\r
 289 \r
 290 \r
 291         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external\r
 292         mode). */\r
 293         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
 294 \r
 295         /* Wait for the clock status bits to update. */\r
 296         while( MCGSC_CLKST != 0x03 )\r
 297         {\r
 298                 /* Nothing to do here. */\r
 299         }\r
 300 \r
 301         /* Setup the IO for the LED outputs. */\r
 302         vParTestInitialise();\r
 303 }\r
 304 /*-----------------------------------------------------------*/\r
 305 \r
 306 void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
 307 {\r
 308         /* This will get called if a stack overflow is detected during the context\r
 309         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
 310         problems within nested interrupts, but only do this for debug purposes as\r
 311         it will increase the context switch time. */\r
 312 \r
 313         ( void ) pxTask;\r
 314         ( void ) pcTaskName;\r
 315 \r
 316         for( ;; )\r
 317         {\r
 318         }\r
 319 }\r
 320 /*-----------------------------------------------------------*/\r
 321 \r
 322 static void vRegTest1Task( void *pvParameters )\r
 323 {\r
 324   /* Just to remove compiler warnings. */\r
 325   ( void ) pvParameters;\r
 326 \r
 327         /* Set all the registers to known values, then check that each retains its\r
 328         expected value - as described at the top of this file.  If an error is\r
 329         found then the loop counter will no longer be incremented allowing the check\r
 330         task to recognise the error. */\r
 331         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
 332                                                 "       moveq           #1, d0                                  \n\t"\r
 333                                                 "       moveq           #2, d1                                  \n\t"\r
 334                                                 "       moveq           #3, d2                                  \n\t"\r
 335                                                 "       moveq           #4, d3                                  \n\t"\r
 336                                                 "       moveq           #5, d4                                  \n\t"\r
 337                                                 "       moveq           #6, d5                                  \n\t"\r
 338                                                 "       moveq           #7, d6                                  \n\t"\r
 339                                                 "       moveq           #8, d7                                  \n\t"\r
 340                                                 "       move            #9, a0                                  \n\t"\r
 341                                                 "       move            #10, a1                                 \n\t"\r
 342                                                 "       move            #11, a2                                 \n\t"\r
 343                                                 "       move            #12, a3                                 \n\t"\r
 344                                                 "       move            #13, a4                                 \n\t"\r
 345                                                 "       move            #15, a6                                 \n\t"\r
 346                                                 "                                                                               \n\t"\r
 347                                                 "       cmpi.l          #1, d0                                  \n\t"\r
 348                                                 "       bne                     reg_test_1_error                \n\t"\r
 349                                                 "       cmpi.l          #2, d1                                  \n\t"\r
 350                                                 "       bne                     reg_test_1_error                \n\t"\r
 351                                                 "       cmpi.l          #3, d2                                  \n\t"\r
 352                                                 "       bne                     reg_test_1_error                \n\t"\r
 353                                                 "       cmpi.l          #4, d3                                  \n\t"\r
 354                                                 "       bne                     reg_test_1_error                \n\t"\r
 355                                                 "       cmpi.l          #5, d4                                  \n\t"\r
 356                                                 "       bne                     reg_test_1_error                \n\t"\r
 357                                                 "       cmpi.l          #6, d5                                  \n\t"\r
 358                                                 "       bne                     reg_test_1_error                \n\t"\r
 359                                                 "       cmpi.l          #7, d6                                  \n\t"\r
 360                                                 "       bne                     reg_test_1_error                \n\t"\r
 361                                                 "       cmpi.l          #8, d7                                  \n\t"\r
 362                                                 "       bne                     reg_test_1_error                \n\t"\r
 363                                                 "       move            a0, d0                                  \n\t"\r
 364                                                 "       cmpi.l          #9, d0                                  \n\t"\r
 365                                                 "       bne                     reg_test_1_error                \n\t"\r
 366                                                 "       move            a1, d0                                  \n\t"\r
 367                                                 "       cmpi.l          #10, d0                                 \n\t"\r
 368                                                 "       bne                     reg_test_1_error                \n\t"\r
 369                                                 "       move            a2, d0                                  \n\t"\r
 370                                                 "       cmpi.l          #11, d0                                 \n\t"\r
 371                                                 "       bne                     reg_test_1_error                \n\t"\r
 372                                                 "       move            a3, d0                                  \n\t"\r
 373                                                 "       cmpi.l          #12, d0                                 \n\t"\r
 374                                                 "       bne                     reg_test_1_error                \n\t"\r
 375                                                 "       move            a4, d0                                  \n\t"\r
 376                                                 "       cmpi.l          #13, d0                                 \n\t"\r
 377                                                 "       bne                     reg_test_1_error                \n\t"\r
 378                                                 "       move            a6, d0                                  \n\t"\r
 379                                                 "       cmpi.l          #15, d0                                 \n\t"\r
 380                                                 "       bne                     reg_test_1_error                \n\t"\r
 381                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
 382                                                 "       addq            #1, d0                                  \n\t"\r
 383                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
 384                                                 "       bra                     reg_test_1_start                \n\t"\r
 385                                                 "reg_test_1_error:                                              \n\t"\r
 386                                                 "       bra                     reg_test_1_error                \n\t"\r
 387                                         );\r
 388 }\r
 389 /*-----------------------------------------------------------*/\r
 390 \r
 391 static void vRegTest2Task( void *pvParameters )\r
 392 {\r
 393   /* Just to remove compiler warnings. */\r
 394   ( void ) pvParameters;\r
 395 \r
 396         /* Set all the registers to known values, then check that each retains its\r
 397         expected value - as described at the top of this file.  If an error is\r
 398         found then the loop counter will no longer be incremented allowing the check\r
 399         task to recognise the error. */\r
 400         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
 401                                                 "       moveq           #10, d0                                 \n\t"\r
 402                                                 "       moveq           #20, d1                                 \n\t"\r
 403                                                 "       moveq           #30, d2                                 \n\t"\r
 404                                                 "       moveq           #40, d3                                 \n\t"\r
 405                                                 "       moveq           #50, d4                                 \n\t"\r
 406                                                 "       moveq           #60, d5                                 \n\t"\r
 407                                                 "       moveq           #70, d6                                 \n\t"\r
 408                                                 "       moveq           #80, d7                                 \n\t"\r
 409                                                 "       move            #90, a0                                 \n\t"\r
 410                                                 "       move            #100, a1                                \n\t"\r
 411                                                 "       move            #110, a2                                \n\t"\r
 412                                                 "       move            #120, a3                                \n\t"\r
 413                                                 "       move            #130, a4                                \n\t"\r
 414                                                 "       move            #150, a6                                \n\t"\r
 415                                                 "                                                                               \n\t"\r
 416                                                 "       cmpi.l          #10, d0                                 \n\t"\r
 417                                                 "       bne                     reg_test_2_error                \n\t"\r
 418                                                 "       cmpi.l          #20, d1                                 \n\t"\r
 419                                                 "       bne                     reg_test_2_error                \n\t"\r
 420                                                 "       cmpi.l          #30, d2                                 \n\t"\r
 421                                                 "       bne                     reg_test_2_error                \n\t"\r
 422                                                 "       cmpi.l          #40, d3                                 \n\t"\r
 423                                                 "       bne                     reg_test_2_error                \n\t"\r
 424                                                 "       cmpi.l          #50, d4                                 \n\t"\r
 425                                                 "       bne                     reg_test_2_error                \n\t"\r
 426                                                 "       cmpi.l          #60, d5                                 \n\t"\r
 427                                                 "       bne                     reg_test_2_error                \n\t"\r
 428                                                 "       cmpi.l          #70, d6                                 \n\t"\r
 429                                                 "       bne                     reg_test_2_error                \n\t"\r
 430                                                 "       cmpi.l          #80, d7                                 \n\t"\r
 431                                                 "       bne                     reg_test_2_error                \n\t"\r
 432                                                 "       move            a0, d0                                  \n\t"\r
 433                                                 "       cmpi.l          #90, d0                                 \n\t"\r
 434                                                 "       bne                     reg_test_2_error                \n\t"\r
 435                                                 "       move            a1, d0                                  \n\t"\r
 436                                                 "       cmpi.l          #100, d0                                \n\t"\r
 437                                                 "       bne                     reg_test_2_error                \n\t"\r
 438                                                 "       move            a2, d0                                  \n\t"\r
 439                                                 "       cmpi.l          #110, d0                                \n\t"\r
 440                                                 "       bne                     reg_test_2_error                \n\t"\r
 441                                                 "       move            a3, d0                                  \n\t"\r
 442                                                 "       cmpi.l          #120, d0                                \n\t"\r
 443                                                 "       bne                     reg_test_2_error                \n\t"\r
 444                                                 "       move            a4, d0                                  \n\t"\r
 445                                                 "       cmpi.l          #130, d0                                \n\t"\r
 446                                                 "       bne                     reg_test_2_error                \n\t"\r
 447                                                 "       move            a6, d0                                  \n\t"\r
 448                                                 "       cmpi.l          #150, d0                                \n\t"\r
 449                                                 "       bne                     reg_test_2_error                \n\t"\r
 450                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
 451                                                 "       addq            #1, d0                                  \n\t"\r
 452                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
 453                                                 "       bra                     reg_test_2_start                \n\t"\r
 454                                                 "reg_test_2_error:                                              \n\t"\r
 455                                                 "       bra                     reg_test_2_error                \n\t"\r
 456                                         );\r
 457 }\r
 458 /*-----------------------------------------------------------*/\r
 459 \r