]> git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/main.c
d8267631bd4f74364bad39fb30039f81cb066afd
[freertos] / FreeRTOS / Demo / ColdFire_MCF51CN128_CodeWarrior / Sources / main.c
1 /*\r
2     FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
3         \r
4 \r
5     ***************************************************************************\r
6      *                                                                       *\r
7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
8      *    Complete, revised, and edited pdf reference manuals are also       *\r
9      *    available.                                                         *\r
10      *                                                                       *\r
11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
12      *    ensuring you get running as quickly as possible and with an        *\r
13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
14      *    the FreeRTOS project to continue with its mission of providing     *\r
15      *    professional grade, cross platform, de facto standard solutions    *\r
16      *    for microcontrollers - completely free of charge!                  *\r
17      *                                                                       *\r
18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
19      *                                                                       *\r
20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
21      *                                                                       *\r
22     ***************************************************************************\r
23 \r
24 \r
25     This file is part of the FreeRTOS distribution.\r
26 \r
27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
28     the terms of the GNU General Public License (version 2) as published by the\r
29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
31     distribute a combined work that includes FreeRTOS without being obliged to\r
32     provide the source code for proprietary components outside of the FreeRTOS\r
33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
36     more details. You should have received a copy of the GNU General Public\r
37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
39     by writing to Richard Barry, contact details for whom are available on the\r
40     FreeRTOS WEB site.\r
41 \r
42     1 tab == 4 spaces!\r
43     \r
44     ***************************************************************************\r
45      *                                                                       *\r
46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
47      *    not run, what could be wrong?                                      *\r
48      *                                                                       *\r
49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
50      *                                                                       *\r
51     ***************************************************************************\r
52 \r
53     \r
54     http://www.FreeRTOS.org - Documentation, training, latest information, \r
55     license and contact details.\r
56     \r
57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
58     including FreeRTOS+Trace - an indispensable productivity tool.\r
59 \r
60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
61     the code with commercial support, indemnification, and middleware, under \r
62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
63     provide a safety engineered and independently SIL3 certified version under \r
64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
65 */\r
66 \r
67 \r
68 /*\r
69  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
70  * documentation provides more details of the standard demo application tasks.\r
71  * In addition to the standard demo tasks, the following tasks and tests are\r
72  * defined and/or created within this file:\r
73  *\r
74  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
75  * simply generates a page that shows the current state of all the tasks within\r
76  * the system, including the high water mark of each task stack. The high water\r
77  * mark is displayed as the amount of stack that has never been used, so the\r
78  * closer the value is to zero the closer the task has come to overflowing its\r
79  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
80  * pages display some TCP/IP status information and permit LED3 to be turned on\r
81  * and off using a check box.\r
82  *\r
83  * Tick hook function that implements a "Check" function -  This is executed \r
84  * every 5 seconds from the tick hook function.  It checks to ensure that all \r
85  * the standard demo tasks are still operational and running without error.  \r
86  * The system status (pass/fail) is then displayed underneith the task table on \r
87  * the served WEB pages.  \r
88  *\r
89  * "Reg test" tasks - These fill the registers with known values, then check\r
90  * that each register still contains its expected value.  Each task uses\r
91  * different values.  The tasks run with very low priority so get preempted very\r
92  * frequently.  A register containing an unexpected value is indicative of an\r
93  * error in the context switching mechanism.\r
94  *\r
95  */\r
96 \r
97 /* Standard includes. */\r
98 #include <stdio.h>\r
99 \r
100 /* Scheduler includes. */\r
101 #include "FreeRTOS.h"\r
102 #include "task.h"\r
103 #include "queue.h"\r
104 #include "semphr.h"\r
105 \r
106 /* Demo app includes. */\r
107 #include "BlockQ.h"\r
108 #include "death.h"\r
109 #include "flash.h"\r
110 #include "partest.h"\r
111 #include "GenQTest.h"\r
112 #include "QPeek.h"\r
113 #include "recmutex.h"\r
114 \r
115 /*-----------------------------------------------------------*/\r
116 \r
117 /* ComTest constants - there is no free LED for the comtest tasks. */\r
118 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
119 #define mainCOM_TEST_LED                                        ( 5 )\r
120 \r
121 /* Task priorities. */\r
122 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
123 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
124 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
125 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
126 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
127 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
128 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
129 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
130 \r
131 /* WEB server requires enough stack for the string handling functions. */\r
132 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
133 \r
134 /*\r
135  * Configure the hardware for the demo.\r
136  */\r
137 static void prvSetupHardware( void );\r
138 \r
139 /*\r
140  * Implements the 'check' function as described at the top of this file.\r
141  */\r
142 static void prvCheckFunction( void );\r
143 \r
144 /*\r
145  * Implement the 'Reg test' functionality as described at the top of this file.\r
146  */\r
147 static void vRegTest1Task( void *pvParameters );\r
148 static void vRegTest2Task( void *pvParameters );\r
149 \r
150 /*\r
151  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
152  * this task.\r
153  */\r
154 extern void vuIP_Task( void *pvParameters );\r
155 \r
156 /*-----------------------------------------------------------*/\r
157 \r
158 /* Counters used to detect errors within the reg test tasks. */\r
159 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
160 \r
161 /* Flag that latches any errors detected in the system. */\r
162 unsigned long ulCheckErrors = 0;\r
163 \r
164 /*-----------------------------------------------------------*/\r
165 \r
166 int main( void )\r
167 {\r
168 extern void vBasicWEBServer( void *pv );\r
169 \r
170         /* Setup the hardware ready for this demo. */\r
171         prvSetupHardware();\r
172         \r
173         xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
174 \r
175         /* Start the standard demo tasks. */\r
176         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
177         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
178         vStartQueuePeekTasks();\r
179         vStartRecursiveMutexTasks();\r
180         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
181 \r
182         /* Start the reg test tasks - defined in this file. */\r
183         xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
184         xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
185 \r
186         /* Start the scheduler. */\r
187         vTaskStartScheduler();\r
188 \r
189     /* Will only get here if there was insufficient memory to create the idle\r
190     task. */\r
191         for( ;; )\r
192         {\r
193         }\r
194 }\r
195 /*-----------------------------------------------------------*/\r
196 \r
197 void vApplicationTickHook( void )\r
198 {\r
199 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
200 const unsigned long ulExecutionRate = 5000 / portTICK_RATE_MS;\r
201         \r
202     /* Increment the count of how many times the tick hook has been called. */\r
203     ulExecutionCount++;\r
204     \r
205     /* Is it time to perform the check again? */\r
206         if( ulExecutionCount >= ulExecutionRate )\r
207         {\r
208                 /* Reset the execution count so this function is called again in 5\r
209                 seconds time. */\r
210                 ulExecutionCount = 0;\r
211         \r
212                 /* Has an error been found in any task? */\r
213                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
214                 {\r
215                         ulCheckErrors |= 0x01UL;\r
216                 }\r
217 \r
218                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
219                 {\r
220                         ulCheckErrors |= 0x02UL;\r
221                 }\r
222 \r
223                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
224                 {\r
225                         ulCheckErrors |= 0x04UL;\r
226                 }\r
227 \r
228                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
229             {\r
230                 ulCheckErrors |= 0x200UL;\r
231             }\r
232 \r
233                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
234                 {\r
235                         ulCheckErrors |= 0x1000UL;\r
236                 }\r
237 \r
238                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
239                 {\r
240                         ulCheckErrors |= 0x1000UL;\r
241                 }\r
242 \r
243                 ulLastRegTest1Count = ulRegTest1Counter;\r
244                 ulLastRegTest2Count = ulRegTest2Counter;\r
245         }\r
246 }\r
247 /*-----------------------------------------------------------*/\r
248 \r
249 static void prvSetupHardware( void ) \r
250 {\r
251         /* Disable the watchdog, STOP and WAIT modes. */\r
252         SOPT1 = 0;\r
253 \r
254         /* --- Setup clock to use external 25MHz source. --- */\r
255         \r
256         /* Extal and xtal pin ON. */\r
257         PTDPF1_D4 = 0x03;\r
258         PTDPF1_D5 = 0x03;\r
259 \r
260         /* Switch from FEI to FBE (FLL bypassed external)\r
261         enable external clock source */\r
262         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
263               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
264               | MCGC2_RANGE_MASK;   /* High range */\r
265                 \r
266         /* Select clock mode and clear IREFs. */\r
267         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
268               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
269               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
270           \r
271         /* Wait for Reference and Clock status bits to update. */\r
272         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
273         {\r
274                 /* Nothing to do here. */\r
275         }\r
276 \r
277         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
278         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
279               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
280 \r
281         /* Wait for PLL status and lock bits to update. */\r
282         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
283         {\r
284                 /* Nothing to do here. */\r
285         }\r
286 \r
287 \r
288         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external \r
289         mode). */\r
290         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
291 \r
292         /* Wait for the clock status bits to update. */\r
293         while( MCGSC_CLKST != 0x03 )\r
294         {\r
295                 /* Nothing to do here. */\r
296         }\r
297 \r
298         /* Setup the IO for the LED outputs. */\r
299         vParTestInitialise();\r
300 }\r
301 /*-----------------------------------------------------------*/\r
302 \r
303 void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
304 {\r
305         /* This will get called if a stack overflow is detected during the context\r
306         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
307         problems within nested interrupts, but only do this for debug purposes as\r
308         it will increase the context switch time. */\r
309 \r
310         ( void ) pxTask;\r
311         ( void ) pcTaskName;\r
312 \r
313         for( ;; )\r
314         {\r
315         }\r
316 }\r
317 /*-----------------------------------------------------------*/\r
318 \r
319 static void vRegTest1Task( void *pvParameters )\r
320 {\r
321   /* Just to remove compiler warnings. */\r
322   ( void ) pvParameters;\r
323   \r
324         /* Set all the registers to known values, then check that each retains its\r
325         expected value - as described at the top of this file.  If an error is\r
326         found then the loop counter will no longer be incremented allowing the check\r
327         task to recognise the error. */\r
328         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
329                                                 "       moveq           #1, d0                                  \n\t"\r
330                                                 "       moveq           #2, d1                                  \n\t"\r
331                                                 "       moveq           #3, d2                                  \n\t"\r
332                                                 "       moveq           #4, d3                                  \n\t"\r
333                                                 "       moveq           #5, d4                                  \n\t"\r
334                                                 "       moveq           #6, d5                                  \n\t"                                           \r
335                                                 "       moveq           #7, d6                                  \n\t"\r
336                                                 "       moveq           #8, d7                                  \n\t"\r
337                                                 "       move            #9, a0                                  \n\t"\r
338                                                 "       move            #10, a1                                 \n\t"\r
339                                                 "       move            #11, a2                                 \n\t"\r
340                                                 "       move            #12, a3                                 \n\t"\r
341                                                 "       move            #13, a4                                 \n\t"\r
342                                                 "       move            #15, a6                                 \n\t"\r
343                                                 "                                                                               \n\t"\r
344                                                 "       cmpi.l          #1, d0                                  \n\t"\r
345                                                 "       bne                     reg_test_1_error                \n\t"\r
346                                                 "       cmpi.l          #2, d1                                  \n\t"\r
347                                                 "       bne                     reg_test_1_error                \n\t"\r
348                                                 "       cmpi.l          #3, d2                                  \n\t"\r
349                                                 "       bne                     reg_test_1_error                \n\t"\r
350                                                 "       cmpi.l          #4, d3                                  \n\t"\r
351                                                 "       bne                     reg_test_1_error                \n\t"\r
352                                                 "       cmpi.l          #5, d4                                  \n\t"\r
353                                                 "       bne                     reg_test_1_error                \n\t"\r
354                                                 "       cmpi.l          #6, d5                                  \n\t"\r
355                                                 "       bne                     reg_test_1_error                \n\t"\r
356                                                 "       cmpi.l          #7, d6                                  \n\t"\r
357                                                 "       bne                     reg_test_1_error                \n\t"\r
358                                                 "       cmpi.l          #8, d7                                  \n\t"\r
359                                                 "       bne                     reg_test_1_error                \n\t"\r
360                                                 "       move            a0, d0                                  \n\t"\r
361                                                 "       cmpi.l          #9, d0                                  \n\t"\r
362                                                 "       bne                     reg_test_1_error                \n\t"\r
363                                                 "       move            a1, d0                                  \n\t"\r
364                                                 "       cmpi.l          #10, d0                                 \n\t"\r
365                                                 "       bne                     reg_test_1_error                \n\t"\r
366                                                 "       move            a2, d0                                  \n\t"\r
367                                                 "       cmpi.l          #11, d0                                 \n\t"\r
368                                                 "       bne                     reg_test_1_error                \n\t"\r
369                                                 "       move            a3, d0                                  \n\t"\r
370                                                 "       cmpi.l          #12, d0                                 \n\t"\r
371                                                 "       bne                     reg_test_1_error                \n\t"\r
372                                                 "       move            a4, d0                                  \n\t"\r
373                                                 "       cmpi.l          #13, d0                                 \n\t"\r
374                                                 "       bne                     reg_test_1_error                \n\t"\r
375                                                 "       move            a6, d0                                  \n\t"\r
376                                                 "       cmpi.l          #15, d0                                 \n\t"\r
377                                                 "       bne                     reg_test_1_error                \n\t"\r
378                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
379                                                 "       addq            #1, d0                                  \n\t"\r
380                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
381                                                 "       bra                     reg_test_1_start                \n\t"\r
382                                                 "reg_test_1_error:                                              \n\t"\r
383                                                 "       bra                     reg_test_1_error                \n\t"\r
384                                         );\r
385 }\r
386 /*-----------------------------------------------------------*/\r
387 \r
388 static void vRegTest2Task( void *pvParameters )\r
389 {\r
390   /* Just to remove compiler warnings. */\r
391   ( void ) pvParameters;\r
392 \r
393         /* Set all the registers to known values, then check that each retains its\r
394         expected value - as described at the top of this file.  If an error is\r
395         found then the loop counter will no longer be incremented allowing the check\r
396         task to recognise the error. */\r
397         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
398                                                 "       moveq           #10, d0                                 \n\t"\r
399                                                 "       moveq           #20, d1                                 \n\t"\r
400                                                 "       moveq           #30, d2                                 \n\t"\r
401                                                 "       moveq           #40, d3                                 \n\t"\r
402                                                 "       moveq           #50, d4                                 \n\t"\r
403                                                 "       moveq           #60, d5                                 \n\t"\r
404                                                 "       moveq           #70, d6                                 \n\t"\r
405                                                 "       moveq           #80, d7                                 \n\t"\r
406                                                 "       move            #90, a0                                 \n\t"\r
407                                                 "       move            #100, a1                                \n\t"\r
408                                                 "       move            #110, a2                                \n\t"\r
409                                                 "       move            #120, a3                                \n\t"\r
410                                                 "       move            #130, a4                                \n\t"\r
411                                                 "       move            #150, a6                                \n\t"\r
412                                                 "                                                                               \n\t"\r
413                                                 "       cmpi.l          #10, d0                                 \n\t"\r
414                                                 "       bne                     reg_test_2_error                \n\t"\r
415                                                 "       cmpi.l          #20, d1                                 \n\t"\r
416                                                 "       bne                     reg_test_2_error                \n\t"\r
417                                                 "       cmpi.l          #30, d2                                 \n\t"\r
418                                                 "       bne                     reg_test_2_error                \n\t"\r
419                                                 "       cmpi.l          #40, d3                                 \n\t"\r
420                                                 "       bne                     reg_test_2_error                \n\t"\r
421                                                 "       cmpi.l          #50, d4                                 \n\t"\r
422                                                 "       bne                     reg_test_2_error                \n\t"\r
423                                                 "       cmpi.l          #60, d5                                 \n\t"\r
424                                                 "       bne                     reg_test_2_error                \n\t"\r
425                                                 "       cmpi.l          #70, d6                                 \n\t"\r
426                                                 "       bne                     reg_test_2_error                \n\t"\r
427                                                 "       cmpi.l          #80, d7                                 \n\t"\r
428                                                 "       bne                     reg_test_2_error                \n\t"\r
429                                                 "       move            a0, d0                                  \n\t"\r
430                                                 "       cmpi.l          #90, d0                                 \n\t"\r
431                                                 "       bne                     reg_test_2_error                \n\t"\r
432                                                 "       move            a1, d0                                  \n\t"\r
433                                                 "       cmpi.l          #100, d0                                \n\t"\r
434                                                 "       bne                     reg_test_2_error                \n\t"\r
435                                                 "       move            a2, d0                                  \n\t"\r
436                                                 "       cmpi.l          #110, d0                                \n\t"\r
437                                                 "       bne                     reg_test_2_error                \n\t"\r
438                                                 "       move            a3, d0                                  \n\t"\r
439                                                 "       cmpi.l          #120, d0                                \n\t"\r
440                                                 "       bne                     reg_test_2_error                \n\t"\r
441                                                 "       move            a4, d0                                  \n\t"\r
442                                                 "       cmpi.l          #130, d0                                \n\t"\r
443                                                 "       bne                     reg_test_2_error                \n\t"\r
444                                                 "       move            a6, d0                                  \n\t"\r
445                                                 "       cmpi.l          #150, d0                                \n\t"\r
446                                                 "       bne                     reg_test_2_error                \n\t"\r
447                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
448                                                 "       addq            #1, d0                                  \n\t"\r
449                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
450                                                 "       bra                     reg_test_2_start                \n\t"\r
451                                                 "reg_test_2_error:                                              \n\t"\r
452                                                 "       bra                     reg_test_2_error                \n\t"\r
453                                         );\r
454 }\r
455 /*-----------------------------------------------------------*/\r
456 \r