]> git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/main.c
Update version number ready to release the FAT file system demo.
[freertos] / FreeRTOS / Demo / ColdFire_MCF51CN128_CodeWarrior / Sources / main.c
1 /*\r
2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
3 \r
4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
6 \r
7     ***************************************************************************\r
8      *                                                                       *\r
9      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
10      *    Complete, revised, and edited pdf reference manuals are also       *\r
11      *    available.                                                         *\r
12      *                                                                       *\r
13      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
14      *    ensuring you get running as quickly as possible and with an        *\r
15      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
16      *    the FreeRTOS project to continue with its mission of providing     *\r
17      *    professional grade, cross platform, de facto standard solutions    *\r
18      *    for microcontrollers - completely free of charge!                  *\r
19      *                                                                       *\r
20      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
21      *                                                                       *\r
22      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
23      *                                                                       *\r
24     ***************************************************************************\r
25 \r
26 \r
27     This file is part of the FreeRTOS distribution.\r
28 \r
29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
30     the terms of the GNU General Public License (version 2) as published by the\r
31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
32 \r
33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
34     distribute a combined work that includes FreeRTOS without being obliged to\r
35     provide the source code for proprietary components outside of the FreeRTOS\r
36     kernel.\r
37 \r
38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
41     details. You should have received a copy of the GNU General Public License\r
42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
44     writing to Real Time Engineers Ltd., contact details for whom are available\r
45     on the FreeRTOS WEB site.\r
46 \r
47     1 tab == 4 spaces!\r
48 \r
49     ***************************************************************************\r
50      *                                                                       *\r
51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
52      *    not run, what could be wrong?"                                     *\r
53      *                                                                       *\r
54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
55      *                                                                       *\r
56     ***************************************************************************\r
57 \r
58 \r
59     http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
60     license and Real Time Engineers Ltd. contact details.\r
61 \r
62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
64     fully thread aware and reentrant UDP/IP stack.\r
65 \r
66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
67     Integrity Systems, who sell the code with commercial support, \r
68     indemnification and middleware, under the OpenRTOS brand.\r
69     \r
70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
71     engineered and independently SIL3 certified version for use in safety and \r
72     mission critical applications that require provable dependability.\r
73 */\r
74 \r
75 \r
76 /*\r
77  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
78  * documentation provides more details of the standard demo application tasks.\r
79  * In addition to the standard demo tasks, the following tasks and tests are\r
80  * defined and/or created within this file:\r
81  *\r
82  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
83  * simply generates a page that shows the current state of all the tasks within\r
84  * the system, including the high water mark of each task stack. The high water\r
85  * mark is displayed as the amount of stack that has never been used, so the\r
86  * closer the value is to zero the closer the task has come to overflowing its\r
87  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
88  * pages display some TCP/IP status information and permit LED3 to be turned on\r
89  * and off using a check box.\r
90  *\r
91  * Tick hook function that implements a "Check" function -  This is executed \r
92  * every 5 seconds from the tick hook function.  It checks to ensure that all \r
93  * the standard demo tasks are still operational and running without error.  \r
94  * The system status (pass/fail) is then displayed underneith the task table on \r
95  * the served WEB pages.  \r
96  *\r
97  * "Reg test" tasks - These fill the registers with known values, then check\r
98  * that each register still contains its expected value.  Each task uses\r
99  * different values.  The tasks run with very low priority so get preempted very\r
100  * frequently.  A register containing an unexpected value is indicative of an\r
101  * error in the context switching mechanism.\r
102  *\r
103  */\r
104 \r
105 /* Standard includes. */\r
106 #include <stdio.h>\r
107 \r
108 /* Scheduler includes. */\r
109 #include "FreeRTOS.h"\r
110 #include "task.h"\r
111 #include "queue.h"\r
112 #include "semphr.h"\r
113 \r
114 /* Demo app includes. */\r
115 #include "BlockQ.h"\r
116 #include "death.h"\r
117 #include "flash.h"\r
118 #include "partest.h"\r
119 #include "GenQTest.h"\r
120 #include "QPeek.h"\r
121 #include "recmutex.h"\r
122 \r
123 /*-----------------------------------------------------------*/\r
124 \r
125 /* ComTest constants - there is no free LED for the comtest tasks. */\r
126 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
127 #define mainCOM_TEST_LED                                        ( 5 )\r
128 \r
129 /* Task priorities. */\r
130 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
131 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
132 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
133 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
134 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
135 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
136 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
137 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
138 \r
139 /* WEB server requires enough stack for the string handling functions. */\r
140 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
141 \r
142 /*\r
143  * Configure the hardware for the demo.\r
144  */\r
145 static void prvSetupHardware( void );\r
146 \r
147 /*\r
148  * Implements the 'check' function as described at the top of this file.\r
149  */\r
150 static void prvCheckFunction( void );\r
151 \r
152 /*\r
153  * Implement the 'Reg test' functionality as described at the top of this file.\r
154  */\r
155 static void vRegTest1Task( void *pvParameters );\r
156 static void vRegTest2Task( void *pvParameters );\r
157 \r
158 /*\r
159  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
160  * this task.\r
161  */\r
162 extern void vuIP_Task( void *pvParameters );\r
163 \r
164 /*-----------------------------------------------------------*/\r
165 \r
166 /* Counters used to detect errors within the reg test tasks. */\r
167 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
168 \r
169 /* Flag that latches any errors detected in the system. */\r
170 unsigned long ulCheckErrors = 0;\r
171 \r
172 /*-----------------------------------------------------------*/\r
173 \r
174 int main( void )\r
175 {\r
176 extern void vBasicWEBServer( void *pv );\r
177 \r
178         /* Setup the hardware ready for this demo. */\r
179         prvSetupHardware();\r
180         \r
181         xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
182 \r
183         /* Start the standard demo tasks. */\r
184         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
185         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
186         vStartQueuePeekTasks();\r
187         vStartRecursiveMutexTasks();\r
188         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
189 \r
190         /* Start the reg test tasks - defined in this file. */\r
191         xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
192         xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
193 \r
194         /* Start the scheduler. */\r
195         vTaskStartScheduler();\r
196 \r
197     /* Will only get here if there was insufficient memory to create the idle\r
198     task. */\r
199         for( ;; )\r
200         {\r
201         }\r
202 }\r
203 /*-----------------------------------------------------------*/\r
204 \r
205 void vApplicationTickHook( void )\r
206 {\r
207 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
208 const unsigned long ulExecutionRate = 5000 / portTICK_RATE_MS;\r
209         \r
210     /* Increment the count of how many times the tick hook has been called. */\r
211     ulExecutionCount++;\r
212     \r
213     /* Is it time to perform the check again? */\r
214         if( ulExecutionCount >= ulExecutionRate )\r
215         {\r
216                 /* Reset the execution count so this function is called again in 5\r
217                 seconds time. */\r
218                 ulExecutionCount = 0;\r
219         \r
220                 /* Has an error been found in any task? */\r
221                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
222                 {\r
223                         ulCheckErrors |= 0x01UL;\r
224                 }\r
225 \r
226                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
227                 {\r
228                         ulCheckErrors |= 0x02UL;\r
229                 }\r
230 \r
231                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
232                 {\r
233                         ulCheckErrors |= 0x04UL;\r
234                 }\r
235 \r
236                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
237             {\r
238                 ulCheckErrors |= 0x200UL;\r
239             }\r
240 \r
241                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
242                 {\r
243                         ulCheckErrors |= 0x1000UL;\r
244                 }\r
245 \r
246                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
247                 {\r
248                         ulCheckErrors |= 0x1000UL;\r
249                 }\r
250 \r
251                 ulLastRegTest1Count = ulRegTest1Counter;\r
252                 ulLastRegTest2Count = ulRegTest2Counter;\r
253         }\r
254 }\r
255 /*-----------------------------------------------------------*/\r
256 \r
257 static void prvSetupHardware( void ) \r
258 {\r
259         /* Disable the watchdog, STOP and WAIT modes. */\r
260         SOPT1 = 0;\r
261 \r
262         /* --- Setup clock to use external 25MHz source. --- */\r
263         \r
264         /* Extal and xtal pin ON. */\r
265         PTDPF1_D4 = 0x03;\r
266         PTDPF1_D5 = 0x03;\r
267 \r
268         /* Switch from FEI to FBE (FLL bypassed external)\r
269         enable external clock source */\r
270         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
271               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
272               | MCGC2_RANGE_MASK;   /* High range */\r
273                 \r
274         /* Select clock mode and clear IREFs. */\r
275         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
276               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
277               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
278           \r
279         /* Wait for Reference and Clock status bits to update. */\r
280         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
281         {\r
282                 /* Nothing to do here. */\r
283         }\r
284 \r
285         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
286         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
287               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
288 \r
289         /* Wait for PLL status and lock bits to update. */\r
290         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
291         {\r
292                 /* Nothing to do here. */\r
293         }\r
294 \r
295 \r
296         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external \r
297         mode). */\r
298         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
299 \r
300         /* Wait for the clock status bits to update. */\r
301         while( MCGSC_CLKST != 0x03 )\r
302         {\r
303                 /* Nothing to do here. */\r
304         }\r
305 \r
306         /* Setup the IO for the LED outputs. */\r
307         vParTestInitialise();\r
308 }\r
309 /*-----------------------------------------------------------*/\r
310 \r
311 void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
312 {\r
313         /* This will get called if a stack overflow is detected during the context\r
314         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
315         problems within nested interrupts, but only do this for debug purposes as\r
316         it will increase the context switch time. */\r
317 \r
318         ( void ) pxTask;\r
319         ( void ) pcTaskName;\r
320 \r
321         for( ;; )\r
322         {\r
323         }\r
324 }\r
325 /*-----------------------------------------------------------*/\r
326 \r
327 static void vRegTest1Task( void *pvParameters )\r
328 {\r
329   /* Just to remove compiler warnings. */\r
330   ( void ) pvParameters;\r
331   \r
332         /* Set all the registers to known values, then check that each retains its\r
333         expected value - as described at the top of this file.  If an error is\r
334         found then the loop counter will no longer be incremented allowing the check\r
335         task to recognise the error. */\r
336         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
337                                                 "       moveq           #1, d0                                  \n\t"\r
338                                                 "       moveq           #2, d1                                  \n\t"\r
339                                                 "       moveq           #3, d2                                  \n\t"\r
340                                                 "       moveq           #4, d3                                  \n\t"\r
341                                                 "       moveq           #5, d4                                  \n\t"\r
342                                                 "       moveq           #6, d5                                  \n\t"                                           \r
343                                                 "       moveq           #7, d6                                  \n\t"\r
344                                                 "       moveq           #8, d7                                  \n\t"\r
345                                                 "       move            #9, a0                                  \n\t"\r
346                                                 "       move            #10, a1                                 \n\t"\r
347                                                 "       move            #11, a2                                 \n\t"\r
348                                                 "       move            #12, a3                                 \n\t"\r
349                                                 "       move            #13, a4                                 \n\t"\r
350                                                 "       move            #15, a6                                 \n\t"\r
351                                                 "                                                                               \n\t"\r
352                                                 "       cmpi.l          #1, d0                                  \n\t"\r
353                                                 "       bne                     reg_test_1_error                \n\t"\r
354                                                 "       cmpi.l          #2, d1                                  \n\t"\r
355                                                 "       bne                     reg_test_1_error                \n\t"\r
356                                                 "       cmpi.l          #3, d2                                  \n\t"\r
357                                                 "       bne                     reg_test_1_error                \n\t"\r
358                                                 "       cmpi.l          #4, d3                                  \n\t"\r
359                                                 "       bne                     reg_test_1_error                \n\t"\r
360                                                 "       cmpi.l          #5, d4                                  \n\t"\r
361                                                 "       bne                     reg_test_1_error                \n\t"\r
362                                                 "       cmpi.l          #6, d5                                  \n\t"\r
363                                                 "       bne                     reg_test_1_error                \n\t"\r
364                                                 "       cmpi.l          #7, d6                                  \n\t"\r
365                                                 "       bne                     reg_test_1_error                \n\t"\r
366                                                 "       cmpi.l          #8, d7                                  \n\t"\r
367                                                 "       bne                     reg_test_1_error                \n\t"\r
368                                                 "       move            a0, d0                                  \n\t"\r
369                                                 "       cmpi.l          #9, d0                                  \n\t"\r
370                                                 "       bne                     reg_test_1_error                \n\t"\r
371                                                 "       move            a1, d0                                  \n\t"\r
372                                                 "       cmpi.l          #10, d0                                 \n\t"\r
373                                                 "       bne                     reg_test_1_error                \n\t"\r
374                                                 "       move            a2, d0                                  \n\t"\r
375                                                 "       cmpi.l          #11, d0                                 \n\t"\r
376                                                 "       bne                     reg_test_1_error                \n\t"\r
377                                                 "       move            a3, d0                                  \n\t"\r
378                                                 "       cmpi.l          #12, d0                                 \n\t"\r
379                                                 "       bne                     reg_test_1_error                \n\t"\r
380                                                 "       move            a4, d0                                  \n\t"\r
381                                                 "       cmpi.l          #13, d0                                 \n\t"\r
382                                                 "       bne                     reg_test_1_error                \n\t"\r
383                                                 "       move            a6, d0                                  \n\t"\r
384                                                 "       cmpi.l          #15, d0                                 \n\t"\r
385                                                 "       bne                     reg_test_1_error                \n\t"\r
386                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
387                                                 "       addq            #1, d0                                  \n\t"\r
388                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
389                                                 "       bra                     reg_test_1_start                \n\t"\r
390                                                 "reg_test_1_error:                                              \n\t"\r
391                                                 "       bra                     reg_test_1_error                \n\t"\r
392                                         );\r
393 }\r
394 /*-----------------------------------------------------------*/\r
395 \r
396 static void vRegTest2Task( void *pvParameters )\r
397 {\r
398   /* Just to remove compiler warnings. */\r
399   ( void ) pvParameters;\r
400 \r
401         /* Set all the registers to known values, then check that each retains its\r
402         expected value - as described at the top of this file.  If an error is\r
403         found then the loop counter will no longer be incremented allowing the check\r
404         task to recognise the error. */\r
405         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
406                                                 "       moveq           #10, d0                                 \n\t"\r
407                                                 "       moveq           #20, d1                                 \n\t"\r
408                                                 "       moveq           #30, d2                                 \n\t"\r
409                                                 "       moveq           #40, d3                                 \n\t"\r
410                                                 "       moveq           #50, d4                                 \n\t"\r
411                                                 "       moveq           #60, d5                                 \n\t"\r
412                                                 "       moveq           #70, d6                                 \n\t"\r
413                                                 "       moveq           #80, d7                                 \n\t"\r
414                                                 "       move            #90, a0                                 \n\t"\r
415                                                 "       move            #100, a1                                \n\t"\r
416                                                 "       move            #110, a2                                \n\t"\r
417                                                 "       move            #120, a3                                \n\t"\r
418                                                 "       move            #130, a4                                \n\t"\r
419                                                 "       move            #150, a6                                \n\t"\r
420                                                 "                                                                               \n\t"\r
421                                                 "       cmpi.l          #10, d0                                 \n\t"\r
422                                                 "       bne                     reg_test_2_error                \n\t"\r
423                                                 "       cmpi.l          #20, d1                                 \n\t"\r
424                                                 "       bne                     reg_test_2_error                \n\t"\r
425                                                 "       cmpi.l          #30, d2                                 \n\t"\r
426                                                 "       bne                     reg_test_2_error                \n\t"\r
427                                                 "       cmpi.l          #40, d3                                 \n\t"\r
428                                                 "       bne                     reg_test_2_error                \n\t"\r
429                                                 "       cmpi.l          #50, d4                                 \n\t"\r
430                                                 "       bne                     reg_test_2_error                \n\t"\r
431                                                 "       cmpi.l          #60, d5                                 \n\t"\r
432                                                 "       bne                     reg_test_2_error                \n\t"\r
433                                                 "       cmpi.l          #70, d6                                 \n\t"\r
434                                                 "       bne                     reg_test_2_error                \n\t"\r
435                                                 "       cmpi.l          #80, d7                                 \n\t"\r
436                                                 "       bne                     reg_test_2_error                \n\t"\r
437                                                 "       move            a0, d0                                  \n\t"\r
438                                                 "       cmpi.l          #90, d0                                 \n\t"\r
439                                                 "       bne                     reg_test_2_error                \n\t"\r
440                                                 "       move            a1, d0                                  \n\t"\r
441                                                 "       cmpi.l          #100, d0                                \n\t"\r
442                                                 "       bne                     reg_test_2_error                \n\t"\r
443                                                 "       move            a2, d0                                  \n\t"\r
444                                                 "       cmpi.l          #110, d0                                \n\t"\r
445                                                 "       bne                     reg_test_2_error                \n\t"\r
446                                                 "       move            a3, d0                                  \n\t"\r
447                                                 "       cmpi.l          #120, d0                                \n\t"\r
448                                                 "       bne                     reg_test_2_error                \n\t"\r
449                                                 "       move            a4, d0                                  \n\t"\r
450                                                 "       cmpi.l          #130, d0                                \n\t"\r
451                                                 "       bne                     reg_test_2_error                \n\t"\r
452                                                 "       move            a6, d0                                  \n\t"\r
453                                                 "       cmpi.l          #150, d0                                \n\t"\r
454                                                 "       bne                     reg_test_2_error                \n\t"\r
455                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
456                                                 "       addq            #1, d0                                  \n\t"\r
457                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
458                                                 "       bra                     reg_test_2_start                \n\t"\r
459                                                 "reg_test_2_error:                                              \n\t"\r
460                                                 "       bra                     reg_test_2_error                \n\t"\r
461                                         );\r
462 }\r
463 /*-----------------------------------------------------------*/\r
464 \r