git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/main.c

   1 /*\r
   2     FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 \r
  67 /*\r
  68  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
  69  * documentation provides more details of the standard demo application tasks.\r
  70  * In addition to the standard demo tasks, the following tasks and tests are\r
  71  * defined and/or created within this file:\r
  72  *\r
  73  * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP\r
  74  * processing is performed in this task.  It manages the WEB server functionality.\r
  75  *\r
  76  * "Check" task -  This only executes every five seconds but has a high priority\r
  77  * to ensure it gets processor time.  Its main function is to check that all the\r
  78  * standard demo tasks are still operational.  An error found in any task will be\r
  79  * latched in the ulErrorCode variable for display through the WEB server (the\r
  80  * error code is displayed at the foot of the table that contains information on\r
  81  * the state of each task).\r
  82  *\r
  83  * "Reg test" tasks - These fill the registers with known values, then check\r
  84  * that each register still contains its expected value.  Each task uses\r
  85  * different values.  The tasks run with very low priority so get preempted very\r
  86  * frequently.  A register containing an unexpected value is indicative of an\r
  87  * error in the context switching mechanism.\r
  88  *\r
  89  */\r
  90 \r
  91 /* Standard includes. */\r
  92 #include <stdio.h>\r
  93 \r
  94 /* Scheduler includes. */\r
  95 #include "FreeRTOS.h"\r
  96 #include "task.h"\r
  97 #include "queue.h"\r
  98 #include "semphr.h"\r
  99 \r
 100 /* Demo app includes. */\r
 101 #include "BlockQ.h"\r
 102 #include "death.h"\r
 103 #include "blocktim.h"\r
 104 #include "flash.h"\r
 105 #include "partest.h"\r
 106 #include "semtest.h"\r
 107 #include "PollQ.h"\r
 108 #include "GenQTest.h"\r
 109 #include "QPeek.h"\r
 110 #include "recmutex.h"\r
 111 #include "IntQueue.h"\r
 112 #include "comtest2.h"\r
 113 \r
 114 /*-----------------------------------------------------------*/\r
 115 \r
 116 /* The time between cycles of the 'check' functionality - as described at the\r
 117 top of this file. */\r
 118 #define mainCHECK_TASK_PERIOD                                   ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
 119 \r
 120 /* Task priorities. */\r
 121 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
 122 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
 123 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
 124 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
 125 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
 126 \r
 127 /* The WEB server task uses more stack than most other tasks because of its\r
 128 reliance on using sprintf(). */\r
 129 #define mainBASIC_WEB_STACK_SIZE                        ( configMINIMAL_STACK_SIZE * 2 )\r
 130 \r
 131 /*\r
 132  * Configure the hardware for the demo.\r
 133  */\r
 134 static void prvSetupHardware( void );\r
 135 \r
 136 /*\r
 137  * Implements the 'check' task functionality as described at the top of this\r
 138  * file.\r
 139  */\r
 140 static void prvCheckTask( void *pvParameters );\r
 141 \r
 142 /*\r
 143  * The task that implements the WEB server.\r
 144  */\r
 145 extern void vuIP_Task( void *pvParameters );\r
 146 \r
 147 /*\r
 148  * Implement the 'Reg test' functionality as described at the top of this file.\r
 149  */\r
 150 static void vRegTest1Task( void *pvParameters );\r
 151 static void vRegTest2Task( void *pvParameters );\r
 152 \r
 153 /*-----------------------------------------------------------*/\r
 154 \r
 155 /* Counters used to detect errors within the reg test tasks. */\r
 156 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 157 \r
 158 /* Any errors that the check task finds in any tasks are latched into\r
 159 ulErrorCode, and then displayed via the WEB server. */\r
 160 static unsigned long ulErrorCode = 0UL;\r
 161 \r
 162 /*-----------------------------------------------------------*/\r
 163 \r
 164 int main( void )\r
 165 {\r
 166         /* Setup the hardware ready for this demo. */\r
 167         prvSetupHardware();\r
 168 \r
 169         /* Create the WEB server task. */\r
 170         xTaskCreate( vuIP_Task, "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
 171 \r
 172         /* Start the standard demo tasks. */\r
 173         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
 174         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
 175     vCreateBlockTimeTasks();\r
 176         vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
 177         vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
 178         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
 179         vStartQueuePeekTasks();\r
 180     vStartRecursiveMutexTasks();\r
 181 \r
 182         /* Start the reg test tasks - defined in this file. */\r
 183         xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
 184         xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 185 \r
 186         /* Create the check task. */\r
 187         xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
 188 \r
 189         /* Start the scheduler. */\r
 190         vTaskStartScheduler();\r
 191 \r
 192     /* Will only get here if there was insufficient heap to create the idle\r
 193     task. */\r
 194         for( ;; );\r
 195 }\r
 196 /*-----------------------------------------------------------*/\r
 197 \r
 198 static void prvCheckTask( void *pvParameters )\r
 199 {\r
 200 unsigned ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 201 portTickType xLastExecutionTime;\r
 202 \r
 203         /* To prevent compiler warnings. */\r
 204         ( void ) pvParameters;\r
 205 \r
 206         /* Initialise the variable used to control our iteration rate prior to\r
 207         its first use. */\r
 208         xLastExecutionTime = xTaskGetTickCount();\r
 209 \r
 210         for( ;; )\r
 211         {\r
 212                 /* Wait until it is time to run the tests again. */\r
 213                 vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD );\r
 214 \r
 215                 /* Has an error been found in any task? */\r
 216                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
 217                 {\r
 218                         ulErrorCode |= 0x01UL;\r
 219                 }\r
 220 \r
 221                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
 222                 {\r
 223                         ulErrorCode |= 0x02UL;\r
 224                 }\r
 225 \r
 226                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
 227                 {\r
 228                         ulErrorCode |= 0x04UL;\r
 229                 }\r
 230 \r
 231                 if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
 232             {\r
 233                 ulErrorCode |= 0x20UL;\r
 234             }\r
 235 \r
 236                 if( xArePollingQueuesStillRunning() != pdTRUE )\r
 237             {\r
 238                 ulErrorCode |= 0x40UL;\r
 239             }\r
 240 \r
 241                 if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
 242                 {\r
 243                         ulErrorCode |= 0x80UL;\r
 244                 }\r
 245 \r
 246             if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
 247             {\r
 248                 ulErrorCode |= 0x100UL;\r
 249             }\r
 250 \r
 251                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
 252                 {\r
 253                         ulErrorCode |= 0x200UL;\r
 254                 }\r
 255 \r
 256                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
 257                 {\r
 258                         ulErrorCode |= 0x200UL;\r
 259                 }\r
 260 \r
 261                 /* Remember the reg test counts so a stall in their values can be\r
 262                 detected next time around. */\r
 263                 ulLastRegTest1Count = ulRegTest1Counter;\r
 264                 ulLastRegTest2Count = ulRegTest2Counter;\r
 265         }\r
 266 }\r
 267 /*-----------------------------------------------------------*/\r
 268 \r
 269 unsigned long ulGetErrorCode( void )\r
 270 {\r
 271         /* Returns the error code for display via the WEB server. */\r
 272         return ulErrorCode;\r
 273 }\r
 274 /*-----------------------------------------------------------*/\r
 275 \r
 276 void prvSetupHardware( void )\r
 277 {\r
 278 __attribute__ ((section(".cfmconfig")))\r
 279 static const unsigned long _cfm[6] = {\r
 280         0, /* KEY_UPPER 0x00000400 */\r
 281         0, /* KEY_LOWER 0x00000404 */\r
 282         0, /* CFMPROT 0x00000408 */\r
 283         0, /* CFMSACC 0x0000040C */\r
 284         0, /* CFMDACC 0x00000410 */\r
 285         0, /* CFMSEC 0x00000414 */\r
 286 };\r
 287 \r
 288         /* Just to stop compiler warnings. */\r
 289         ( void ) _cfm;\r
 290 \r
 291         /* Ensure the watchdog is disabled. */\r
 292         MCF_SCM_CWCR = 0;\r
 293 \r
 294     /* Initialize IPSBAR (0x40000000). */\r
 295         asm volatile(\r
 296                 "move.l  #0x40000000,%d0        \n"\r
 297                 "andi.l  #0xC0000000,%d0        \n"\r
 298                 "add.l   #0x1,%d0                       \n"\r
 299                 "move.l  %d0,0x40000000         "\r
 300         );\r
 301 \r
 302     /* Initialize FLASHBAR (0x00) */\r
 303         asm volatile(\r
 304                 "move.l  #0x00,%d0                      \n"\r
 305                 "andi.l  #0xFFF80000,%d0        \n"\r
 306                 "add.l   #0x41,%d0                      \n"\r
 307                 "movec   %d0,%FLASHBAR          "\r
 308         );\r
 309 \r
 310         portDISABLE_INTERRUPTS();\r
 311 \r
 312         /* RAMBAR. */\r
 313         MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;\r
 314 \r
 315         /* Multiply 25MHz crystal by 12 to get 60MHz clock. */\r
 316         MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;\r
 317         while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
 318         {\r
 319         }\r
 320 \r
 321         /* Setup the port used to toggle LEDs. */\r
 322         vParTestInitialise();\r
 323 }\r
 324 /*-----------------------------------------------------------*/\r
 325 \r
 326 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
 327 {\r
 328         /* This will get called if a stack overflow is detected during the context\r
 329         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
 330         problems within nested interrupts, but only do this for debug purposes as\r
 331         it will increase the context switch time. */\r
 332 \r
 333         ( void ) pxTask;\r
 334         ( void ) pcTaskName;\r
 335 \r
 336         for( ;; );\r
 337 }\r
 338 /*-----------------------------------------------------------*/\r
 339 \r
 340 static void vRegTest1Task( void *pvParameters )\r
 341 {\r
 342         /* Sanity check - did we receive the parameter expected? */\r
 343         if( pvParameters != &ulRegTest1Counter )\r
 344         {\r
 345                 /* Change here so the check task can detect that an error occurred. */\r
 346                 for( ;; );\r
 347         }\r
 348 \r
 349         /* Set all the registers to known values, then check that each retains its\r
 350         expected value - as described at the top of this file.  If an error is\r
 351         found then the loop counter will no longer be incremented allowing the check\r
 352         task to recognise the error. */\r
 353         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
 354                                                 "       moveq           #1, %d0                                 \n\t"\r
 355                                                 "       moveq           #2, %d1                                 \n\t"\r
 356                                                 "       moveq           #3, %d2                                 \n\t"\r
 357                                                 "       moveq           #4, %d3                                 \n\t"\r
 358                                                 "       moveq           #5, %d4                                 \n\t"\r
 359                                                 "       moveq           #6, %d5                                 \n\t"\r
 360                                                 "       moveq           #7, %d6                                 \n\t"\r
 361                                                 "       moveq           #8, %d7                                 \n\t"\r
 362                                                 "       move            #9, %a0                                 \n\t"\r
 363                                                 "       move            #10, %a1                                \n\t"\r
 364                                                 "       move            #11, %a2                                \n\t"\r
 365                                                 "       move            #12, %a3                                \n\t"\r
 366                                                 "       move            #13, %a4                                \n\t"\r
 367                                                 "       move            #14, %a5                                \n\t"\r
 368                                                 "       move            #15, %a6                                \n\t"\r
 369                                                 "                                                                               \n\t"\r
 370                                                 "       cmpi.l          #1, %d0                                 \n\t"\r
 371                                                 "       bne                     reg_test_1_error                \n\t"\r
 372                                                 "       cmpi.l          #2, %d1                                 \n\t"\r
 373                                                 "       bne                     reg_test_1_error                \n\t"\r
 374                                                 "       cmpi.l          #3, %d2                                 \n\t"\r
 375                                                 "       bne                     reg_test_1_error                \n\t"\r
 376                                                 "       cmpi.l          #4, %d3                                 \n\t"\r
 377                                                 "       bne                     reg_test_1_error                \n\t"\r
 378                                                 "       cmpi.l          #5, %d4                                 \n\t"\r
 379                                                 "       bne                     reg_test_1_error                \n\t"\r
 380                                                 "       cmpi.l          #6, %d5                                 \n\t"\r
 381                                                 "       bne                     reg_test_1_error                \n\t"\r
 382                                                 "       cmpi.l          #7, %d6                                 \n\t"\r
 383                                                 "       bne                     reg_test_1_error                \n\t"\r
 384                                                 "       cmpi.l          #8, %d7                                 \n\t"\r
 385                                                 "       bne                     reg_test_1_error                \n\t"\r
 386                                                 "       move            %a0, %d0                                \n\t"\r
 387                                                 "       cmpi.l          #9, %d0                                 \n\t"\r
 388                                                 "       bne                     reg_test_1_error                \n\t"\r
 389                                                 "       move            %a1, %d0                                \n\t"\r
 390                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 391                                                 "       bne                     reg_test_1_error                \n\t"\r
 392                                                 "       move            %a2, %d0                                \n\t"\r
 393                                                 "       cmpi.l          #11, %d0                                \n\t"\r
 394                                                 "       bne                     reg_test_1_error                \n\t"\r
 395                                                 "       move            %a3, %d0                                \n\t"\r
 396                                                 "       cmpi.l          #12, %d0                                \n\t"\r
 397                                                 "       bne                     reg_test_1_error                \n\t"\r
 398                                                 "       move            %a4, %d0                                \n\t"\r
 399                                                 "       cmpi.l          #13, %d0                                \n\t"\r
 400                                                 "       bne                     reg_test_1_error                \n\t"\r
 401                                                 "       move            %a5, %d0                                \n\t"\r
 402                                                 "       cmpi.l          #14, %d0                                \n\t"\r
 403                                                 "       bne                     reg_test_1_error                \n\t"\r
 404                                                 "       move            %a6, %d0                                \n\t"\r
 405                                                 "       cmpi.l          #15, %d0                                \n\t"\r
 406                                                 "       bne                     reg_test_1_error                \n\t"\r
 407                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 408                                                 "       addql           #1, %d0                                 \n\t"\r
 409                                                 "       movel           %d0, ulRegTest1Counter  \n\t"\r
 410                                                 "       bra                     reg_test_1_start                \n\t"\r
 411                                                 "reg_test_1_error:                                              \n\t"\r
 412                                                 "       bra                     reg_test_1_error                \n\t"\r
 413                                         );\r
 414 }\r
 415 /*-----------------------------------------------------------*/\r
 416 \r
 417 static void vRegTest2Task( void *pvParameters )\r
 418 {\r
 419         /* Sanity check - did we receive the parameter expected? */\r
 420         if( pvParameters != &ulRegTest2Counter )\r
 421         {\r
 422                 /* Change here so the check task can detect that an error occurred. */\r
 423                 for( ;; );\r
 424         }\r
 425 \r
 426         /* Set all the registers to known values, then check that each retains its\r
 427         expected value - as described at the top of this file.  If an error is\r
 428         found then the loop counter will no longer be incremented allowing the check\r
 429         task to recognise the error. */\r
 430         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
 431                                                 "       moveq           #10, %d0                                \n\t"\r
 432                                                 "       moveq           #20, %d1                                \n\t"\r
 433                                                 "       moveq           #30, %d2                                \n\t"\r
 434                                                 "       moveq           #40, %d3                                \n\t"\r
 435                                                 "       moveq           #50, %d4                                \n\t"\r
 436                                                 "       moveq           #60, %d5                                \n\t"\r
 437                                                 "       moveq           #70, %d6                                \n\t"\r
 438                                                 "       moveq           #80, %d7                                \n\t"\r
 439                                                 "       move            #90, %a0                                \n\t"\r
 440                                                 "       move            #100, %a1                               \n\t"\r
 441                                                 "       move            #110, %a2                               \n\t"\r
 442                                                 "       move            #120, %a3                               \n\t"\r
 443                                                 "       move            #130, %a4                               \n\t"\r
 444                                                 "       move            #140, %a5                               \n\t"\r
 445                                                 "       move            #150, %a6                               \n\t"\r
 446                                                 "                                                                               \n\t"\r
 447                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 448                                                 "       bne                     reg_test_2_error                \n\t"\r
 449                                                 "       cmpi.l          #20, %d1                                \n\t"\r
 450                                                 "       bne                     reg_test_2_error                \n\t"\r
 451                                                 "       cmpi.l          #30, %d2                                \n\t"\r
 452                                                 "       bne                     reg_test_2_error                \n\t"\r
 453                                                 "       cmpi.l          #40, %d3                                \n\t"\r
 454                                                 "       bne                     reg_test_2_error                \n\t"\r
 455                                                 "       cmpi.l          #50, %d4                                \n\t"\r
 456                                                 "       bne                     reg_test_2_error                \n\t"\r
 457                                                 "       cmpi.l          #60, %d5                                \n\t"\r
 458                                                 "       bne                     reg_test_2_error                \n\t"\r
 459                                                 "       cmpi.l          #70, %d6                                \n\t"\r
 460                                                 "       bne                     reg_test_2_error                \n\t"\r
 461                                                 "       cmpi.l          #80, %d7                                \n\t"\r
 462                                                 "       bne                     reg_test_2_error                \n\t"\r
 463                                                 "       move            %a0, %d0                                \n\t"\r
 464                                                 "       cmpi.l          #90, %d0                                \n\t"\r
 465                                                 "       bne                     reg_test_2_error                \n\t"\r
 466                                                 "       move            %a1, %d0                                \n\t"\r
 467                                                 "       cmpi.l          #100, %d0                               \n\t"\r
 468                                                 "       bne                     reg_test_2_error                \n\t"\r
 469                                                 "       move            %a2, %d0                                \n\t"\r
 470                                                 "       cmpi.l          #110, %d0                               \n\t"\r
 471                                                 "       bne                     reg_test_2_error                \n\t"\r
 472                                                 "       move            %a3, %d0                                \n\t"\r
 473                                                 "       cmpi.l          #120, %d0                               \n\t"\r
 474                                                 "       bne                     reg_test_2_error                \n\t"\r
 475                                                 "       move            %a4, %d0                                \n\t"\r
 476                                                 "       cmpi.l          #130, %d0                               \n\t"\r
 477                                                 "       bne                     reg_test_2_error                \n\t"\r
 478                                                 "       move            %a5, %d0                                \n\t"\r
 479                                                 "       cmpi.l          #140, %d0                               \n\t"\r
 480                                                 "       bne                     reg_test_2_error                \n\t"\r
 481                                                 "       move            %a6, %d0                                \n\t"\r
 482                                                 "       cmpi.l          #150, %d0                               \n\t"\r
 483                                                 "       bne                     reg_test_2_error                \n\t"\r
 484                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 485                                                 "       addql           #1, %d0                                 \n\t"\r
 486                                                 "       movel           %d0, ulRegTest2Counter  \n\t"\r
 487                                                 "       bra                     reg_test_2_start                \n\t"\r
 488                                                 "reg_test_2_error:                                              \n\t"\r
 489                                                 "       bra                     reg_test_2_error                \n\t"\r
 490                                         );\r
 491 }\r
 492 /*-----------------------------------------------------------*/\r
 493 \r