git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/main.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.1\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 \r
  29 /*\r
  30  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
  31  * documentation provides more details of the standard demo application tasks.\r
  32  * In addition to the standard demo tasks, the following tasks and tests are\r
  33  * defined and/or created within this file:\r
  34  *\r
  35  * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP\r
  36  * processing is performed in this task.  It manages the WEB server functionality.\r
  37  *\r
  38  * "Check" task -  This only executes every five seconds but has a high priority\r
  39  * to ensure it gets processor time.  Its main function is to check that all the\r
  40  * standard demo tasks are still operational.  An error found in any task will be\r
  41  * latched in the ulErrorCode variable for display through the WEB server (the\r
  42  * error code is displayed at the foot of the table that contains information on\r
  43  * the state of each task).\r
  44  *\r
  45  * "Reg test" tasks - These fill the registers with known values, then check\r
  46  * that each register still contains its expected value.  Each task uses\r
  47  * different values.  The tasks run with very low priority so get preempted very\r
  48  * frequently.  A register containing an unexpected value is indicative of an\r
  49  * error in the context switching mechanism.\r
  50  *\r
  51  */\r
  52 \r
  53 /* Standard includes. */\r
  54 #include <stdio.h>\r
  55 \r
  56 /* Scheduler includes. */\r
  57 #include "FreeRTOS.h"\r
  58 #include "task.h"\r
  59 #include "queue.h"\r
  60 #include "semphr.h"\r
  61 \r
  62 /* Demo app includes. */\r
  63 #include "BlockQ.h"\r
  64 #include "death.h"\r
  65 #include "blocktim.h"\r
  66 #include "flash.h"\r
  67 #include "partest.h"\r
  68 #include "semtest.h"\r
  69 #include "PollQ.h"\r
  70 #include "GenQTest.h"\r
  71 #include "QPeek.h"\r
  72 #include "recmutex.h"\r
  73 #include "IntQueue.h"\r
  74 #include "comtest2.h"\r
  75 \r
  76 /*-----------------------------------------------------------*/\r
  77 \r
  78 /* The time between cycles of the 'check' functionality - as described at the\r
  79 top of this file. */\r
  80 #define mainCHECK_TASK_PERIOD                                   ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
  81 \r
  82 /* Task priorities. */\r
  83 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
  84 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
  85 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
  86 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
  87 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
  88 \r
  89 /* The WEB server task uses more stack than most other tasks because of its\r
  90 reliance on using sprintf(). */\r
  91 #define mainBASIC_WEB_STACK_SIZE                        ( configMINIMAL_STACK_SIZE * 2 )\r
  92 \r
  93 /*\r
  94  * Configure the hardware for the demo.\r
  95  */\r
  96 static void prvSetupHardware( void );\r
  97 \r
  98 /*\r
  99  * Implements the 'check' task functionality as described at the top of this\r
 100  * file.\r
 101  */\r
 102 static void prvCheckTask( void *pvParameters );\r
 103 \r
 104 /*\r
 105  * The task that implements the WEB server.\r
 106  */\r
 107 extern void vuIP_Task( void *pvParameters );\r
 108 \r
 109 /*\r
 110  * Implement the 'Reg test' functionality as described at the top of this file.\r
 111  */\r
 112 static void vRegTest1Task( void *pvParameters );\r
 113 static void vRegTest2Task( void *pvParameters );\r
 114 \r
 115 /*-----------------------------------------------------------*/\r
 116 \r
 117 /* Counters used to detect errors within the reg test tasks. */\r
 118 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 119 \r
 120 /* Any errors that the check task finds in any tasks are latched into\r
 121 ulErrorCode, and then displayed via the WEB server. */\r
 122 static unsigned long ulErrorCode = 0UL;\r
 123 \r
 124 /*-----------------------------------------------------------*/\r
 125 \r
 126 int main( void )\r
 127 {\r
 128         /* Setup the hardware ready for this demo. */\r
 129         prvSetupHardware();\r
 130 \r
 131         /* Create the WEB server task. */\r
 132         xTaskCreate( vuIP_Task, "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
 133 \r
 134         /* Start the standard demo tasks. */\r
 135         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
 136         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
 137     vCreateBlockTimeTasks();\r
 138         vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
 139         vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
 140         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
 141         vStartQueuePeekTasks();\r
 142     vStartRecursiveMutexTasks();\r
 143 \r
 144         /* Start the reg test tasks - defined in this file. */\r
 145         xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
 146         xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 147 \r
 148         /* Create the check task. */\r
 149         xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
 150 \r
 151         /* Start the scheduler. */\r
 152         vTaskStartScheduler();\r
 153 \r
 154     /* Will only get here if there was insufficient heap to create the idle\r
 155     task. */\r
 156         for( ;; );\r
 157 }\r
 158 /*-----------------------------------------------------------*/\r
 159 \r
 160 static void prvCheckTask( void *pvParameters )\r
 161 {\r
 162 unsigned ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 163 portTickType xLastExecutionTime;\r
 164 \r
 165         /* To prevent compiler warnings. */\r
 166         ( void ) pvParameters;\r
 167 \r
 168         /* Initialise the variable used to control our iteration rate prior to\r
 169         its first use. */\r
 170         xLastExecutionTime = xTaskGetTickCount();\r
 171 \r
 172         for( ;; )\r
 173         {\r
 174                 /* Wait until it is time to run the tests again. */\r
 175                 vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD );\r
 176 \r
 177                 /* Has an error been found in any task? */\r
 178                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
 179                 {\r
 180                         ulErrorCode |= 0x01UL;\r
 181                 }\r
 182 \r
 183                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
 184                 {\r
 185                         ulErrorCode |= 0x02UL;\r
 186                 }\r
 187 \r
 188                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
 189                 {\r
 190                         ulErrorCode |= 0x04UL;\r
 191                 }\r
 192 \r
 193                 if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
 194             {\r
 195                 ulErrorCode |= 0x20UL;\r
 196             }\r
 197 \r
 198                 if( xArePollingQueuesStillRunning() != pdTRUE )\r
 199             {\r
 200                 ulErrorCode |= 0x40UL;\r
 201             }\r
 202 \r
 203                 if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
 204                 {\r
 205                         ulErrorCode |= 0x80UL;\r
 206                 }\r
 207 \r
 208             if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
 209             {\r
 210                 ulErrorCode |= 0x100UL;\r
 211             }\r
 212 \r
 213                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
 214                 {\r
 215                         ulErrorCode |= 0x200UL;\r
 216                 }\r
 217 \r
 218                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
 219                 {\r
 220                         ulErrorCode |= 0x200UL;\r
 221                 }\r
 222 \r
 223                 /* Remember the reg test counts so a stall in their values can be\r
 224                 detected next time around. */\r
 225                 ulLastRegTest1Count = ulRegTest1Counter;\r
 226                 ulLastRegTest2Count = ulRegTest2Counter;\r
 227         }\r
 228 }\r
 229 /*-----------------------------------------------------------*/\r
 230 \r
 231 unsigned long ulGetErrorCode( void )\r
 232 {\r
 233         /* Returns the error code for display via the WEB server. */\r
 234         return ulErrorCode;\r
 235 }\r
 236 /*-----------------------------------------------------------*/\r
 237 \r
 238 void prvSetupHardware( void )\r
 239 {\r
 240 __attribute__ ((section(".cfmconfig")))\r
 241 static const unsigned long _cfm[6] = {\r
 242         0, /* KEY_UPPER 0x00000400 */\r
 243         0, /* KEY_LOWER 0x00000404 */\r
 244         0, /* CFMPROT 0x00000408 */\r
 245         0, /* CFMSACC 0x0000040C */\r
 246         0, /* CFMDACC 0x00000410 */\r
 247         0, /* CFMSEC 0x00000414 */\r
 248 };\r
 249 \r
 250         /* Just to stop compiler warnings. */\r
 251         ( void ) _cfm;\r
 252 \r
 253         /* Ensure the watchdog is disabled. */\r
 254         MCF_SCM_CWCR = 0;\r
 255 \r
 256     /* Initialize IPSBAR (0x40000000). */\r
 257         asm volatile(\r
 258                 "move.l  #0x40000000,%d0        \n"\r
 259                 "andi.l  #0xC0000000,%d0        \n"\r
 260                 "add.l   #0x1,%d0                       \n"\r
 261                 "move.l  %d0,0x40000000         "\r
 262         );\r
 263 \r
 264     /* Initialize FLASHBAR (0x00) */\r
 265         asm volatile(\r
 266                 "move.l  #0x00,%d0                      \n"\r
 267                 "andi.l  #0xFFF80000,%d0        \n"\r
 268                 "add.l   #0x41,%d0                      \n"\r
 269                 "movec   %d0,%FLASHBAR          "\r
 270         );\r
 271 \r
 272         portDISABLE_INTERRUPTS();\r
 273 \r
 274         /* RAMBAR. */\r
 275         MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;\r
 276 \r
 277         /* Multiply 25MHz crystal by 12 to get 60MHz clock. */\r
 278         MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;\r
 279         while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
 280         {\r
 281         }\r
 282 \r
 283         /* Setup the port used to toggle LEDs. */\r
 284         vParTestInitialise();\r
 285 }\r
 286 /*-----------------------------------------------------------*/\r
 287 \r
 288 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
 289 {\r
 290         /* This will get called if a stack overflow is detected during the context\r
 291         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
 292         problems within nested interrupts, but only do this for debug purposes as\r
 293         it will increase the context switch time. */\r
 294 \r
 295         ( void ) pxTask;\r
 296         ( void ) pcTaskName;\r
 297 \r
 298         for( ;; );\r
 299 }\r
 300 /*-----------------------------------------------------------*/\r
 301 \r
 302 static void vRegTest1Task( void *pvParameters )\r
 303 {\r
 304         /* Sanity check - did we receive the parameter expected? */\r
 305         if( pvParameters != &ulRegTest1Counter )\r
 306         {\r
 307                 /* Change here so the check task can detect that an error occurred. */\r
 308                 for( ;; );\r
 309         }\r
 310 \r
 311         /* Set all the registers to known values, then check that each retains its\r
 312         expected value - as described at the top of this file.  If an error is\r
 313         found then the loop counter will no longer be incremented allowing the check\r
 314         task to recognise the error. */\r
 315         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
 316                                                 "       moveq           #1, %d0                                 \n\t"\r
 317                                                 "       moveq           #2, %d1                                 \n\t"\r
 318                                                 "       moveq           #3, %d2                                 \n\t"\r
 319                                                 "       moveq           #4, %d3                                 \n\t"\r
 320                                                 "       moveq           #5, %d4                                 \n\t"\r
 321                                                 "       moveq           #6, %d5                                 \n\t"\r
 322                                                 "       moveq           #7, %d6                                 \n\t"\r
 323                                                 "       moveq           #8, %d7                                 \n\t"\r
 324                                                 "       move            #9, %a0                                 \n\t"\r
 325                                                 "       move            #10, %a1                                \n\t"\r
 326                                                 "       move            #11, %a2                                \n\t"\r
 327                                                 "       move            #12, %a3                                \n\t"\r
 328                                                 "       move            #13, %a4                                \n\t"\r
 329                                                 "       move            #14, %a5                                \n\t"\r
 330                                                 "       move            #15, %a6                                \n\t"\r
 331                                                 "                                                                               \n\t"\r
 332                                                 "       cmpi.l          #1, %d0                                 \n\t"\r
 333                                                 "       bne                     reg_test_1_error                \n\t"\r
 334                                                 "       cmpi.l          #2, %d1                                 \n\t"\r
 335                                                 "       bne                     reg_test_1_error                \n\t"\r
 336                                                 "       cmpi.l          #3, %d2                                 \n\t"\r
 337                                                 "       bne                     reg_test_1_error                \n\t"\r
 338                                                 "       cmpi.l          #4, %d3                                 \n\t"\r
 339                                                 "       bne                     reg_test_1_error                \n\t"\r
 340                                                 "       cmpi.l          #5, %d4                                 \n\t"\r
 341                                                 "       bne                     reg_test_1_error                \n\t"\r
 342                                                 "       cmpi.l          #6, %d5                                 \n\t"\r
 343                                                 "       bne                     reg_test_1_error                \n\t"\r
 344                                                 "       cmpi.l          #7, %d6                                 \n\t"\r
 345                                                 "       bne                     reg_test_1_error                \n\t"\r
 346                                                 "       cmpi.l          #8, %d7                                 \n\t"\r
 347                                                 "       bne                     reg_test_1_error                \n\t"\r
 348                                                 "       move            %a0, %d0                                \n\t"\r
 349                                                 "       cmpi.l          #9, %d0                                 \n\t"\r
 350                                                 "       bne                     reg_test_1_error                \n\t"\r
 351                                                 "       move            %a1, %d0                                \n\t"\r
 352                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 353                                                 "       bne                     reg_test_1_error                \n\t"\r
 354                                                 "       move            %a2, %d0                                \n\t"\r
 355                                                 "       cmpi.l          #11, %d0                                \n\t"\r
 356                                                 "       bne                     reg_test_1_error                \n\t"\r
 357                                                 "       move            %a3, %d0                                \n\t"\r
 358                                                 "       cmpi.l          #12, %d0                                \n\t"\r
 359                                                 "       bne                     reg_test_1_error                \n\t"\r
 360                                                 "       move            %a4, %d0                                \n\t"\r
 361                                                 "       cmpi.l          #13, %d0                                \n\t"\r
 362                                                 "       bne                     reg_test_1_error                \n\t"\r
 363                                                 "       move            %a5, %d0                                \n\t"\r
 364                                                 "       cmpi.l          #14, %d0                                \n\t"\r
 365                                                 "       bne                     reg_test_1_error                \n\t"\r
 366                                                 "       move            %a6, %d0                                \n\t"\r
 367                                                 "       cmpi.l          #15, %d0                                \n\t"\r
 368                                                 "       bne                     reg_test_1_error                \n\t"\r
 369                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 370                                                 "       addql           #1, %d0                                 \n\t"\r
 371                                                 "       movel           %d0, ulRegTest1Counter  \n\t"\r
 372                                                 "       bra                     reg_test_1_start                \n\t"\r
 373                                                 "reg_test_1_error:                                              \n\t"\r
 374                                                 "       bra                     reg_test_1_error                \n\t"\r
 375                                         );\r
 376 }\r
 377 /*-----------------------------------------------------------*/\r
 378 \r
 379 static void vRegTest2Task( void *pvParameters )\r
 380 {\r
 381         /* Sanity check - did we receive the parameter expected? */\r
 382         if( pvParameters != &ulRegTest2Counter )\r
 383         {\r
 384                 /* Change here so the check task can detect that an error occurred. */\r
 385                 for( ;; );\r
 386         }\r
 387 \r
 388         /* Set all the registers to known values, then check that each retains its\r
 389         expected value - as described at the top of this file.  If an error is\r
 390         found then the loop counter will no longer be incremented allowing the check\r
 391         task to recognise the error. */\r
 392         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
 393                                                 "       moveq           #10, %d0                                \n\t"\r
 394                                                 "       moveq           #20, %d1                                \n\t"\r
 395                                                 "       moveq           #30, %d2                                \n\t"\r
 396                                                 "       moveq           #40, %d3                                \n\t"\r
 397                                                 "       moveq           #50, %d4                                \n\t"\r
 398                                                 "       moveq           #60, %d5                                \n\t"\r
 399                                                 "       moveq           #70, %d6                                \n\t"\r
 400                                                 "       moveq           #80, %d7                                \n\t"\r
 401                                                 "       move            #90, %a0                                \n\t"\r
 402                                                 "       move            #100, %a1                               \n\t"\r
 403                                                 "       move            #110, %a2                               \n\t"\r
 404                                                 "       move            #120, %a3                               \n\t"\r
 405                                                 "       move            #130, %a4                               \n\t"\r
 406                                                 "       move            #140, %a5                               \n\t"\r
 407                                                 "       move            #150, %a6                               \n\t"\r
 408                                                 "                                                                               \n\t"\r
 409                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 410                                                 "       bne                     reg_test_2_error                \n\t"\r
 411                                                 "       cmpi.l          #20, %d1                                \n\t"\r
 412                                                 "       bne                     reg_test_2_error                \n\t"\r
 413                                                 "       cmpi.l          #30, %d2                                \n\t"\r
 414                                                 "       bne                     reg_test_2_error                \n\t"\r
 415                                                 "       cmpi.l          #40, %d3                                \n\t"\r
 416                                                 "       bne                     reg_test_2_error                \n\t"\r
 417                                                 "       cmpi.l          #50, %d4                                \n\t"\r
 418                                                 "       bne                     reg_test_2_error                \n\t"\r
 419                                                 "       cmpi.l          #60, %d5                                \n\t"\r
 420                                                 "       bne                     reg_test_2_error                \n\t"\r
 421                                                 "       cmpi.l          #70, %d6                                \n\t"\r
 422                                                 "       bne                     reg_test_2_error                \n\t"\r
 423                                                 "       cmpi.l          #80, %d7                                \n\t"\r
 424                                                 "       bne                     reg_test_2_error                \n\t"\r
 425                                                 "       move            %a0, %d0                                \n\t"\r
 426                                                 "       cmpi.l          #90, %d0                                \n\t"\r
 427                                                 "       bne                     reg_test_2_error                \n\t"\r
 428                                                 "       move            %a1, %d0                                \n\t"\r
 429                                                 "       cmpi.l          #100, %d0                               \n\t"\r
 430                                                 "       bne                     reg_test_2_error                \n\t"\r
 431                                                 "       move            %a2, %d0                                \n\t"\r
 432                                                 "       cmpi.l          #110, %d0                               \n\t"\r
 433                                                 "       bne                     reg_test_2_error                \n\t"\r
 434                                                 "       move            %a3, %d0                                \n\t"\r
 435                                                 "       cmpi.l          #120, %d0                               \n\t"\r
 436                                                 "       bne                     reg_test_2_error                \n\t"\r
 437                                                 "       move            %a4, %d0                                \n\t"\r
 438                                                 "       cmpi.l          #130, %d0                               \n\t"\r
 439                                                 "       bne                     reg_test_2_error                \n\t"\r
 440                                                 "       move            %a5, %d0                                \n\t"\r
 441                                                 "       cmpi.l          #140, %d0                               \n\t"\r
 442                                                 "       bne                     reg_test_2_error                \n\t"\r
 443                                                 "       move            %a6, %d0                                \n\t"\r
 444                                                 "       cmpi.l          #150, %d0                               \n\t"\r
 445                                                 "       bne                     reg_test_2_error                \n\t"\r
 446                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 447                                                 "       addql           #1, %d0                                 \n\t"\r
 448                                                 "       movel           %d0, ulRegTest2Counter  \n\t"\r
 449                                                 "       bra                     reg_test_2_start                \n\t"\r
 450                                                 "reg_test_2_error:                                              \n\t"\r
 451                                                 "       bra                     reg_test_2_error                \n\t"\r
 452                                         );\r
 453 }\r
 454 /*-----------------------------------------------------------*/\r
 455 \r