git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/main.c

   1 /*\r
   2     FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 \r
  66 /*\r
  67  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
  68  * documentation provides more details of the standard demo application tasks.\r
  69  * In addition to the standard demo tasks, the following tasks and tests are\r
  70  * defined and/or created within this file:\r
  71  *\r
  72  * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP\r
  73  * processing is performed in this task.  It manages the WEB server functionality.\r
  74  *\r
  75  * "Check" task -  This only executes every five seconds but has a high priority\r
  76  * to ensure it gets processor time.  Its main function is to check that all the\r
  77  * standard demo tasks are still operational.  An error found in any task will be\r
  78  * latched in the ulErrorCode variable for display through the WEB server (the\r
  79  * error code is displayed at the foot of the table that contains information on\r
  80  * the state of each task).\r
  81  *\r
  82  * "Reg test" tasks - These fill the registers with known values, then check\r
  83  * that each register still contains its expected value.  Each task uses\r
  84  * different values.  The tasks run with very low priority so get preempted very\r
  85  * frequently.  A register containing an unexpected value is indicative of an\r
  86  * error in the context switching mechanism.\r
  87  *\r
  88  */\r
  89 \r
  90 /* Standard includes. */\r
  91 #include <stdio.h>\r
  92 \r
  93 /* Scheduler includes. */\r
  94 #include "FreeRTOS.h"\r
  95 #include "task.h"\r
  96 #include "queue.h"\r
  97 #include "semphr.h"\r
  98 \r
  99 /* Demo app includes. */\r
 100 #include "BlockQ.h"\r
 101 #include "death.h"\r
 102 #include "blocktim.h"\r
 103 #include "flash.h"\r
 104 #include "partest.h"\r
 105 #include "semtest.h"\r
 106 #include "PollQ.h"\r
 107 #include "GenQTest.h"\r
 108 #include "QPeek.h"\r
 109 #include "recmutex.h"\r
 110 #include "IntQueue.h"\r
 111 #include "comtest2.h"\r
 112 \r
 113 /*-----------------------------------------------------------*/\r
 114 \r
 115 /* The time between cycles of the 'check' functionality - as described at the\r
 116 top of this file. */\r
 117 #define mainCHECK_TASK_PERIOD                                   ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
 118 \r
 119 /* Task priorities. */\r
 120 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
 121 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
 122 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
 123 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
 124 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
 125 \r
 126 /* The WEB server task uses more stack than most other tasks because of its\r
 127 reliance on using sprintf(). */\r
 128 #define mainBASIC_WEB_STACK_SIZE                        ( configMINIMAL_STACK_SIZE * 2 )\r
 129 \r
 130 /*\r
 131  * Configure the hardware for the demo.\r
 132  */\r
 133 static void prvSetupHardware( void );\r
 134 \r
 135 /*\r
 136  * Implements the 'check' task functionality as described at the top of this\r
 137  * file.\r
 138  */\r
 139 static void prvCheckTask( void *pvParameters );\r
 140 \r
 141 /*\r
 142  * The task that implements the WEB server.\r
 143  */\r
 144 extern void vuIP_Task( void *pvParameters );\r
 145 \r
 146 /*\r
 147  * Implement the 'Reg test' functionality as described at the top of this file.\r
 148  */\r
 149 static void vRegTest1Task( void *pvParameters );\r
 150 static void vRegTest2Task( void *pvParameters );\r
 151 \r
 152 /*-----------------------------------------------------------*/\r
 153 \r
 154 /* Counters used to detect errors within the reg test tasks. */\r
 155 static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 156 \r
 157 /* Any errors that the check task finds in any tasks are latched into \r
 158 ulErrorCode, and then displayed via the WEB server. */\r
 159 static unsigned portLONG ulErrorCode = 0UL;\r
 160 \r
 161 /*-----------------------------------------------------------*/\r
 162 \r
 163 int main( void )\r
 164 {\r
 165         /* Setup the hardware ready for this demo. */\r
 166         prvSetupHardware();\r
 167 \r
 168         /* Create the WEB server task. */\r
 169         xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
 170 \r
 171         /* Start the standard demo tasks. */\r
 172         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
 173         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
 174     vCreateBlockTimeTasks();\r
 175         vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
 176         vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
 177         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
 178         vStartQueuePeekTasks();\r
 179     vStartRecursiveMutexTasks();\r
 180 \r
 181         /* Start the reg test tasks - defined in this file. */\r
 182         xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
 183         xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 184 \r
 185         /* Create the check task. */\r
 186         xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
 187 \r
 188         /* Start the scheduler. */\r
 189         vTaskStartScheduler();\r
 190 \r
 191     /* Will only get here if there was insufficient heap to create the idle\r
 192     task. */\r
 193         for( ;; );\r
 194 }\r
 195 /*-----------------------------------------------------------*/\r
 196 \r
 197 static void prvCheckTask( void *pvParameters )\r
 198 {\r
 199 unsigned ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 200 portTickType xLastExecutionTime;\r
 201 \r
 202         /* To prevent compiler warnings. */\r
 203         ( void ) pvParameters;\r
 204 \r
 205         /* Initialise the variable used to control our iteration rate prior to\r
 206         its first use. */\r
 207         xLastExecutionTime = xTaskGetTickCount();\r
 208 \r
 209         for( ;; )\r
 210         {\r
 211                 /* Wait until it is time to run the tests again. */\r
 212                 vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD );\r
 213 \r
 214                 /* Has an error been found in any task? */\r
 215                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
 216                 {\r
 217                         ulErrorCode |= 0x01UL;\r
 218                 }\r
 219 \r
 220                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
 221                 {\r
 222                         ulErrorCode |= 0x02UL;\r
 223                 }\r
 224 \r
 225                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
 226                 {\r
 227                         ulErrorCode |= 0x04UL;\r
 228                 }\r
 229 \r
 230                 if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
 231             {\r
 232                 ulErrorCode |= 0x20UL;\r
 233             }\r
 234 \r
 235                 if( xArePollingQueuesStillRunning() != pdTRUE )\r
 236             {\r
 237                 ulErrorCode |= 0x40UL;\r
 238             }\r
 239 \r
 240                 if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
 241                 {\r
 242                         ulErrorCode |= 0x80UL;\r
 243                 }\r
 244 \r
 245             if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
 246             {\r
 247                 ulErrorCode |= 0x100UL;\r
 248             }\r
 249 \r
 250                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
 251                 {\r
 252                         ulErrorCode |= 0x200UL;\r
 253                 }\r
 254 \r
 255                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
 256                 {\r
 257                         ulErrorCode |= 0x200UL;\r
 258                 }\r
 259 \r
 260                 /* Remember the reg test counts so a stall in their values can be\r
 261                 detected next time around. */\r
 262                 ulLastRegTest1Count = ulRegTest1Counter;\r
 263                 ulLastRegTest2Count = ulRegTest2Counter;\r
 264         }\r
 265 }\r
 266 /*-----------------------------------------------------------*/\r
 267 \r
 268 unsigned portLONG ulGetErrorCode( void )\r
 269 {\r
 270         /* Returns the error code for display via the WEB server. */\r
 271         return ulErrorCode;\r
 272 }\r
 273 /*-----------------------------------------------------------*/\r
 274 \r
 275 void prvSetupHardware( void )\r
 276 {\r
 277 __attribute__ ((section(".cfmconfig")))\r
 278 static const unsigned long _cfm[6] = {\r
 279         0, /* KEY_UPPER 0x00000400 */\r
 280         0, /* KEY_LOWER 0x00000404 */\r
 281         0, /* CFMPROT 0x00000408 */\r
 282         0, /* CFMSACC 0x0000040C */\r
 283         0, /* CFMDACC 0x00000410 */\r
 284         0, /* CFMSEC 0x00000414 */\r
 285 };\r
 286 \r
 287         /* Just to stop compiler warnings. */\r
 288         ( void ) _cfm;\r
 289 \r
 290         /* Ensure the watchdog is disabled. */\r
 291         MCF_SCM_CWCR = 0;\r
 292 \r
 293     /* Initialize IPSBAR (0x40000000). */\r
 294         asm volatile(\r
 295                 "move.l  #0x40000000,%d0        \n"\r
 296                 "andi.l  #0xC0000000,%d0        \n"\r
 297                 "add.l   #0x1,%d0                       \n"\r
 298                 "move.l  %d0,0x40000000         "\r
 299         );\r
 300 \r
 301     /* Initialize FLASHBAR (0x00) */\r
 302         asm volatile(\r
 303                 "move.l  #0x00,%d0                      \n"\r
 304                 "andi.l  #0xFFF80000,%d0        \n"\r
 305                 "add.l   #0x41,%d0                      \n"\r
 306                 "movec   %d0,%FLASHBAR          "\r
 307         );\r
 308 \r
 309         portDISABLE_INTERRUPTS();\r
 310 \r
 311         /* RAMBAR. */\r
 312         MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;\r
 313 \r
 314         /* Multiply 25MHz crystal by 12 to get 60MHz clock. */\r
 315         MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;\r
 316         while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
 317         {\r
 318         }\r
 319 \r
 320         /* Setup the port used to toggle LEDs. */\r
 321         vParTestInitialise();\r
 322 }\r
 323 /*-----------------------------------------------------------*/\r
 324 \r
 325 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
 326 {\r
 327         /* This will get called if a stack overflow is detected during the context\r
 328         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
 329         problems within nested interrupts, but only do this for debug purposes as\r
 330         it will increase the context switch time. */\r
 331 \r
 332         ( void ) pxTask;\r
 333         ( void ) pcTaskName;\r
 334 \r
 335         for( ;; );\r
 336 }\r
 337 /*-----------------------------------------------------------*/\r
 338 \r
 339 static void vRegTest1Task( void *pvParameters )\r
 340 {\r
 341         /* Sanity check - did we receive the parameter expected? */\r
 342         if( pvParameters != &ulRegTest1Counter )\r
 343         {\r
 344                 /* Change here so the check task can detect that an error occurred. */\r
 345                 for( ;; );\r
 346         }\r
 347 \r
 348         /* Set all the registers to known values, then check that each retains its\r
 349         expected value - as described at the top of this file.  If an error is\r
 350         found then the loop counter will no longer be incremented allowing the check\r
 351         task to recognise the error. */\r
 352         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
 353                                                 "       moveq           #1, %d0                                 \n\t"\r
 354                                                 "       moveq           #2, %d1                                 \n\t"\r
 355                                                 "       moveq           #3, %d2                                 \n\t"\r
 356                                                 "       moveq           #4, %d3                                 \n\t"\r
 357                                                 "       moveq           #5, %d4                                 \n\t"\r
 358                                                 "       moveq           #6, %d5                                 \n\t"\r
 359                                                 "       moveq           #7, %d6                                 \n\t"\r
 360                                                 "       moveq           #8, %d7                                 \n\t"\r
 361                                                 "       move            #9, %a0                                 \n\t"\r
 362                                                 "       move            #10, %a1                                \n\t"\r
 363                                                 "       move            #11, %a2                                \n\t"\r
 364                                                 "       move            #12, %a3                                \n\t"\r
 365                                                 "       move            #13, %a4                                \n\t"\r
 366                                                 "       move            #14, %a5                                \n\t"\r
 367                                                 "       move            #15, %a6                                \n\t"\r
 368                                                 "                                                                               \n\t"\r
 369                                                 "       cmpi.l          #1, %d0                                 \n\t"\r
 370                                                 "       bne                     reg_test_1_error                \n\t"\r
 371                                                 "       cmpi.l          #2, %d1                                 \n\t"\r
 372                                                 "       bne                     reg_test_1_error                \n\t"\r
 373                                                 "       cmpi.l          #3, %d2                                 \n\t"\r
 374                                                 "       bne                     reg_test_1_error                \n\t"\r
 375                                                 "       cmpi.l          #4, %d3                                 \n\t"\r
 376                                                 "       bne                     reg_test_1_error                \n\t"\r
 377                                                 "       cmpi.l          #5, %d4                                 \n\t"\r
 378                                                 "       bne                     reg_test_1_error                \n\t"\r
 379                                                 "       cmpi.l          #6, %d5                                 \n\t"\r
 380                                                 "       bne                     reg_test_1_error                \n\t"\r
 381                                                 "       cmpi.l          #7, %d6                                 \n\t"\r
 382                                                 "       bne                     reg_test_1_error                \n\t"\r
 383                                                 "       cmpi.l          #8, %d7                                 \n\t"\r
 384                                                 "       bne                     reg_test_1_error                \n\t"\r
 385                                                 "       move            %a0, %d0                                \n\t"\r
 386                                                 "       cmpi.l          #9, %d0                                 \n\t"\r
 387                                                 "       bne                     reg_test_1_error                \n\t"\r
 388                                                 "       move            %a1, %d0                                \n\t"\r
 389                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 390                                                 "       bne                     reg_test_1_error                \n\t"\r
 391                                                 "       move            %a2, %d0                                \n\t"\r
 392                                                 "       cmpi.l          #11, %d0                                \n\t"\r
 393                                                 "       bne                     reg_test_1_error                \n\t"\r
 394                                                 "       move            %a3, %d0                                \n\t"\r
 395                                                 "       cmpi.l          #12, %d0                                \n\t"\r
 396                                                 "       bne                     reg_test_1_error                \n\t"\r
 397                                                 "       move            %a4, %d0                                \n\t"\r
 398                                                 "       cmpi.l          #13, %d0                                \n\t"\r
 399                                                 "       bne                     reg_test_1_error                \n\t"\r
 400                                                 "       move            %a5, %d0                                \n\t"\r
 401                                                 "       cmpi.l          #14, %d0                                \n\t"\r
 402                                                 "       bne                     reg_test_1_error                \n\t"\r
 403                                                 "       move            %a6, %d0                                \n\t"\r
 404                                                 "       cmpi.l          #15, %d0                                \n\t"\r
 405                                                 "       bne                     reg_test_1_error                \n\t"\r
 406                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 407                                                 "       addql           #1, %d0                                 \n\t"\r
 408                                                 "       movel           %d0, ulRegTest1Counter  \n\t"\r
 409                                                 "       bra                     reg_test_1_start                \n\t"\r
 410                                                 "reg_test_1_error:                                              \n\t"\r
 411                                                 "       bra                     reg_test_1_error                \n\t"\r
 412                                         );\r
 413 }\r
 414 /*-----------------------------------------------------------*/\r
 415 \r
 416 static void vRegTest2Task( void *pvParameters )\r
 417 {\r
 418         /* Sanity check - did we receive the parameter expected? */\r
 419         if( pvParameters != &ulRegTest2Counter )\r
 420         {\r
 421                 /* Change here so the check task can detect that an error occurred. */\r
 422                 for( ;; );\r
 423         }\r
 424 \r
 425         /* Set all the registers to known values, then check that each retains its\r
 426         expected value - as described at the top of this file.  If an error is\r
 427         found then the loop counter will no longer be incremented allowing the check\r
 428         task to recognise the error. */\r
 429         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
 430                                                 "       moveq           #10, %d0                                \n\t"\r
 431                                                 "       moveq           #20, %d1                                \n\t"\r
 432                                                 "       moveq           #30, %d2                                \n\t"\r
 433                                                 "       moveq           #40, %d3                                \n\t"\r
 434                                                 "       moveq           #50, %d4                                \n\t"\r
 435                                                 "       moveq           #60, %d5                                \n\t"\r
 436                                                 "       moveq           #70, %d6                                \n\t"\r
 437                                                 "       moveq           #80, %d7                                \n\t"\r
 438                                                 "       move            #90, %a0                                \n\t"\r
 439                                                 "       move            #100, %a1                               \n\t"\r
 440                                                 "       move            #110, %a2                               \n\t"\r
 441                                                 "       move            #120, %a3                               \n\t"\r
 442                                                 "       move            #130, %a4                               \n\t"\r
 443                                                 "       move            #140, %a5                               \n\t"\r
 444                                                 "       move            #150, %a6                               \n\t"\r
 445                                                 "                                                                               \n\t"\r
 446                                                 "       cmpi.l          #10, %d0                                \n\t"\r
 447                                                 "       bne                     reg_test_2_error                \n\t"\r
 448                                                 "       cmpi.l          #20, %d1                                \n\t"\r
 449                                                 "       bne                     reg_test_2_error                \n\t"\r
 450                                                 "       cmpi.l          #30, %d2                                \n\t"\r
 451                                                 "       bne                     reg_test_2_error                \n\t"\r
 452                                                 "       cmpi.l          #40, %d3                                \n\t"\r
 453                                                 "       bne                     reg_test_2_error                \n\t"\r
 454                                                 "       cmpi.l          #50, %d4                                \n\t"\r
 455                                                 "       bne                     reg_test_2_error                \n\t"\r
 456                                                 "       cmpi.l          #60, %d5                                \n\t"\r
 457                                                 "       bne                     reg_test_2_error                \n\t"\r
 458                                                 "       cmpi.l          #70, %d6                                \n\t"\r
 459                                                 "       bne                     reg_test_2_error                \n\t"\r
 460                                                 "       cmpi.l          #80, %d7                                \n\t"\r
 461                                                 "       bne                     reg_test_2_error                \n\t"\r
 462                                                 "       move            %a0, %d0                                \n\t"\r
 463                                                 "       cmpi.l          #90, %d0                                \n\t"\r
 464                                                 "       bne                     reg_test_2_error                \n\t"\r
 465                                                 "       move            %a1, %d0                                \n\t"\r
 466                                                 "       cmpi.l          #100, %d0                               \n\t"\r
 467                                                 "       bne                     reg_test_2_error                \n\t"\r
 468                                                 "       move            %a2, %d0                                \n\t"\r
 469                                                 "       cmpi.l          #110, %d0                               \n\t"\r
 470                                                 "       bne                     reg_test_2_error                \n\t"\r
 471                                                 "       move            %a3, %d0                                \n\t"\r
 472                                                 "       cmpi.l          #120, %d0                               \n\t"\r
 473                                                 "       bne                     reg_test_2_error                \n\t"\r
 474                                                 "       move            %a4, %d0                                \n\t"\r
 475                                                 "       cmpi.l          #130, %d0                               \n\t"\r
 476                                                 "       bne                     reg_test_2_error                \n\t"\r
 477                                                 "       move            %a5, %d0                                \n\t"\r
 478                                                 "       cmpi.l          #140, %d0                               \n\t"\r
 479                                                 "       bne                     reg_test_2_error                \n\t"\r
 480                                                 "       move            %a6, %d0                                \n\t"\r
 481                                                 "       cmpi.l          #150, %d0                               \n\t"\r
 482                                                 "       bne                     reg_test_2_error                \n\t"\r
 483                                                 "       movel           ulRegTest1Counter, %d0  \n\t"\r
 484                                                 "       addql           #1, %d0                                 \n\t"\r
 485                                                 "       movel           %d0, ulRegTest2Counter  \n\t"\r
 486                                                 "       bra                     reg_test_2_start                \n\t"\r
 487                                                 "reg_test_2_error:                                              \n\t"\r
 488                                                 "       bra                     reg_test_2_error                \n\t"\r
 489                                         );\r
 490 }\r
 491 /*-----------------------------------------------------------*/\r
 492 \r