1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2008/02/26 Revision: 0.1
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7 * (c) Copyright UNIS, spol. s r.o. 1997-2008
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12 * http : www.processorexpert.com
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13 * mail : info@processorexpert.com
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16 #ifndef __MCF52259_TMR_H__
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17 #define __MCF52259_TMR_H__
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20 /*********************************************************************
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22 * Timer Module (TMR)
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24 *********************************************************************/
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26 /* Register read/write macros */
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27 #define MCF_TMR0_TMR (*(vuint16*)(0x40000400))
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28 #define MCF_TMR0_TRR (*(vuint16*)(0x40000404))
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29 #define MCF_TMR0_TCR (*(vuint16*)(0x40000408))
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30 #define MCF_TMR0_TCN (*(vuint16*)(0x4000040C))
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31 #define MCF_TMR0_TER (*(vuint8 *)(0x40000411))
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33 #define MCF_TMR1_TMR (*(vuint16*)(0x40000440))
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34 #define MCF_TMR1_TRR (*(vuint16*)(0x40000444))
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35 #define MCF_TMR1_TCR (*(vuint16*)(0x40000448))
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36 #define MCF_TMR1_TCN (*(vuint16*)(0x4000044C))
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37 #define MCF_TMR1_TER (*(vuint8 *)(0x40000451))
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39 #define MCF_TMR2_TMR (*(vuint16*)(0x40000480))
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40 #define MCF_TMR2_TRR (*(vuint16*)(0x40000484))
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41 #define MCF_TMR2_TCR (*(vuint16*)(0x40000488))
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42 #define MCF_TMR2_TCN (*(vuint16*)(0x4000048C))
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43 #define MCF_TMR2_TER (*(vuint8 *)(0x40000491))
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45 #define MCF_TMR3_TMR (*(vuint16*)(0x400004C0))
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46 #define MCF_TMR3_TRR (*(vuint16*)(0x400004C4))
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47 #define MCF_TMR3_TCR (*(vuint16*)(0x400004C8))
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48 #define MCF_TMR3_TCN (*(vuint16*)(0x400004CC))
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49 #define MCF_TMR3_TER (*(vuint8 *)(0x400004D1))
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51 #define MCF_TMR_TMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
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52 #define MCF_TMR_TRR(x) (*(vuint16*)(0x40000404 + ((x)*0x40)))
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53 #define MCF_TMR_TCR(x) (*(vuint16*)(0x40000408 + ((x)*0x40)))
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54 #define MCF_TMR_TCN(x) (*(vuint16*)(0x4000040C + ((x)*0x40)))
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55 #define MCF_TMR_TER(x) (*(vuint8 *)(0x40000411 + ((x)*0x40)))
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58 /* Bit definitions and macros for MCF_TMR_TMR */
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59 #define MCF_TMR_TMR_RST (0x1)
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60 #define MCF_TMR_TMR_CLK(x) (((x)&0x3)<<0x1)
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61 #define MCF_TMR_TMR_CLK_STOP (0)
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62 #define MCF_TMR_TMR_CLK_SYSCLK (0x2)
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63 #define MCF_TMR_TMR_CLK_DIV16 (0x4)
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64 #define MCF_TMR_TMR_CLK_TIN (0x6)
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65 #define MCF_TMR_TMR_FRR (0x8)
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66 #define MCF_TMR_TMR_ORI (0x10)
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67 #define MCF_TMR_TMR_OM (0x20)
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68 #define MCF_TMR_TMR_CE(x) (((x)&0x3)<<0x6)
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69 #define MCF_TMR_TMR_CE_NONE (0)
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70 #define MCF_TMR_TMR_CE_RISE (0x40)
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71 #define MCF_TMR_TMR_CE_FALL (0x80)
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72 #define MCF_TMR_TMR_CE_ANY (0xC0)
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73 #define MCF_TMR_TMR_PS(x) (((x)&0xFF)<<0x8)
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75 /* Bit definitions and macros for MCF_TMR_TRR */
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76 #define MCF_TMR_TRR_REF(x) (((x)&0xFFFF)<<0)
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78 /* Bit definitions and macros for MCF_TMR_TCR */
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79 #define MCF_TMR_TCR_CAP(x) (((x)&0xFFFF)<<0)
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81 /* Bit definitions and macros for MCF_TMR_TCN */
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82 #define MCF_TMR_TCN_COUNT(x) (((x)&0xFFFF)<<0)
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84 /* Bit definitions and macros for MCF_TMR_TER */
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85 #define MCF_TMR_TER_CAP (0x1)
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86 #define MCF_TMR_TER_REF (0x2)
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89 #endif /* __MCF52259_TMR_H__ */
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