1 //*****************************************************************************
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3 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
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5 // Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. You may not combine
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14 // this software with "viral" open-source software in order to form a larger
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15 // program. Any use in violation of the foregoing restrictions may subject
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16 // the user to criminal sanctions under applicable laws, as well as to civil
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17 // liability for the breach of the terms and conditions of this license.
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19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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27 //*****************************************************************************
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29 #ifndef __HW_I2C_H__
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30 #define __HW_I2C_H__
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32 //*****************************************************************************
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34 // The following are defines for the offsets between the I2C master and slave
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37 //*****************************************************************************
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38 #define I2C_O_MSA 0x00000000 // I2C Master Slave Address
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39 #define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
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40 #define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
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41 #define I2C_O_MCS 0x00000004 // I2C Master Control/Status
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42 #define I2C_O_SDR 0x00000008 // I2C Slave Data
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43 #define I2C_O_MDR 0x00000008 // I2C Master Data
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44 #define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
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45 #define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
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46 #define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
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47 #define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
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48 #define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
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49 #define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
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51 #define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
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52 #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
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54 #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
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55 #define I2C_O_MCR 0x00000020 // I2C Master Configuration
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57 //*****************************************************************************
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59 // The following are defines for the bit fields in the I2C_O_MSA register.
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61 //*****************************************************************************
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62 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
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63 #define I2C_MSA_RS 0x00000001 // Receive not Send
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64 #define I2C_MSA_SA_S 1
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66 //*****************************************************************************
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68 // The following are defines for the bit fields in the I2C_O_SOAR register.
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70 //*****************************************************************************
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71 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
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72 #define I2C_SOAR_OAR_S 0
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74 //*****************************************************************************
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76 // The following are defines for the bit fields in the I2C_O_SCSR register.
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78 //*****************************************************************************
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79 #define I2C_SCSR_FBR 0x00000004 // First Byte Received.
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80 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
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81 #define I2C_SCSR_DA 0x00000001 // Device Active.
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82 #define I2C_SCSR_RREQ 0x00000001 // Receive Request.
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84 //*****************************************************************************
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86 // The following are defines for the bit fields in the I2C_O_MCS register.
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88 //*****************************************************************************
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89 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
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90 #define I2C_MCS_IDLE 0x00000020 // I2C Idle.
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91 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
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92 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
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93 #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
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94 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
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95 #define I2C_MCS_STOP 0x00000004 // Generate STOP.
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96 #define I2C_MCS_START 0x00000002 // Generate START.
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97 #define I2C_MCS_ERROR 0x00000002 // Error.
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98 #define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
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99 #define I2C_MCS_BUSY 0x00000001 // I2C Busy.
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101 //*****************************************************************************
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103 // The following are defines for the bit fields in the I2C_O_SDR register.
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105 //*****************************************************************************
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106 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
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107 #define I2C_SDR_DATA_S 0
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109 //*****************************************************************************
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111 // The following are defines for the bit fields in the I2C_O_MDR register.
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113 //*****************************************************************************
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114 #define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
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115 #define I2C_MDR_DATA_S 0
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117 //*****************************************************************************
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119 // The following are defines for the bit fields in the I2C_O_MTPR register.
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121 //*****************************************************************************
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122 #define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
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123 #define I2C_MTPR_TPR_S 0
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125 //*****************************************************************************
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127 // The following are defines for the bit fields in the I2C_O_SIMR register.
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129 //*****************************************************************************
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130 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.
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131 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.
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132 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.
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134 //*****************************************************************************
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136 // The following are defines for the bit fields in the I2C_O_SRIS register.
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138 //*****************************************************************************
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139 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
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141 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
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143 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.
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145 //*****************************************************************************
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147 // The following are defines for the bit fields in the I2C_O_MIMR register.
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149 //*****************************************************************************
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150 #define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
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152 //*****************************************************************************
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154 // The following are defines for the bit fields in the I2C_O_MRIS register.
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156 //*****************************************************************************
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157 #define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
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159 //*****************************************************************************
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161 // The following are defines for the bit fields in the I2C_O_SMIS register.
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163 //*****************************************************************************
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164 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
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166 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
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168 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.
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170 //*****************************************************************************
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172 // The following are defines for the bit fields in the I2C_O_SICR register.
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174 //*****************************************************************************
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175 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.
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176 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.
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177 #define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.
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179 //*****************************************************************************
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181 // The following are defines for the bit fields in the I2C_O_MMIS register.
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183 //*****************************************************************************
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184 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
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186 //*****************************************************************************
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188 // The following are defines for the bit fields in the I2C_O_MICR register.
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190 //*****************************************************************************
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191 #define I2C_MICR_IC 0x00000001 // Interrupt Clear.
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193 //*****************************************************************************
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195 // The following are defines for the bit fields in the I2C_O_MCR register.
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197 //*****************************************************************************
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198 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
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199 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
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200 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
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202 //*****************************************************************************
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204 // The following definitions are deprecated.
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206 //*****************************************************************************
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209 //*****************************************************************************
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211 // The following are deprecated defines for the offsets between the I2C master
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212 // and slave registers.
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214 //*****************************************************************************
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215 #define I2C_O_SLAVE 0x00000800 // Offset from master to slave
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217 //*****************************************************************************
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219 // The following are deprecated defines for the I2C master register offsets.
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221 //*****************************************************************************
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222 #define I2C_MASTER_O_SA 0x00000000 // Slave address register
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223 #define I2C_MASTER_O_CS 0x00000004 // Control and Status register
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224 #define I2C_MASTER_O_DR 0x00000008 // Data register
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225 #define I2C_MASTER_O_TPR 0x0000000C // Timer period register
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226 #define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
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227 #define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
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228 #define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
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229 #define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
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230 #define I2C_MASTER_O_CR 0x00000020 // Configuration register
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232 //*****************************************************************************
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234 // The following are deprecated defines for the I2C slave register offsets.
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236 //*****************************************************************************
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237 #define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
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238 #define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
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239 #define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
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240 #define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
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241 #define I2C_SLAVE_O_DR 0x00000008 // Data register
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242 #define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
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243 #define I2C_SLAVE_O_OAR 0x00000000 // Own address register
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245 //*****************************************************************************
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247 // The following are deprecated defines for the bit fields in the I2C master
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248 // slave address register.
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250 //*****************************************************************************
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251 #define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
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252 #define I2C_MASTER_SA_RS 0x00000001 // Receive/send
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253 #define I2C_MASTER_SA_SA_SHIFT 1
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255 //*****************************************************************************
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257 // The following are deprecated defines for the bit fields in the I2C Master
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258 // Control and Status register.
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260 //*****************************************************************************
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261 #define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
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262 #define I2C_MASTER_CS_IDLE 0x00000020 // Idle
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263 #define I2C_MASTER_CS_ERR_MASK 0x0000001C
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264 #define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
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265 #define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
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266 #define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
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267 #define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
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268 #define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
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269 #define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
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270 #define I2C_MASTER_CS_STOP 0x00000004 // Stop
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271 #define I2C_MASTER_CS_START 0x00000002 // Start
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272 #define I2C_MASTER_CS_RUN 0x00000001 // Run
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274 //*****************************************************************************
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276 // The following are deprecated defines for the values used in determining the
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277 // contents of the I2C Master Timer Period register.
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279 //*****************************************************************************
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280 #define I2C_SCL_FAST 400000 // SCL fast frequency
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281 #define I2C_SCL_STANDARD 100000 // SCL standard frequency
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282 #define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
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283 #define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
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284 #define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
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286 //*****************************************************************************
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288 // The following are deprecated defines for the bit fields in the I2C Master
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289 // Interrupt Mask register.
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291 //*****************************************************************************
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292 #define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
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294 //*****************************************************************************
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296 // The following are deprecated defines for the bit fields in the I2C Master
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297 // Raw Interrupt Status register.
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299 //*****************************************************************************
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300 #define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
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302 //*****************************************************************************
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304 // The following are deprecated defines for the bit fields in the I2C Master
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305 // Masked Interrupt Status register.
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307 //*****************************************************************************
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308 #define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
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310 //*****************************************************************************
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312 // The following are deprecated defines for the bit fields in the I2C Master
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313 // Interrupt Clear register.
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315 //*****************************************************************************
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316 #define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
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318 //*****************************************************************************
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320 // The following are deprecated defines for the bit fields in the I2C Master
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321 // Configuration register.
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323 //*****************************************************************************
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324 #define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
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325 #define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
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326 #define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
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328 //*****************************************************************************
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330 // The following are deprecated defines for the bit fields in the I2C Slave Own
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331 // Address register.
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333 //*****************************************************************************
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334 #define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
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336 //*****************************************************************************
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338 // The following are deprecated defines for the bit fields in the I2C Slave
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339 // Control/Status register.
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341 //*****************************************************************************
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342 #define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
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343 #define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
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344 #define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
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345 #define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
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347 //*****************************************************************************
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349 // The following are deprecated defines for the bit fields in the I2C Slave
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350 // Interrupt Mask register.
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352 //*****************************************************************************
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353 #define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
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355 //*****************************************************************************
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357 // The following are deprecated defines for the bit fields in the I2C Slave Raw
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358 // Interrupt Status register.
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360 //*****************************************************************************
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361 #define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
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363 //*****************************************************************************
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365 // The following are deprecated defines for the bit fields in the I2C Slave
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366 // Masked Interrupt Status register.
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368 //*****************************************************************************
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369 #define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
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371 //*****************************************************************************
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373 // The following are deprecated defines for the bit fields in the I2C Slave
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374 // Interrupt Clear register.
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376 //*****************************************************************************
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377 #define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
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379 //*****************************************************************************
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381 // The following are deprecated defines for the bit fields in the I2C_O_SIMR
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384 //*****************************************************************************
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385 #define I2C_SIMR_IM 0x00000001 // Interrupt Mask.
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387 //*****************************************************************************
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389 // The following are deprecated defines for the bit fields in the I2C_O_SRIS
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392 //*****************************************************************************
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393 #define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.
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395 //*****************************************************************************
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397 // The following are deprecated defines for the bit fields in the I2C_O_SMIS
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400 //*****************************************************************************
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401 #define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.
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403 //*****************************************************************************
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405 // The following are deprecated defines for the bit fields in the I2C_O_SICR
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408 //*****************************************************************************
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409 #define I2C_SICR_IC 0x00000001 // Clear Interrupt.
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413 #endif // __HW_I2C_H__
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