1 //*****************************************************************************
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3 // hw_timer.h - Defines and macros used when accessing the timer.
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5 // Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. You may not combine
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14 // this software with "viral" open-source software in order to form a larger
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15 // program. Any use in violation of the foregoing restrictions may subject
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16 // the user to criminal sanctions under applicable laws, as well as to civil
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17 // liability for the breach of the terms and conditions of this license.
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19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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27 //*****************************************************************************
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29 #ifndef __HW_TIMER_H__
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30 #define __HW_TIMER_H__
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32 //*****************************************************************************
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34 // The following are defines for the timer register offsets.
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36 //*****************************************************************************
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37 #define TIMER_O_CFG 0x00000000 // Configuration register
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38 #define TIMER_O_TAMR 0x00000004 // TimerA mode register
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39 #define TIMER_O_TBMR 0x00000008 // TimerB mode register
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40 #define TIMER_O_CTL 0x0000000C // Control register
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41 #define TIMER_O_IMR 0x00000018 // Interrupt mask register
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42 #define TIMER_O_RIS 0x0000001C // Interrupt status register
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43 #define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
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44 #define TIMER_O_ICR 0x00000024 // Interrupt clear register
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45 #define TIMER_O_TAILR 0x00000028 // TimerA interval load register
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46 #define TIMER_O_TBILR 0x0000002C // TimerB interval load register
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47 #define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
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48 #define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
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49 #define TIMER_O_TAPR 0x00000038 // TimerA prescale register
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50 #define TIMER_O_TBPR 0x0000003C // TimerB prescale register
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51 #define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
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52 #define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
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53 #define TIMER_O_TAR 0x00000048 // TimerA register
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54 #define TIMER_O_TBR 0x0000004C // TimerB register
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56 //*****************************************************************************
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58 // The following are defines for the bit fields in the TIMER_CFG register.
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60 //*****************************************************************************
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61 #define TIMER_CFG_M 0x00000007 // GPTM Configuration.
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62 #define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
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63 #define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
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64 #define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
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66 //*****************************************************************************
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68 // The following are defines for the bit fields in the TIMER_CTL register.
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70 //*****************************************************************************
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71 #define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
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72 #define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
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73 #define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
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74 #define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
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75 #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
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76 #define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
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77 #define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
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78 #define TIMER_CTL_TBEN 0x00000100 // TimerB enable
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79 #define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
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80 #define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
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81 #define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
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82 #define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
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83 #define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
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84 #define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
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85 #define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
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86 #define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
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87 #define TIMER_CTL_TAEN 0x00000001 // TimerA enable
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89 //*****************************************************************************
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91 // The following are defines for the bit fields in the TIMER_IMR register.
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93 //*****************************************************************************
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94 #define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
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95 #define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
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96 #define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
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97 #define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
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98 #define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
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99 #define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
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100 #define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
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102 //*****************************************************************************
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104 // The following are defines for the bit fields in the TIMER_RIS register.
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106 //*****************************************************************************
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107 #define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
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108 #define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
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109 #define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
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110 #define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
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111 #define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
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112 #define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
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113 #define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
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115 //*****************************************************************************
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117 // The following are defines for the bit fields in the TIMER_ICR register.
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119 //*****************************************************************************
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120 #define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
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121 #define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
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122 #define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
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123 #define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
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124 #define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
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125 #define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
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126 #define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
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128 //*****************************************************************************
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130 // The following are defines for the bit fields in the TIMER_TAILR register.
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132 //*****************************************************************************
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133 #define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
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135 #define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
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137 #define TIMER_TAILR_TAILRH_S 16
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138 #define TIMER_TAILR_TAILRL_S 0
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140 //*****************************************************************************
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142 // The following are defines for the bit fields in the TIMER_TBILR register.
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144 //*****************************************************************************
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145 #define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
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147 #define TIMER_TBILR_TBILRL_S 0
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149 //*****************************************************************************
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151 // The following are defines for the bit fields in the TIMER_TAMATCHR register.
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153 //*****************************************************************************
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154 #define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
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155 #define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
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156 #define TIMER_TAMATCHR_TAMRH_S 16
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157 #define TIMER_TAMATCHR_TAMRL_S 0
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159 //*****************************************************************************
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161 // The following are defines for the bit fields in the TIMER_TBMATCHR register.
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163 //*****************************************************************************
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164 #define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
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165 #define TIMER_TBMATCHR_TBMRL_S 0
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167 //*****************************************************************************
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169 // The following are defines for the bit fields in the TIMER_TAR register.
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171 //*****************************************************************************
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172 #define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
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173 #define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
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174 #define TIMER_TAR_TARH_S 16
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175 #define TIMER_TAR_TARL_S 0
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177 //*****************************************************************************
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179 // The following are defines for the bit fields in the TIMER_TBR register.
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181 //*****************************************************************************
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182 #define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
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183 #define TIMER_TBR_TBRL_S 0
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185 //*****************************************************************************
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187 // The following are defines for the bit fields in the TIMER_O_TAMR register.
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189 //*****************************************************************************
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190 #define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
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192 #define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
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193 #define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
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194 #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.
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195 #define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.
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196 #define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.
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198 //*****************************************************************************
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200 // The following are defines for the bit fields in the TIMER_O_TBMR register.
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202 //*****************************************************************************
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203 #define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
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205 #define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
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206 #define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
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207 #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.
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208 #define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.
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209 #define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.
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211 //*****************************************************************************
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213 // The following are defines for the bit fields in the TIMER_O_MIS register.
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215 //*****************************************************************************
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216 #define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
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218 #define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
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220 #define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
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222 #define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
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223 #define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
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225 #define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
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227 #define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
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230 //*****************************************************************************
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232 // The following are defines for the bit fields in the TIMER_O_TAPR register.
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234 //*****************************************************************************
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235 #define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
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236 #define TIMER_TAPR_TAPSR_S 0
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238 //*****************************************************************************
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240 // The following are defines for the bit fields in the TIMER_O_TBPR register.
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242 //*****************************************************************************
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243 #define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
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244 #define TIMER_TBPR_TBPSR_S 0
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246 //*****************************************************************************
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248 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
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250 //*****************************************************************************
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251 #define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
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252 #define TIMER_TAPMR_TAPSMR_S 0
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254 //*****************************************************************************
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256 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
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258 //*****************************************************************************
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259 #define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
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260 #define TIMER_TBPMR_TBPSMR_S 0
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262 //*****************************************************************************
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264 // The following definitions are deprecated.
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266 //*****************************************************************************
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269 //*****************************************************************************
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271 // The following are deprecated defines for the reset values of the timer
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274 //*****************************************************************************
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275 #define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
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276 #define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
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277 #define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
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278 #define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
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279 #define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
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280 #define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
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281 #define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
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282 #define TIMER_RV_CFG 0x00000000 // Configuration register RV
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283 #define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
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284 #define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
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285 #define TIMER_RV_CTL 0x00000000 // Control register RV
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286 #define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
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287 #define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
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288 #define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
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289 #define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
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290 #define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
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291 #define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
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292 #define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
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294 //*****************************************************************************
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296 // The following are deprecated defines for the bit fields in the TIMER_CFG
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299 //*****************************************************************************
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300 #define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
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302 //*****************************************************************************
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304 // The following are deprecated defines for the bit fields in the TIMER_TnMR
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307 //*****************************************************************************
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308 #define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
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309 #define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
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310 #define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
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311 #define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
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312 #define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
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313 #define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
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315 //*****************************************************************************
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317 // The following are deprecated defines for the bit fields in the TIMER_CTL
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320 //*****************************************************************************
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321 #define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
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322 #define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
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324 //*****************************************************************************
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326 // The following are deprecated defines for the bit fields in the TIMER_MIS
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329 //*****************************************************************************
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330 #define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
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331 #define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
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332 #define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
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333 #define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
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334 #define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
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335 #define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
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336 #define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
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338 //*****************************************************************************
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340 // The following are deprecated defines for the bit fields in the TIMER_TAILR
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343 //*****************************************************************************
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344 #define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
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345 #define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
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347 //*****************************************************************************
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349 // The following are deprecated defines for the bit fields in the TIMER_TBILR
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352 //*****************************************************************************
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353 #define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
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355 //*****************************************************************************
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357 // The following are deprecated defines for the bit fields in the
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358 // TIMER_TAMATCHR register.
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360 //*****************************************************************************
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361 #define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
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362 #define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
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364 //*****************************************************************************
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366 // The following are deprecated defines for the bit fields in the
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367 // TIMER_TBMATCHR register.
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369 //*****************************************************************************
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370 #define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
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372 //*****************************************************************************
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374 // The following are deprecated defines for the bit fields in the TIMER_TnPR
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377 //*****************************************************************************
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378 #define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
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380 //*****************************************************************************
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382 // The following are deprecated defines for the bit fields in the TIMER_TnPMR
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385 //*****************************************************************************
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386 #define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
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388 //*****************************************************************************
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390 // The following are deprecated defines for the bit fields in the TIMER_TAR
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393 //*****************************************************************************
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394 #define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
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395 #define TIMER_TAR_TARL 0x0000FFFF // TimerA value
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397 //*****************************************************************************
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399 // The following are deprecated defines for the bit fields in the TIMER_TBR
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402 //*****************************************************************************
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403 #define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
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407 #endif // __HW_TIMER_H__
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