1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_tim1.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file contains all the functions prototypes for the
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6 * TIM1 firmware library.
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7 ********************************************************************************
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12 ********************************************************************************
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13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 *******************************************************************************/
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef __STM32F10x_TIM1_H
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23 #define __STM32F10x_TIM1_H
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25 /* Includes ------------------------------------------------------------------*/
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26 #include "stm32f10x_map.h"
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28 /* Exported types ------------------------------------------------------------*/
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30 /* TIM1 Time Base Init structure definition */
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34 u16 TIM1_CounterMode;
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36 u16 TIM1_ClockDivision;
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37 u8 TIM1_RepetitionCounter;
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38 } TIM1_TimeBaseInitTypeDef;
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40 /* TIM1 Output Compare Init structure definition */
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44 u16 TIM1_OutputState;
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45 u16 TIM1_OutputNState;
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47 u16 TIM1_OCPolarity;
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48 u16 TIM1_OCNPolarity;
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49 u16 TIM1_OCIdleState;
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50 u16 TIM1_OCNIdleState;
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51 } TIM1_OCInitTypeDef;
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53 /* TIM1 Input Capture Init structure definition */
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57 u16 TIM1_ICPolarity;
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58 u16 TIM1_ICSelection;
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59 u16 TIM1_ICPrescaler;
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61 } TIM1_ICInitTypeDef;
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63 /* BDTR structure definition */
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68 u16 TIM1_LOCKLevel;
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71 u16 TIM1_BreakPolarity;
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72 u16 TIM1_AutomaticOutput;
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73 } TIM1_BDTRInitTypeDef;
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75 /* Exported constants --------------------------------------------------------*/
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76 /* TIM1 Output Compare and PWM modes ----------------------------------------*/
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77 #define TIM1_OCMode_Timing ((u16)0x0000)
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78 #define TIM1_OCMode_Active ((u16)0x0010)
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79 #define TIM1_OCMode_Inactive ((u16)0x0020)
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80 #define TIM1_OCMode_Toggle ((u16)0x0030)
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81 #define TIM1_OCMode_PWM1 ((u16)0x0060)
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82 #define TIM1_OCMode_PWM2 ((u16)0x0070)
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84 #define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \
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85 (MODE == TIM1_OCMode_Active) || \
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86 (MODE == TIM1_OCMode_Inactive) || \
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87 (MODE == TIM1_OCMode_Toggle)|| \
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88 (MODE == TIM1_OCMode_PWM1) || \
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89 (MODE == TIM1_OCMode_PWM2))
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91 #define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \
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92 (MODE == TIM1_OCMode_Active) || \
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93 (MODE == TIM1_OCMode_Inactive) || \
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94 (MODE == TIM1_OCMode_Toggle)|| \
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95 (MODE == TIM1_OCMode_PWM1) || \
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96 (MODE == TIM1_OCMode_PWM2) || \
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97 (MODE == TIM1_ForcedAction_Active) || \
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98 (MODE == TIM1_ForcedAction_InActive))
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99 /* TIM1 One Pulse Mode ------------------------------------------------------*/
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100 #define TIM1_OPMode_Single ((u16)0x0001)
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101 #define TIM1_OPMode_Repetitive ((u16)0x0000)
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103 #define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \
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104 (MODE == TIM1_OPMode_Repetitive))
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106 /* TIM1 Channel -------------------------------------------------------------*/
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107 #define TIM1_Channel_1 ((u16)0x0000)
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108 #define TIM1_Channel_2 ((u16)0x0001)
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109 #define TIM1_Channel_3 ((u16)0x0002)
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110 #define TIM1_Channel_4 ((u16)0x0003)
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112 #define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
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113 (CHANNEL == TIM1_Channel_2) || \
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114 (CHANNEL == TIM1_Channel_3) || \
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115 (CHANNEL == TIM1_Channel_4))
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117 #define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
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118 (CHANNEL == TIM1_Channel_2))
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120 #define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
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121 (CHANNEL == TIM1_Channel_2) || \
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122 (CHANNEL == TIM1_Channel_3))
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123 /* TIM1 Clock Division CKD --------------------------------------------------*/
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124 #define TIM1_CKD_DIV1 ((u16)0x0000)
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125 #define TIM1_CKD_DIV2 ((u16)0x0100)
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126 #define TIM1_CKD_DIV4 ((u16)0x0200)
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128 #define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \
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129 (DIV == TIM1_CKD_DIV2) || \
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130 (DIV == TIM1_CKD_DIV4))
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132 /* TIM1 Counter Mode --------------------------------------------------------*/
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133 #define TIM1_CounterMode_Up ((u16)0x0000)
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134 #define TIM1_CounterMode_Down ((u16)0x0010)
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135 #define TIM1_CounterMode_CenterAligned1 ((u16)0x0020)
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136 #define TIM1_CounterMode_CenterAligned2 ((u16)0x0040)
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137 #define TIM1_CounterMode_CenterAligned3 ((u16)0x0060)
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139 #define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \
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140 (MODE == TIM1_CounterMode_Down) || \
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141 (MODE == TIM1_CounterMode_CenterAligned1) || \
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142 (MODE == TIM1_CounterMode_CenterAligned2) || \
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143 (MODE == TIM1_CounterMode_CenterAligned3))
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145 /* TIM1 Output Compare Polarity ---------------------------------------------*/
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146 #define TIM1_OCPolarity_High ((u16)0x0000)
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147 #define TIM1_OCPolarity_Low ((u16)0x0001)
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149 #define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \
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150 (POLARITY == TIM1_OCPolarity_Low))
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152 /* TIM1 Output Compare N Polarity -------------------------------------------*/
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153 #define TIM1_OCNPolarity_High ((u16)0x0000)
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154 #define TIM1_OCNPolarity_Low ((u16)0x0001)
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156 #define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \
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157 (POLARITY == TIM1_OCNPolarity_Low))
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159 /* TIM1 Output Compare states -----------------------------------------------*/
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160 #define TIM1_OutputState_Disable ((u16)0x0000)
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161 #define TIM1_OutputState_Enable ((u16)0x0001)
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163 #define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \
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164 (STATE == TIM1_OutputState_Enable))
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166 /* TIM1 Output Compare N States ---------------------------------------------*/
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167 #define TIM1_OutputNState_Disable ((u16)0x0000)
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168 #define TIM1_OutputNState_Enable ((u16)0x0001)
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170 #define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \
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171 (STATE == TIM1_OutputNState_Enable))
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173 /* Break Input enable/disable -----------------------------------------------*/
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174 #define TIM1_Break_Enable ((u16)0x1000)
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175 #define TIM1_Break_Disable ((u16)0x0000)
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177 #define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \
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178 (STATE == TIM1_Break_Disable))
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180 /* Break Polarity -----------------------------------------------------------*/
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181 #define TIM1_BreakPolarity_Low ((u16)0x0000)
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182 #define TIM1_BreakPolarity_High ((u16)0x2000)
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184 #define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \
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185 (POLARITY == TIM1_BreakPolarity_High))
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187 /* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/
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188 #define TIM1_AutomaticOutput_Enable ((u16)0x4000)
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189 #define TIM1_AutomaticOutput_Disable ((u16)0x0000)
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191 #define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \
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192 (STATE == TIM1_AutomaticOutput_Disable))
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193 /* Lock levels --------------------------------------------------------------*/
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194 #define TIM1_LOCKLevel_OFF ((u16)0x0000)
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195 #define TIM1_LOCKLevel_1 ((u16)0x0100)
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196 #define TIM1_LOCKLevel_2 ((u16)0x0200)
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197 #define TIM1_LOCKLevel_3 ((u16)0x0300)
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199 #define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \
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200 (LEVEL == TIM1_LOCKLevel_1) || \
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201 (LEVEL == TIM1_LOCKLevel_2) || \
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202 (LEVEL == TIM1_LOCKLevel_3))
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204 /* OSSI: Off-State Selection for Idle mode states ---------------------------*/
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205 #define TIM1_OSSIState_Enable ((u16)0x0400)
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206 #define TIM1_OSSIState_Disable ((u16)0x0000)
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208 #define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \
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209 (STATE == TIM1_OSSIState_Disable))
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211 /* OSSR: Off-State Selection for Run mode states ----------------------------*/
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212 #define TIM1_OSSRState_Enable ((u16)0x0800)
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213 #define TIM1_OSSRState_Disable ((u16)0x0000)
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215 #define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \
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216 (STATE == TIM1_OSSRState_Disable))
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218 /* TIM1 Output Compare Idle State -------------------------------------------*/
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219 #define TIM1_OCIdleState_Set ((u16)0x0001)
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220 #define TIM1_OCIdleState_Reset ((u16)0x0000)
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222 #define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \
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223 (STATE == TIM1_OCIdleState_Reset))
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225 /* TIM1 Output Compare N Idle State -----------------------------------------*/
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226 #define TIM1_OCNIdleState_Set ((u16)0x0001)
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227 #define TIM1_OCNIdleState_Reset ((u16)0x0000)
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229 #define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \
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230 (STATE == TIM1_OCNIdleState_Reset))
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232 /* TIM1 Input Capture Polarity ----------------------------------------------*/
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233 #define TIM1_ICPolarity_Rising ((u16)0x0000)
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234 #define TIM1_ICPolarity_Falling ((u16)0x0001)
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236 #define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \
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237 (POLARITY == TIM1_ICPolarity_Falling))
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239 /* TIM1 Input Capture Selection ---------------------------------------------*/
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240 #define TIM1_ICSelection_DirectTI ((u16)0x0001)
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241 #define TIM1_ICSelection_IndirectTI ((u16)0x0002)
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242 #define TIM1_ICSelection_TRGI ((u16)0x0003)
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244 #define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \
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245 (SELECTION == TIM1_ICSelection_IndirectTI) || \
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246 (SELECTION == TIM1_ICSelection_TRGI))
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248 /* TIM1 Input Capture Prescaler ---------------------------------------------*/
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249 #define TIM1_ICPSC_DIV1 ((u16)0x0000)
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250 #define TIM1_ICPSC_DIV2 ((u16)0x0004)
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251 #define TIM1_ICPSC_DIV4 ((u16)0x0008)
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252 #define TIM1_ICPSC_DIV8 ((u16)0x000C)
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254 #define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \
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255 (PRESCALER == TIM1_ICPSC_DIV2) || \
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256 (PRESCALER == TIM1_ICPSC_DIV4) || \
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257 (PRESCALER == TIM1_ICPSC_DIV8))
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259 /* TIM1 Input Capture Filer Value ---------------------------------------------*/
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260 #define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
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262 /* TIM1 interrupt sources ---------------------------------------------------*/
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263 #define TIM1_IT_Update ((u16)0x0001)
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264 #define TIM1_IT_CC1 ((u16)0x0002)
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265 #define TIM1_IT_CC2 ((u16)0x0004)
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266 #define TIM1_IT_CC3 ((u16)0x0008)
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267 #define TIM1_IT_CC4 ((u16)0x0010)
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268 #define TIM1_IT_COM ((u16)0x0020)
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269 #define TIM1_IT_Trigger ((u16)0x0040)
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270 #define TIM1_IT_Break ((u16)0x0080)
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272 #define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))
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274 #define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \
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275 (IT == TIM1_IT_CC1) || \
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276 (IT == TIM1_IT_CC2) || \
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277 (IT == TIM1_IT_CC3) || \
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278 (IT == TIM1_IT_CC4) || \
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279 (IT == TIM1_IT_COM) || \
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280 (IT == TIM1_IT_Trigger) || \
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281 (IT == TIM1_IT_Break))
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283 /* TIM1 DMA Base address ----------------------------------------------------*/
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284 #define TIM1_DMABase_CR1 ((u16)0x0000)
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285 #define TIM1_DMABase_CR2 ((u16)0x0001)
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286 #define TIM1_DMABase_SMCR ((u16)0x0002)
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287 #define TIM1_DMABase_DIER ((u16)0x0003)
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288 #define TIM1_DMABase_SR ((u16)0x0004)
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289 #define TIM1_DMABase_EGR ((u16)0x0005)
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290 #define TIM1_DMABase_CCMR1 ((u16)0x0006)
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291 #define TIM1_DMABase_CCMR2 ((u16)0x0007)
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292 #define TIM1_DMABase_CCER ((u16)0x0008)
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293 #define TIM1_DMABase_CNT ((u16)0x0009)
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294 #define TIM1_DMABase_PSC ((u16)0x000A)
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295 #define TIM1_DMABase_ARR ((u16)0x000B)
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296 #define TIM1_DMABase_RCR ((u16)0x000C)
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297 #define TIM1_DMABase_CCR1 ((u16)0x000D)
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298 #define TIM1_DMABase_CCR2 ((u16)0x000E)
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299 #define TIM1_DMABase_CCR3 ((u16)0x000F)
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300 #define TIM1_DMABase_CCR4 ((u16)0x0010)
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301 #define TIM1_DMABase_BDTR ((u16)0x0011)
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302 #define TIM1_DMABase_DCR ((u16)0x0012)
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304 #define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \
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305 (BASE == TIM1_DMABase_CR2) || \
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306 (BASE == TIM1_DMABase_SMCR) || \
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307 (BASE == TIM1_DMABase_DIER) || \
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308 (BASE == TIM1_DMABase_SR) || \
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309 (BASE == TIM1_DMABase_EGR) || \
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310 (BASE == TIM1_DMABase_CCMR1) || \
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311 (BASE == TIM1_DMABase_CCMR2) || \
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312 (BASE == TIM1_DMABase_CCER) || \
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313 (BASE == TIM1_DMABase_CNT) || \
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314 (BASE == TIM1_DMABase_PSC) || \
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315 (BASE == TIM1_DMABase_ARR) || \
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316 (BASE == TIM1_DMABase_RCR) || \
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317 (BASE == TIM1_DMABase_CCR1) || \
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318 (BASE == TIM1_DMABase_CCR2) || \
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319 (BASE == TIM1_DMABase_CCR3) || \
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320 (BASE == TIM1_DMABase_CCR4) || \
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321 (BASE == TIM1_DMABase_BDTR) || \
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322 (BASE == TIM1_DMABase_DCR))
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324 /* TIM1 DMA Burst Length ----------------------------------------------------*/
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325 #define TIM1_DMABurstLength_1Byte ((u16)0x0000)
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326 #define TIM1_DMABurstLength_2Bytes ((u16)0x0100)
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327 #define TIM1_DMABurstLength_3Bytes ((u16)0x0200)
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328 #define TIM1_DMABurstLength_4Bytes ((u16)0x0300)
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329 #define TIM1_DMABurstLength_5Bytes ((u16)0x0400)
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330 #define TIM1_DMABurstLength_6Bytes ((u16)0x0500)
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331 #define TIM1_DMABurstLength_7Bytes ((u16)0x0600)
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332 #define TIM1_DMABurstLength_8Bytes ((u16)0x0700)
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333 #define TIM1_DMABurstLength_9Bytes ((u16)0x0800)
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334 #define TIM1_DMABurstLength_10Bytes ((u16)0x0900)
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335 #define TIM1_DMABurstLength_11Bytes ((u16)0x0A00)
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336 #define TIM1_DMABurstLength_12Bytes ((u16)0x0B00)
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337 #define TIM1_DMABurstLength_13Bytes ((u16)0x0C00)
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338 #define TIM1_DMABurstLength_14Bytes ((u16)0x0D00)
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339 #define TIM1_DMABurstLength_15Bytes ((u16)0x0E00)
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340 #define TIM1_DMABurstLength_16Bytes ((u16)0x0F00)
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341 #define TIM1_DMABurstLength_17Bytes ((u16)0x1000)
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342 #define TIM1_DMABurstLength_18Bytes ((u16)0x1100)
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344 #define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \
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345 (LENGTH == TIM1_DMABurstLength_2Bytes) || \
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346 (LENGTH == TIM1_DMABurstLength_3Bytes) || \
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347 (LENGTH == TIM1_DMABurstLength_4Bytes) || \
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348 (LENGTH == TIM1_DMABurstLength_5Bytes) || \
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349 (LENGTH == TIM1_DMABurstLength_6Bytes) || \
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350 (LENGTH == TIM1_DMABurstLength_7Bytes) || \
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351 (LENGTH == TIM1_DMABurstLength_8Bytes) || \
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352 (LENGTH == TIM1_DMABurstLength_9Bytes) || \
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353 (LENGTH == TIM1_DMABurstLength_10Bytes) || \
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354 (LENGTH == TIM1_DMABurstLength_11Bytes) || \
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355 (LENGTH == TIM1_DMABurstLength_12Bytes) || \
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356 (LENGTH == TIM1_DMABurstLength_13Bytes) || \
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357 (LENGTH == TIM1_DMABurstLength_14Bytes) || \
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358 (LENGTH == TIM1_DMABurstLength_15Bytes) || \
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359 (LENGTH == TIM1_DMABurstLength_16Bytes) || \
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360 (LENGTH == TIM1_DMABurstLength_17Bytes) || \
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361 (LENGTH == TIM1_DMABurstLength_18Bytes))
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363 /* TIM1 DMA sources ---------------------------------------------------------*/
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364 #define TIM1_DMA_Update ((u16)0x0100)
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365 #define TIM1_DMA_CC1 ((u16)0x0200)
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366 #define TIM1_DMA_CC2 ((u16)0x0400)
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367 #define TIM1_DMA_CC3 ((u16)0x0800)
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368 #define TIM1_DMA_CC4 ((u16)0x1000)
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369 #define TIM1_DMA_COM ((u16)0x2000)
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370 #define TIM1_DMA_Trigger ((u16)0x4000)
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372 #define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))
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374 /* TIM1 External Trigger Prescaler ------------------------------------------*/
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375 #define TIM1_ExtTRGPSC_OFF ((u16)0x0000)
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376 #define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000)
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377 #define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000)
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378 #define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000)
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380 #define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \
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381 (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \
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382 (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \
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383 (PRESCALER == TIM1_ExtTRGPSC_DIV8))
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385 /* TIM1 Internal Trigger Selection ------------------------------------------*/
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386 #define TIM1_TS_ITR0 ((u16)0x0000)
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387 #define TIM1_TS_ITR1 ((u16)0x0010)
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388 #define TIM1_TS_ITR2 ((u16)0x0020)
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389 #define TIM1_TS_ITR3 ((u16)0x0030)
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390 #define TIM1_TS_TI1F_ED ((u16)0x0040)
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391 #define TIM1_TS_TI1FP1 ((u16)0x0050)
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392 #define TIM1_TS_TI2FP2 ((u16)0x0060)
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393 #define TIM1_TS_ETRF ((u16)0x0070)
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395 #define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
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396 (SELECTION == TIM1_TS_ITR1) || \
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397 (SELECTION == TIM1_TS_ITR2) || \
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398 (SELECTION == TIM1_TS_ITR3) || \
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399 (SELECTION == TIM1_TS_TI1F_ED) || \
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400 (SELECTION == TIM1_TS_TI1FP1) || \
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401 (SELECTION == TIM1_TS_TI2FP2) || \
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402 (SELECTION == TIM1_TS_ETRF))
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404 #define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
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405 (SELECTION == TIM1_TS_ITR1) || \
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406 (SELECTION == TIM1_TS_ITR2) || \
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407 (SELECTION == TIM1_TS_ITR3))
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409 #define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \
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410 (SELECTION == TIM1_TS_TI1FP1) || \
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411 (SELECTION == TIM1_TS_TI2FP2))
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413 /* TIM1 External Trigger Polarity -------------------------------------------*/
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414 #define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000)
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415 #define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000)
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417 #define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \
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418 (POLARITY == TIM1_ExtTRGPolarity_NonInverted))
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420 /* TIM1 Prescaler Reload Mode -----------------------------------------------*/
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421 #define TIM1_PSCReloadMode_Update ((u16)0x0000)
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422 #define TIM1_PSCReloadMode_Immediate ((u16)0x0001)
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424 #define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \
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425 (RELOAD == TIM1_PSCReloadMode_Immediate))
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427 /* TIM1 Forced Action -------------------------------------------------------*/
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428 #define TIM1_ForcedAction_Active ((u16)0x0050)
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429 #define TIM1_ForcedAction_InActive ((u16)0x0040)
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431 #define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \
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432 (ACTION == TIM1_ForcedAction_InActive))
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434 /* TIM1 Encoder Mode --------------------------------------------------------*/
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435 #define TIM1_EncoderMode_TI1 ((u16)0x0001)
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436 #define TIM1_EncoderMode_TI2 ((u16)0x0002)
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437 #define TIM1_EncoderMode_TI12 ((u16)0x0003)
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439 #define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \
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440 (MODE == TIM1_EncoderMode_TI2) || \
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441 (MODE == TIM1_EncoderMode_TI12))
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443 /* TIM1 Event Source --------------------------------------------------------*/
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444 #define TIM1_EventSource_Update ((u16)0x0001)
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445 #define TIM1_EventSource_CC1 ((u16)0x0002)
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446 #define TIM1_EventSource_CC2 ((u16)0x0004)
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447 #define TIM1_EventSource_CC3 ((u16)0x0008)
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448 #define TIM1_EventSource_CC4 ((u16)0x0010)
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449 #define TIM1_EventSource_COM ((u16)0x0020)
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450 #define TIM1_EventSource_Trigger ((u16)0x0040)
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451 #define TIM1_EventSource_Break ((u16)0x0080)
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453 #define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))
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456 /* TIM1 Update Source -------------------------------------------------------*/
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457 #define TIM1_UpdateSource_Global ((u16)0x0000)
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458 #define TIM1_UpdateSource_Regular ((u16)0x0001)
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460 #define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \
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461 (SOURCE == TIM1_UpdateSource_Regular))
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463 /* TIM1 Ouput Compare Preload State ------------------------------------------*/
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464 #define TIM1_OCPreload_Enable ((u16)0x0001)
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465 #define TIM1_OCPreload_Disable ((u16)0x0000)
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467 #define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \
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468 (STATE == TIM1_OCPreload_Disable))
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470 /* TIM1 Ouput Compare Fast State ---------------------------------------------*/
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471 #define TIM1_OCFast_Enable ((u16)0x0001)
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472 #define TIM1_OCFast_Disable ((u16)0x0000)
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474 #define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \
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475 (STATE == TIM1_OCFast_Disable))
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477 /* TIM1 Trigger Output Source -----------------------------------------------*/
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478 #define TIM1_TRGOSource_Reset ((u16)0x0000)
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479 #define TIM1_TRGOSource_Enable ((u16)0x0010)
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480 #define TIM1_TRGOSource_Update ((u16)0x0020)
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481 #define TIM1_TRGOSource_OC1 ((u16)0x0030)
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482 #define TIM1_TRGOSource_OC1Ref ((u16)0x0040)
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483 #define TIM1_TRGOSource_OC2Ref ((u16)0x0050)
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484 #define TIM1_TRGOSource_OC3Ref ((u16)0x0060)
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485 #define TIM1_TRGOSource_OC4Ref ((u16)0x0070)
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487 #define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \
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488 (SOURCE == TIM1_TRGOSource_Enable) || \
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489 (SOURCE == TIM1_TRGOSource_Update) || \
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490 (SOURCE == TIM1_TRGOSource_OC1) || \
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491 (SOURCE == TIM1_TRGOSource_OC1Ref) || \
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492 (SOURCE == TIM1_TRGOSource_OC2Ref) || \
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493 (SOURCE == TIM1_TRGOSource_OC3Ref) || \
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494 (SOURCE == TIM1_TRGOSource_OC4Ref))
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496 /* TIM1 Slave Mode ----------------------------------------------------------*/
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497 #define TIM1_SlaveMode_Reset ((u16)0x0004)
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498 #define TIM1_SlaveMode_Gated ((u16)0x0005)
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499 #define TIM1_SlaveMode_Trigger ((u16)0x0006)
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500 #define TIM1_SlaveMode_External1 ((u16)0x0007)
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502 #define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \
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503 (MODE == TIM1_SlaveMode_Gated) || \
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504 (MODE == TIM1_SlaveMode_Trigger) || \
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505 (MODE == TIM1_SlaveMode_External1))
\r
507 /* TIM1 TIx External Clock Source -------------------------------------------*/
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508 #define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050)
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509 #define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060)
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510 #define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
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512 #define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \
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513 (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \
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514 (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))
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516 /* TIM1 Master Slave Mode ---------------------------------------------------*/
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517 #define TIM1_MasterSlaveMode_Enable ((u16)0x0001)
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518 #define TIM1_MasterSlaveMode_Disable ((u16)0x0000)
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520 #define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \
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521 (STATE == TIM1_MasterSlaveMode_Disable))
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523 /* TIM1 Flags ---------------------------------------------------------------*/
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524 #define TIM1_FLAG_Update ((u16)0x0001)
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525 #define TIM1_FLAG_CC1 ((u16)0x0002)
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526 #define TIM1_FLAG_CC2 ((u16)0x0004)
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527 #define TIM1_FLAG_CC3 ((u16)0x0008)
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528 #define TIM1_FLAG_CC4 ((u16)0x0010)
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529 #define TIM1_FLAG_COM ((u16)0x0020)
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530 #define TIM1_FLAG_Trigger ((u16)0x0040)
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531 #define TIM1_FLAG_Break ((u16)0x0080)
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532 #define TIM1_FLAG_CC1OF ((u16)0x0200)
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533 #define TIM1_FLAG_CC2OF ((u16)0x0400)
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534 #define TIM1_FLAG_CC3OF ((u16)0x0800)
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535 #define TIM1_FLAG_CC4OF ((u16)0x1000)
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537 #define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \
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538 (FLAG == TIM1_FLAG_CC1) || \
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539 (FLAG == TIM1_FLAG_CC2) || \
\r
540 (FLAG == TIM1_FLAG_CC3) || \
\r
541 (FLAG == TIM1_FLAG_CC4) || \
\r
542 (FLAG == TIM1_FLAG_COM) || \
\r
543 (FLAG == TIM1_FLAG_Trigger) || \
\r
544 (FLAG == TIM1_FLAG_Break) || \
\r
545 (FLAG == TIM1_FLAG_CC1OF) || \
\r
546 (FLAG == TIM1_FLAG_CC2OF) || \
\r
547 (FLAG == TIM1_FLAG_CC3OF) || \
\r
548 (FLAG == TIM1_FLAG_CC4OF))
\r
550 #define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))
\r
553 /* Exported macro ------------------------------------------------------------*/
\r
554 /* Exported functions --------------------------------------------------------*/
\r
556 void TIM1_DeInit(void);
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557 void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
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558 void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
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559 void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
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560 void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
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561 void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
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562 void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);
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563 void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
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564 void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
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565 void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
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566 void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
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567 void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
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568 void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);
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569 void TIM1_Cmd(FunctionalState NewState);
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570 void TIM1_CtrlPWMOutputs(FunctionalState Newstate);
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571 void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);
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572 void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);
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573 void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);
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574 void TIM1_InternalClockConfig(void);
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575 void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
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577 void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
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579 void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);
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580 void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity,
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582 void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);
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583 void TIM1_UpdateDisableConfig(FunctionalState Newstate);
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584 void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);
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585 void TIM1_SelectHallSensor(FunctionalState Newstate);
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586 void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);
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587 void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);
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588 void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);
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589 void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);
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590 void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
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591 u16 TIM1_IC2Polarity);
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592 void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);
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593 void TIM1_CounterModeConfig(u16 TIM1_CounterMode);
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594 void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);
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595 void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);
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596 void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);
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597 void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);
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598 void TIM1_ARRPreloadConfig(FunctionalState Newstate);
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599 void TIM1_SelectCOM(FunctionalState Newstate);
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600 void TIM1_SelectCCDMA(FunctionalState Newstate);
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601 void TIM1_CCPreloadControl(FunctionalState Newstate);
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602 void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);
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603 void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);
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604 void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);
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605 void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);
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606 void TIM1_OC1FastConfig(u16 TIM1_OCFast);
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607 void TIM1_OC2FastConfig(u16 TIM1_OCFast);
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608 void TIM1_OC3FastConfig(u16 TIM1_OCFast);
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609 void TIM1_OC4FastConfig(u16 TIM1_OCFast);
\r
610 void TIM1_GenerateEvent(u16 TIM1_EventSource);
\r
611 void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);
\r
612 void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);
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613 void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);
\r
614 void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);
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615 void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);
\r
616 void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);
\r
617 void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);
\r
618 void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);
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619 void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);
\r
620 void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);
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621 void TIM1_SetAutoreload(u16 Autoreload);
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622 void TIM1_SetCompare1(u16 Compare1);
\r
623 void TIM1_SetCompare2(u16 Compare2);
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624 void TIM1_SetCompare3(u16 Compare3);
\r
625 void TIM1_SetCompare4(u16 Compare4);
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626 void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);
\r
627 void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);
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628 void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);
\r
629 void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);
\r
630 void TIM1_SetClockDivision(u16 TIM1_CKD);
\r
631 u16 TIM1_GetCapture1(void);
\r
632 u16 TIM1_GetCapture2(void);
\r
633 u16 TIM1_GetCapture3(void);
\r
634 u16 TIM1_GetCapture4(void);
\r
635 u16 TIM1_GetCounter(void);
\r
636 u16 TIM1_GetPrescaler(void);
\r
637 FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG);
\r
638 void TIM1_ClearFlag(u16 TIM1_Flag);
\r
639 ITStatus TIM1_GetITStatus(u16 TIM1_IT);
\r
640 void TIM1_ClearITPendingBit(u16 TIM1_IT);
\r
642 #endif /*__STM32F10x_TIM1_H */
\r
644 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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projects / freertos / blob