1 /** ###################################################################
\r
2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
\r
3 ** Filename : IO_Map.C
\r
4 ** Project : RTOSDemo
\r
5 ** Processor : MC9S12DP256BCPV
\r
7 ** Version : Driver 01.01
\r
8 ** Compiler : Metrowerks HC12 C Compiler
\r
9 ** Date/Time : 13/06/2005, 20:14
\r
11 ** This bean "IO_Map" implements an IO devices mapping.
\r
15 ** No public methods
\r
17 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
\r
18 ** UNIS, spol. s r.o.
\r
22 ** http : www.processorexpert.com
\r
23 ** mail : info@processorexpert.com
\r
24 ** ###################################################################*/
\r
25 /* Based on CPU DB MC9S12DP256_112, version 2.87.278 */
\r
26 #include "PE_types.h"
\r
29 volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */
\r
30 volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */
\r
31 volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */
\r
32 volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */
\r
33 volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */
\r
34 volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */
\r
35 volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */
\r
36 volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */
\r
37 volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */
\r
38 volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */
\r
39 volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */
\r
40 volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */
\r
41 volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */
\r
42 volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */
\r
43 volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */
\r
44 volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */
\r
45 volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */
\r
46 volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */
\r
47 volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */
\r
48 volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */
\r
49 volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */
\r
50 volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */
\r
51 volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */
\r
52 volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */
\r
53 volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */
\r
54 volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */
\r
55 volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */
\r
56 volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */
\r
57 volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */
\r
58 volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */
\r
59 volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */
\r
60 volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */
\r
61 volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */
\r
62 volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */
\r
63 volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */
\r
64 volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */
\r
65 volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */
\r
66 volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */
\r
67 volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */
\r
68 volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */
\r
69 volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */
\r
70 volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */
\r
71 volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */
\r
72 volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */
\r
73 volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */
\r
74 volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */
\r
75 volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */
\r
76 volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */
\r
77 volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */
\r
78 volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */
\r
79 volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */
\r
80 volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */
\r
81 volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */
\r
82 volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */
\r
83 volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */
\r
84 volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */
\r
85 volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */
\r
86 volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */
\r
87 volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */
\r
88 volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */
\r
89 volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */
\r
90 volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */
\r
91 volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */
\r
92 volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */
\r
93 volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */
\r
94 volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */
\r
95 volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */
\r
96 volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */
\r
97 volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */
\r
98 volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */
\r
99 volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */
\r
100 volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */
\r
101 volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */
\r
102 volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */
\r
103 volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */
\r
104 volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */
\r
105 volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */
\r
106 volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */
\r
107 volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */
\r
108 volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */
\r
109 volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */
\r
110 volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */
\r
111 volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */
\r
112 volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */
\r
113 volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */
\r
114 volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */
\r
115 volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */
\r
116 volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */
\r
117 volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */
\r
118 volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */
\r
119 volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */
\r
120 volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */
\r
121 volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */
\r
122 volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */
\r
123 volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */
\r
124 volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */
\r
125 volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */
\r
126 volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */
\r
127 volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */
\r
128 volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */
\r
129 volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */
\r
130 volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */
\r
131 volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */
\r
132 volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */
\r
133 volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */
\r
134 volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */
\r
135 volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */
\r
136 volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */
\r
137 volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */
\r
138 volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */
\r
139 volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */
\r
140 volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */
\r
141 volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */
\r
142 volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */
\r
143 volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */
\r
144 volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */
\r
145 volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */
\r
146 volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */
\r
147 volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */
\r
148 volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */
\r
149 volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */
\r
150 volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */
\r
151 volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */
\r
152 volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */
\r
153 volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */
\r
154 volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */
\r
155 volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */
\r
156 volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */
\r
157 volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */
\r
158 volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */
\r
159 volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */
\r
160 volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */
\r
161 volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */
\r
162 volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */
\r
163 volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */
\r
164 volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */
\r
165 volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */
\r
166 volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */
\r
167 volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */
\r
168 volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */
\r
169 volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */
\r
170 volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */
\r
171 volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */
\r
172 volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */
\r
173 volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */
\r
174 volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */
\r
175 volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */
\r
176 volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */
\r
177 volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */
\r
178 volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */
\r
179 volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */
\r
180 volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */
\r
181 volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */
\r
182 volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */
\r
183 volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */
\r
184 volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */
\r
185 volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */
\r
186 volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */
\r
187 volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */
\r
188 volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */
\r
189 volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */
\r
190 volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */
\r
191 volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */
\r
192 volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */
\r
193 volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */
\r
194 volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */
\r
195 volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */
\r
196 volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */
\r
197 volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */
\r
198 volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */
\r
199 volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */
\r
200 volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */
\r
201 volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */
\r
202 volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */
\r
203 volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */
\r
204 volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */
\r
205 volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */
\r
206 volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */
\r
207 volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */
\r
208 volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */
\r
209 volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */
\r
210 volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */
\r
211 volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */
\r
212 volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */
\r
213 volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */
\r
214 volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */
\r
215 volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */
\r
216 volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */
\r
217 volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */
\r
218 volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */
\r
219 volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */
\r
220 volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */
\r
221 volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */
\r
222 volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */
\r
223 volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */
\r
224 volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */
\r
225 volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */
\r
226 volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */
\r
227 volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */
\r
228 volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */
\r
229 volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */
\r
230 volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */
\r
231 volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */
\r
232 volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */
\r
233 volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */
\r
234 volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */
\r
235 volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */
\r
236 volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */
\r
237 volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */
\r
238 volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */
\r
239 volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */
\r
240 volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */
\r
241 volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */
\r
242 volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */
\r
243 volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */
\r
244 volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */
\r
245 volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */
\r
246 volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */
\r
247 volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */
\r
248 volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */
\r
249 volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */
\r
250 volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */
\r
251 volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */
\r
252 volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */
\r
253 volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */
\r
254 volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */
\r
255 volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */
\r
256 volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */
\r
257 volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */
\r
258 volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */
\r
259 volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */
\r
260 volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */
\r
261 volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */
\r
262 volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */
\r
263 volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */
\r
264 volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */
\r
265 volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */
\r
266 volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */
\r
267 volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */
\r
268 volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */
\r
269 volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */
\r
270 volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */
\r
271 volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */
\r
272 volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */
\r
273 volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */
\r
274 volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */
\r
275 volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */
\r
276 volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */
\r
277 volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */
\r
278 volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */
\r
279 volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */
\r
280 volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */
\r
281 volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */
\r
282 volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */
\r
283 volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */
\r
284 volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */
\r
285 volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */
\r
286 volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */
\r
287 volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */
\r
288 volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */
\r
289 volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */
\r
290 volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */
\r
291 volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */
\r
292 volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */
\r
293 volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */
\r
294 volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */
\r
295 volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */
\r
296 volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */
\r
297 volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */
\r
298 volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */
\r
299 volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */
\r
300 volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */
\r
301 volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */
\r
302 volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */
\r
303 volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */
\r
304 volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */
\r
305 volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */
\r
306 volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */
\r
307 volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */
\r
308 volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */
\r
309 volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */
\r
310 volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */
\r
311 volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */
\r
312 volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */
\r
313 volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */
\r
314 volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */
\r
315 volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */
\r
316 volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */
\r
317 volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */
\r
318 volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */
\r
319 volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */
\r
320 volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */
\r
321 volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */
\r
322 volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */
\r
323 volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */
\r
324 volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */
\r
325 volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */
\r
326 volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */
\r
327 volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */
\r
328 volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */
\r
329 volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */
\r
330 volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */
\r
331 volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */
\r
332 volatile CFORCSTR _CFORC; /* Timer Compare Force Register */
\r
333 volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */
\r
334 volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */
\r
335 volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */
\r
336 volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */
\r
337 volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */
\r
338 volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */
\r
339 volatile DDRESTR _DDRE; /* Port E Data Direction Register */
\r
340 volatile DDRHSTR _DDRH; /* Port H Data Direction Register */
\r
341 volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */
\r
342 volatile DDRKSTR _DDRK; /* Port K Data Direction Register */
\r
343 volatile DDRMSTR _DDRM; /* Port M Data Direction Register */
\r
344 volatile DDRPSTR _DDRP; /* Port P Data Direction Register */
\r
345 volatile DDRSSTR _DDRS; /* Port S Data Direction Register */
\r
346 volatile DDRTSTR _DDRT; /* Port T Data Direction Register */
\r
347 volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */
\r
348 volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */
\r
349 volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */
\r
350 volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */
\r
351 volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */
\r
352 volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */
\r
353 volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */
\r
354 volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */
\r
355 volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */
\r
356 volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */
\r
357 volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */
\r
358 volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */
\r
359 volatile EPROTSTR _EPROT; /* EEPROM Protection Register */
\r
360 volatile ESTATSTR _ESTAT; /* EEPROM Status Register */
\r
361 volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */
\r
362 volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */
\r
363 volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */
\r
364 volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */
\r
365 volatile FPROTSTR _FPROT; /* Flash Protection Register */
\r
366 volatile FSECSTR _FSEC; /* Flash Security Register */
\r
367 volatile FSTATSTR _FSTAT; /* Flash Status Register */
\r
368 volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */
\r
369 volatile IBADSTR _IBAD; /* IIC Address Register */
\r
370 volatile IBCRSTR _IBCR; /* IIC Control Register */
\r
371 volatile IBDRSTR _IBDR; /* IIC Data I/O Register */
\r
372 volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */
\r
373 volatile IBSRSTR _IBSR; /* IIC Status Register */
\r
374 volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */
\r
375 volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */
\r
376 volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */
\r
377 volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */
\r
378 volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */
\r
379 volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */
\r
380 volatile INTCRSTR _INTCR; /* Interrupt Control Register */
\r
381 volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */
\r
382 volatile ITESTSTR _ITEST; /* Interrupt Test Register */
\r
383 volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */
\r
384 volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */
\r
385 volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */
\r
386 volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */
\r
387 volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */
\r
388 volatile MODESTR _MODE; /* Mode Register */
\r
389 volatile MODRRSTR _MODRR; /* Module Routing Register */
\r
390 volatile MTST0STR _MTST0; /* MTST0 */
\r
391 volatile MTST1STR _MTST1; /* MTST1 */
\r
392 volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */
\r
393 volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */
\r
394 volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */
\r
395 volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */
\r
396 volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */
\r
397 volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */
\r
398 volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */
\r
399 volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */
\r
400 volatile PEARSTR _PEAR; /* Port E Assignment Register */
\r
401 volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */
\r
402 volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */
\r
403 volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */
\r
404 volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */
\r
405 volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */
\r
406 volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */
\r
407 volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */
\r
408 volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */
\r
409 volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */
\r
410 volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */
\r
411 volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */
\r
412 volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */
\r
413 volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */
\r
414 volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */
\r
415 volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */
\r
416 volatile PORTESTR _PORTE; /* Port E Register */
\r
417 volatile PORTKSTR _PORTK; /* Port K Data Register */
\r
418 volatile PPAGESTR _PPAGE; /* Page Index Register */
\r
419 volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */
\r
420 volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */
\r
421 volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */
\r
422 volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */
\r
423 volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */
\r
424 volatile PPSTSTR _PPST; /* Port T Polarity Select Register */
\r
425 volatile PTHSTR _PTH; /* Port H I/O Register */
\r
426 volatile PTIHSTR _PTIH; /* Port H Input Register */
\r
427 volatile PTIJSTR _PTIJ; /* Port J Input Register */
\r
428 volatile PTIMSTR _PTIM; /* Port M Input */
\r
429 volatile PTIPSTR _PTIP; /* Port P Input */
\r
430 volatile PTISSTR _PTIS; /* Port S Input */
\r
431 volatile PTITSTR _PTIT; /* Port T Input */
\r
432 volatile PTJSTR _PTJ; /* Port J I/O Register */
\r
433 volatile PTMSTR _PTM; /* Port M I/O Register */
\r
434 volatile PTPSTR _PTP; /* Port P I/O Register */
\r
435 volatile PTSSTR _PTS; /* Port S I/O Register */
\r
436 volatile PTTSTR _PTT; /* Port T I/O Register */
\r
437 volatile PUCRSTR _PUCR; /* Pull-Up Control Register */
\r
438 volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */
\r
439 volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */
\r
440 volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */
\r
441 volatile PWMESTR _PWME; /* PWM Enable Register */
\r
442 volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */
\r
443 volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */
\r
444 volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */
\r
445 volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */
\r
446 volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */
\r
447 volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */
\r
448 volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */
\r
449 volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */
\r
450 volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */
\r
451 volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */
\r
452 volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */
\r
453 volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */
\r
454 volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */
\r
455 volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */
\r
456 volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */
\r
457 volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */
\r
458 volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */
\r
459 volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */
\r
460 volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */
\r
461 volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */
\r
462 volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */
\r
463 volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */
\r
464 volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */
\r
465 volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */
\r
466 volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */
\r
467 volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */
\r
468 volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */
\r
469 volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */
\r
470 volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */
\r
471 volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */
\r
472 volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */
\r
473 volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */
\r
474 volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */
\r
475 volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */
\r
476 volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */
\r
477 volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */
\r
478 volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */
\r
479 volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */
\r
480 volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */
\r
481 volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */
\r
482 volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */
\r
483 volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */
\r
484 volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */
\r
485 volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */
\r
486 volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */
\r
487 volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */
\r
488 volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */
\r
489 volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */
\r
490 volatile TIESTR _TIE; /* Timer Interrupt Enable Register */
\r
491 volatile TIMTSTSTR _TIMTST; /* Timer Test Register */
\r
492 volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */
\r
493 volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */
\r
494 volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */
\r
495 volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */
\r
496 volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */
\r
497 volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */
\r
498 volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */
\r
499 volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */
\r
500 volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */
\r
501 volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */
\r
502 volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */
\r
503 volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */
\r
504 volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */
\r
505 volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */
\r
506 volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */
\r
507 volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */
\r
508 volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */
\r
509 volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */
\r
510 volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */
\r
511 volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */
\r
512 volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */
\r
513 volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */
\r
514 volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */
\r
515 volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */
\r
516 volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */
\r
517 volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */
\r
518 volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */
\r
519 volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */
\r
520 volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */
\r
521 volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */
\r
522 volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */
\r
523 volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */
\r
524 volatile PORTABSTR _PORTAB; /* Port AB Register */
\r
525 volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */
\r
526 volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */
\r
527 volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */
\r
528 volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */
\r
529 volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */
\r
530 volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */
\r
531 volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */
\r
532 volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */
\r
533 volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */
\r
534 volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */
\r
535 volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */
\r
536 volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */
\r
537 volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */
\r
538 volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */
\r
539 volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */
\r
540 volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */
\r
541 volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */
\r
542 volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */
\r
543 volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */
\r
544 volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */
\r
545 volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */
\r
546 volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */
\r
547 volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */
\r
548 volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */
\r
549 volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */
\r
550 volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */
\r
551 volatile TCNTSTR _TCNT; /* Timer Count Register */
\r
553 ** ###################################################################
\r
555 ** This file was created by UNIS Processor Expert 03.33 for
\r
556 ** the Motorola HCS12 series of microcontrollers.
\r
558 ** ###################################################################
\r
projects / freertos / blob