1 /*--------------------------------------------------------------------
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2 Copyright(c) 2015 Intel Corporation. All rights reserved.
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4 Redistribution and use in source and binary forms, with or without
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5 modification, are permitted provided that the following conditions
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8 * Redistributions of source code must retain the above copyright
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9 notice, this list of conditions and the following disclaimer.
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10 * Redistributions in binary form must reproduce the above copyright
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11 notice, this list of conditions and the following disclaimer in
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12 the documentation and/or other materials provided with the
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14 * Neither the name of Intel Corporation nor the names of its
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15 contributors may be used to endorse or promote products derived
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16 from this software without specific prior written permission.
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18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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24 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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28 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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29 --------------------------------------------------------------------*/
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31 #ifndef __GPIO_I2C_H__
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32 #define __GPIO_I2C_H__
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38 //---------------------------------------------------------------------
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39 // Any required includes
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40 //---------------------------------------------------------------------
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41 #include "galileo_gen_defs.h"
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43 //---------------------------------------------------------------------
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44 // PCI Configuration Map Register Offsets
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45 //---------------------------------------------------------------------
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46 #define PCI_REG_VID 0x00 // Vendor ID Register
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47 #define PCI_REG_DID 0x02 // Device ID Register
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48 #define PCI_REG_PCICMD 0x04 // PCI Command Register
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49 #define PCI_REG_PCISTS 0x06 // PCI Status Register
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50 #define PCI_REG_RID 0x08 // PCI Revision ID Register
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51 #define PCI_REG_PI 0x09 // Programming Interface
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52 #define PCI_REG_SCC 0x0a // Sub Class Code Register
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53 #define PCI_REG_BCC 0x0b // Base Class Code Register
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54 #define PCI_REG_PMLT 0x0d // Primary Master Latency Timer
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55 #define PCI_REG_HDR 0x0e // Header Type Register
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56 #define PCI_REG_PBUS 0x18 // Primary Bus Number Register
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57 #define PCI_REG_SBUS 0x19 // Secondary Bus Number Register
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58 #define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register
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59 #define PCI_REG_SMLT 0x1b // Secondary Master Latency Timer
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60 #define PCI_REG_IOBASE 0x1c // I/O base Register
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61 #define PCI_REG_IOLIMIT 0x1d // I/O Limit Register
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62 #define PCI_REG_SECSTATUS 0x1e // Secondary Status Register
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63 #define PCI_REG_MEMBASE 0x20 // Memory Base Register
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64 #define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register
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65 #define PCI_REG_PRE_MEMBASE 0x24 // Prefetchable memory Base register
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66 #define PCI_REG_PRE_MEMLIMIT 0x26 // Prefetchable memory Limit register
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67 #define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte
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68 #define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte
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69 #define PCI_REG_SID0 0x2e // Subsystem ID low byte
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70 #define PCI_REG_SID1 0x2f // Subsystem ID high byte
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71 #define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register
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72 #define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register
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73 #define PCI_REG_INTLINE 0x3c // Interrupt Line Register
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74 #define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register
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76 #define IO_PCI_ADDRESS(bus, dev, fn, reg) \
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77 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
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79 //---------------------------------------------------------------------
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80 // PCI Read/Write IO Data
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81 //---------------------------------------------------------------------
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82 #define IO_PCI_ADDRESS_PORT 0xcf8
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83 #define IO_PCI_DATA_PORT 0xcfc
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85 //---------------------------------------------------------------------
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87 //---------------------------------------------------------------------
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89 struct __attribute__ ((__packed__)) BOARD_GPIO_CONTROLLER_CONFIG
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91 uint32_t PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.
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92 uint32_t PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.
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93 uint32_t IntEn; ///< Value for IOH REG GPIO_INTEN.
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94 uint32_t IntMask; ///< Value for IOH REG GPIO_INTMASK.
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95 uint32_t IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.
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96 uint32_t IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.
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97 uint32_t Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.
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98 uint32_t LsSync; ///< Value for IOH REG GPIO_LS_SYNC.
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101 struct __attribute__ ((__packed__)) BOARD_LEGACY_GPIO_CONFIG
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103 uint32_t CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.
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104 uint32_t CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.
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105 uint32_t CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.
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106 uint32_t CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.
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107 uint32_t CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.
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108 uint32_t CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.
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109 uint32_t CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.
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110 uint32_t CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.
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111 uint32_t CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.
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112 uint32_t ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.
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113 uint32_t ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.
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114 uint32_t ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.
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115 uint32_t ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.
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116 uint32_t ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.
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117 uint32_t ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.
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118 uint32_t ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.
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119 uint32_t ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.
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120 uint32_t ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.
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123 //---------------------------------------------------------------------
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124 // GPIO definitions
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125 //---------------------------------------------------------------------
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126 #define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05, 0x05, 0, 0, 0, 0, 0, 0}
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127 #define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, \
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128 0x03, 0x00, 0x3f, 0x1c, 0x02, 0x00, 0x00, \
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129 0x00, 0x00, 0x3f, 0x00}
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131 #define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \
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132 /* EFI_PLATFORM_TYPE - Galileo Gen 2 */ \
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133 GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER ,\
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135 #define PLATFORM_LEGACY_GPIO_CONFIG_DEFINITION \
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136 /* EFI_PLATFORM_TYPE - Galileo Gen 2 */ \
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137 GALILEO_GEN2_LEGACY_GPIO_INITIALIZER , \
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139 #define IOH_I2C_GPIO_BUS_NUMBER 0x00
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140 #define IOH_I2C_GPIO_DEVICE_NUMBER 0x15
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141 #define IOH_I2C_GPIO_FUNCTION_NUMBER 0x02
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143 #define INTEL_VENDOR_ID 0x8086
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144 #define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
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145 #define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
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147 #define R_IOH_I2C_MEMBAR 0x10
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148 #define R_IOH_GPIO_MEMBAR 0x14
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150 #define GPIO_SWPORTA_DR 0x00
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151 #define GPIO_SWPORTA_DDR 0x04
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152 #define GPIO_SWPORTB_DR 0x0C
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153 #define GPIO_SWPORTB_DDR 0x10
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154 #define GPIO_SWPORTC_DR 0x18
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155 #define GPIO_SWPORTC_DDR 0x1C
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156 #define GPIO_SWPORTD_DR 0x24
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157 #define GPIO_SWPORTD_DDR 0x28
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158 #define GPIO_INTEN 0x30
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159 #define GPIO_INTMASK 0x34
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160 #define GPIO_INTTYPE_LEVEL 0x38
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161 #define GPIO_INT_POLARITY 0x3C
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162 #define GPIO_INTSTATUS 0x40
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163 #define GPIO_RAW_INTSTATUS 0x44
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164 #define GPIO_DEBOUNCE 0x48
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165 #define GPIO_PORTA_EOI 0x4C
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166 #define GPIO_EXT_PORTA 0x50
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167 #define GPIO_EXT_PORTB 0x54
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168 #define GPIO_EXT_PORTC 0x58
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169 #define GPIO_EXT_PORTD 0x5C
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170 #define GPIO_LS_SYNC 0x60
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171 #define GPIO_CONFIG_REG2 0x70
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172 #define GPIO_CONFIG_REG1 0x74
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174 //---------------------------------------------------------------------
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175 // GPIO defines for cypress chip
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176 //---------------------------------------------------------------------
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177 #define PCAL9555_REG_OUT_PORT0 0x02
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178 #define PCAL9555_REG_OUT_PORT1 0x03
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179 #define PCAL9555_REG_CFG_PORT0 0x06
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180 #define PCAL9555_REG_CFG_PORT1 0x07
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181 #define PCAL9555_REG_PULL_EN_PORT0 0x46
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182 #define PCAL9555_REG_PULL_EN_PORT1 0x47
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184 //---------------------------------------------------------------------
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185 // Three IO Expanders at fixed addresses on Galileo Gen2.
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186 //---------------------------------------------------------------------
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187 #define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25
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188 #define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26
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189 #define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27
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191 //---------------------------------------------------------------------
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192 // Legacy GPIO defines
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193 //---------------------------------------------------------------------
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194 #define LEGACY_GPIO_BUS_NUMBER 0
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195 #define LEGACY_GPIO_DEVICE_NUMBER 31
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196 #define LEGACY_GPIO_FUNCTION_NUMBER 0
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198 #define R_QNC_LPC_GBA_BASE 0x44
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199 #define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0
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201 //---------------------------------------------------------------------
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202 // I2C structures and enums
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203 //---------------------------------------------------------------------
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206 /// The I2C hardware address to which the I2C device is preassigned or allocated.
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207 uintn_t I2CDeviceAddress : 10;
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208 } I2C_DEVICE_ADDRESS;
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210 typedef enum _I2C_ADDR_MODE
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212 EfiI2CSevenBitAddrMode,
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213 EfiI2CTenBitAddrMode,
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216 //---------------------------------------------------------------------
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218 //---------------------------------------------------------------------
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219 #define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5
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220 #define R_QNC_GPIO_CGEN_CORE_WELL 0x00
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221 #define R_QNC_GPIO_CGIO_CORE_WELL 0x04
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222 #define R_QNC_GPIO_CGLVL_CORE_WELL 0x08
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223 #define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable
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224 #define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable
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225 #define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable
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226 #define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable
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227 #define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status
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228 #define R_QNC_GPIO_RGEN_RESUME_WELL 0x20
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229 #define R_QNC_GPIO_RGIO_RESUME_WELL 0x24
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230 #define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28
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231 #define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable
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232 #define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable
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233 #define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable
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234 #define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable
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235 #define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status
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236 #define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable
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237 #define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable
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239 #define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
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240 #define I2C_REG_CLR_START_DET 0x64 // Clear START DET Interrupt Register
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241 #define I2C_REG_CLR_STOP_DET 0x60 // Clear STOP DET Interrupt Register
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242 #define B_I2C_REG_CLR_START_DET (BIT0) // Clear START DET Interrupt Register
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243 #define B_I2C_REG_CLR_STOP_DET (BIT0) // Clear STOP DET Interrupt Register
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244 #define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addressing (1)
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245 #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)
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246 #define I2C_REG_CON 0x00 // Control Register
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247 #define I2C_REG_ENABLE 0x6C // Enable Register
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248 #define B_I2C_REG_ENABLE (BIT0) // Enable (1) or disable (0) I2C Controller
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249 #define I2C_REG_ENABLE_STATUS 0x9C // Enable Status Register
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250 #define I2C_REG_CLR_INT 0x40 // Clear Combined and Individual Interrupt Register
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251 #define MAX_T_POLL_COUNT 100
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252 #define TI2C_POLL 25 // microseconds
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253 #define I2C_REG_CLR_RX_OVER 0x48 // Clear RX Over Interrupt Register
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254 #define I2C_REG_CLR_TX_OVER 0x4C // Clear TX Over Interrupt Register
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255 #define I2C_REG_CLR_TX_ABRT 0x54 // Clear TX ABRT Interrupt Register
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256 #define I2C_FIFO_SIZE 16
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257 #define I2C_REG_TAR 0x04 // Master Target Address Register
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258 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
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259 #define I2C_REG_DATA_CMD 0x10 // Data Buffer and Command Register
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260 #define B_I2C_REG_DATA_CMD_RW (BIT8) // Data Buffer and Command Register Read/Write bit
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261 #define I2C_REG_RXFLR 0x78 // Receive FIFO Level Register
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262 #define B_I2C_REG_DATA_CMD_STOP (BIT9) // Data Buffer and Command Register STOP bit
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263 #define I2C_REG_RAW_INTR_STAT 0x34 // Raw Interrupt Status Register
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264 #define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.
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265 #define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Underflow signal status.
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266 #define I2C_REG_CLR_RX_UNDER 0x44 // Clear RX Under Interrupt Register
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267 #define MAX_STOP_DET_POLL_COUNT ((1000 * 1000) / TI2C_POLL) // Extreme for expected Stop detect.
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268 #define I2C_REG_RAW_INTR_STAT_TX_ABRT (BIT6) // Raw Interrupt Status Register TX Abort status.
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269 #define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Overflow signal status.
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270 #define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status.
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272 //---------------------------------------------------------------------
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274 //---------------------------------------------------------------------
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275 #define GPIO_OUTPUT (0)
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276 #define GPIO_INPUT (1)
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279 #define GPIO_NUMBER (7UL)
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281 void vMicroSecondDelay(uint32_t DelayTime);
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282 void vMilliSecondDelay(uint32_t DelayTime);
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283 void vGalileoInitializeLegacyGPIO(void);
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284 void vGalileoInitializeGpioController(void);
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285 void vGalileoLegacyGPIOInitializationForLED(void);
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286 void vGalileoSetGPIOBitDirection(uint32_t GPIONumber, uint32_t Direction);
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287 void vGalileoSetGPIOBitLevel(uint32_t GPIONumber, uint32_t Level);
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288 void vGalileoBlinkLEDUsingLegacyGPIO(uint32_t Level);
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294 #endif /* __GPIO_I2C_H__ */
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