1 /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
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2 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
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3 /* ELIGIBILITY FOR ANY PURPOSES. */
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4 /* (C) Fujitsu Microelectronics Europe GmbH */
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5 /*------------------------------------------------------------------------
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7 - Interrupt level (priority) setting
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8 - Interrupt vector definition
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10 31.04.05 1.00 UMa Initial Version
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11 08.11.05 1.01 MSt SWB Mondeb switch for ICR00 Register added
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12 27.02.06 1.02 UMa added comment in DefaultIRQHandler
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13 17.03.06 1.03 UMa comment out ICR01
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14 28.07.06 1.04 UMa changed comment
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15 06.10.06 1.05 UMa changed DefaultIRQHandler
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16 -------------------------------------------------------------------------*/
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18 #include "mb91467d.h"
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19 #include "watchdog.h"
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20 #include "FreeRTOSConfig.h"
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22 /*------------------------------------------------------------------------
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25 This function pre-sets all interrupt control registers. It can be used
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26 to set all interrupt priorities in static applications. If this file
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27 contains assignments to dedicated resources, verify that the
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28 appropriate controller is used. Not all devices of the MB91460 Series
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29 offer all recources.
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31 NOTE: value 31 disables the interrupt and value 16 sets highest priority.
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32 -------------------------------------------------------------------------*/
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33 void InitIrqLevels(void)
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36 /* Softune Workbench Monitor Debugger is using ext int0 for abort function */
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37 /* ICR00 = 31; *//* External Interrupt 0 */
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38 /* External Interrupt 1 */
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39 ICR01 = 31; /* External Interrupt 2 */
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40 /* External Interrupt 3 */
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41 ICR02 = 31; /* External Interrupt 4 */
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42 /* External Interrupt 5 */
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43 ICR03 = 31; /* External Interrupt 6 */
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44 /* External Interrupt 7 */
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45 ICR04 = 31; /* External Interrupt 8 */
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46 /* External Interrupt 9 */
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47 ICR05 = 31; /* External Interrupt 10 */
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48 /* External Interrupt 11 */
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49 ICR06 = 31; /* External Interrupt 12 */
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50 /* External Interrupt 13 */
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51 ICR07 = 31; /* External Interrupt 14 */
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52 /* External Interrupt 15 */
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53 ICR08 = configKERNEL_INTERRUPT_PRIORITY; /* Reload Timer 0 */
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54 /* Reload Timer 1 */
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55 ICR09 = 31; /* Reload Timer 2 */
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56 /* Reload Timer 3 */
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57 ICR10 = 31; /* Reload Timer 4 */
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58 /* Reload Timer 5 */
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59 ICR11 = 31; /* Reload Timer 6 */
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60 /* Reload Timer 7 */
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61 ICR12 = 31; /* Free Run Timer 0 */
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62 /* Free Run Timer 1 */
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63 ICR13 = 31; /* Free Run Timer 2 */
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64 /* Free Run Timer 3 */
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65 ICR14 = 31; /* Free Run Timer 4 */
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66 /* Free Run Timer 5 */
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67 ICR15 = 31; /* Free Run Timer 6 */
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68 /* Free Run Timer 7 */
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69 ICR16 = 31; /* CAN 0 */
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71 ICR17 = 31; /* CAN 2 */
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73 ICR18 = 31; /* CAN 4 */
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75 ICR19 = 31; /* USART (LIN) 0 RX */
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76 /* USART (LIN) 0 TX */
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77 ICR20 = 31; /* USART (LIN) 1 RX */
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78 /* USART (LIN) 1 TX */
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79 ICR21 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN) 2 RX */
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80 /* USART (LIN) 2 TX */
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81 ICR22 = 31; /* USART (LIN) 3 RX */
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82 /* USART (LIN) 3 TX */
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83 ICR23 = configKERNEL_INTERRUPT_PRIORITY; /* System Reserved */
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84 /* Delayed Interrupt */
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85 ICR24 = 31; /* System Reserved */
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86 /* System Reserved */
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87 ICR25 = 31; /* USART (LIN, FIFO) 4 RX */
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88 /* USART (LIN, FIFO) 4 TX */
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89 ICR26 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN, FIFO) 5 RX */
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90 /* USART (LIN, FIFO) 5 TX */
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91 ICR27 = 31; /* USART (LIN, FIFO) 6 RX */
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92 /* USART (LIN, FIFO) 6 TX */
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93 ICR28 = 31; /* USART (LIN, FIFO) 7 RX */
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94 /* USART (LIN, FIFO) 7 TX */
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95 ICR29 = 31; /* I2C 0 / I2C 2 */
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97 ICR30 = 31; /* USART (LIN, FIFO) 8 RX */
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98 /* USART (LIN, FIFO) 8 TX */
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99 ICR31 = 31; /* USART (LIN, FIFO) 9 RX */
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100 /* USART (LIN, FIFO) 9 TX */
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101 ICR32 = 31; /* USART (LIN, FIFO) 10 RX */
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102 /* USART (LIN, FIFO) 10 TX */
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103 ICR33 = 31; /* USART (LIN, FIFO) 11 RX */
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104 /* USART (LIN, FIFO) 11 TX */
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105 ICR34 = 31; /* USART (LIN, FIFO) 12 RX */
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106 /* USART (LIN, FIFO) 12 TX */
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107 ICR35 = 31; /* USART (LIN, FIFO) 13 RX */
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108 /* USART (LIN, FIFO) 13 TX */
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109 ICR36 = 31; /* USART (LIN, FIFO) 14 RX */
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110 /* USART (LIN, FIFO) 14 TX */
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111 ICR37 = 31; /* USART (LIN, FIFO) 15 RX */
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112 /* USART (LIN, FIFO) 15 TX */
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113 ICR38 = 31; /* Input Capture 0 */
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114 /* Input Capture 1 */
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115 ICR39 = 31; /* Input Capture 2 */
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116 /* Input Capture 3 */
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117 ICR40 = 31; /* Input Capture 4 */
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118 /* Input Capture 5 */
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119 ICR41 = 31; /* Input Capture 6 */
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120 /* Input Capture 7 */
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121 ICR42 = 31; /* Output Compare 0 */
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122 /* Output Compare 1 */
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123 ICR43 = 31; /* Output Compare 2 */
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124 /* Output Compare 3 */
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125 ICR44 = 31; /* Output Compare 4 */
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126 /* Output Compare 5 */
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127 ICR45 = 31; /* Output Compare 6 */
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128 /* Output Compare 7 */
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129 ICR46 = 31; /* Sound Generator */
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130 /* Phase Frequ. Modulator */
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131 ICR47 = 31; /* System Reserved */
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132 /* System Reserved */
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133 ICR48 = 31; /* Prog. Pulse Gen. 0 */
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134 /* Prog. Pulse Gen. 1 */
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135 ICR49 = 31; /* Prog. Pulse Gen. 2 */
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136 /* Prog. Pulse Gen. 3 */
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137 ICR50 = 31; /* Prog. Pulse Gen. 4 */
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138 /* Prog. Pulse Gen. 5 */
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139 ICR51 = 31; /* Prog. Pulse Gen. 6 */
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140 /* Prog. Pulse Gen. 7 */
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141 ICR52 = 31; /* Prog. Pulse Gen. 8 */
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142 /* Prog. Pulse Gen. 9 */
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143 ICR53 = 31; /* Prog. Pulse Gen. 10 */
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144 /* Prog. Pulse Gen. 11 */
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145 ICR54 = 31; /* Prog. Pulse Gen. 12 */
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146 /* Prog. Pulse Gen. 13 */
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147 ICR55 = 31; /* Prog. Pulse Gen. 14 */
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148 /* Prog. Pulse Gen. 15 */
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149 ICR56 = 31; /* Up/Down Counter 0 */
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150 /* Up/Down Counter 1 */
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151 ICR57 = 31; /* Up/Down Counter 2 */
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152 /* Up/Down Counter 3 */
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153 ICR58 = 31; /* Real Time Clock */
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154 /* Calibration Unit */
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155 ICR59 = 31; /* A/D Converter 0 */
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157 ICR60 = 31; /* Alarm Comperator 0 */
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158 /* Alarm Comperator 1 */
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159 ICR61 = 31; /* Low Volage Detector */
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160 /* SMC Zero Point 0-5 */
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161 ICR62 = 31; /* Timebase Overflow */
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162 /* PLL Clock Gear */
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163 ICR63 = 31; /* DMA Controller */
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164 /* Main/Sub OSC stability wait */
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168 /*------------------------------------------------------------------------
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171 Add your own prototypes here. Each vector definition needs is proto-
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172 type. Either do it here or include a header file containing them.
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173 -------------------------------------------------------------------------*/
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174 __interrupt void DefaultIRQHandler (void);
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175 extern __interrupt void ReloadTimer0_IRQHandler ( void );
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176 extern __interrupt void vPortYield ( void );
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177 extern __interrupt void vPortYieldDelayed (void);
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179 extern __interrupt void UART2_RxISR(void);
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180 extern __interrupt void UART2_TxISR(void);
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181 extern __interrupt void UART5_RxISR(void);
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183 /*------------------------------------------------------------------------
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186 Use following statements to define vectors. All resource related
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187 vectors are predefined. Remaining software interrupts can be added here
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189 ------------------------------------------------------------------------*/
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190 #pragma intvect 0xBFF8 0 /* (fixed) reset vector */
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191 #pragma intvect 0x06000000 1 /* (fixed) Mode Byte */
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193 #pragma intvect DefaultIRQHandler 15 /* Non Maskable Interrupt */
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194 #pragma intvect DefaultIRQHandler 16 /* External Interrupt 0 */
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195 #pragma intvect DefaultIRQHandler 17 /* External Interrupt 1 */
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197 #pragma intvect DefaultIRQHandler 18 /* External Interrupt 2 */
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199 #pragma intvect DefaultIRQHandler 19 /* External Interrupt 3 */
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200 #pragma intvect DefaultIRQHandler 20 /* External Interrupt 4 */
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201 #pragma intvect DefaultIRQHandler 21 /* External Interrupt 5 */
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202 #pragma intvect DefaultIRQHandler 22 /* External Interrupt 6 */
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203 #pragma intvect DefaultIRQHandler 23 /* External Interrupt 7 */
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204 #pragma intvect DefaultIRQHandler 24 /* External Interrupt 8 */
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205 #pragma intvect DefaultIRQHandler 25 /* External Interrupt 9 */
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206 #pragma intvect DefaultIRQHandler 26 /* External Interrupt 10 */
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207 #pragma intvect DefaultIRQHandler 27 /* External Interrupt 11 */
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208 #pragma intvect DefaultIRQHandler 28 /* External Interrupt 12 */
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209 #pragma intvect DefaultIRQHandler 29 /* External Interrupt 13 */
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210 #pragma intvect DefaultIRQHandler 30 /* External Interrupt 14 */
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211 #pragma intvect DefaultIRQHandler 31 /* External Interrupt 15 */
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213 #pragma intvect ReloadTimer0_IRQHandler 32 /* Reload Timer 0 */
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215 #pragma intvect DefaultIRQHandler 33 /* Reload Timer 1 */
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216 #pragma intvect DefaultIRQHandler 34 /* Reload Timer 2 */
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217 #pragma intvect DefaultIRQHandler 35 /* Reload Timer 3 */
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218 #pragma intvect DefaultIRQHandler 36 /* Reload Timer 4 */
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219 #pragma intvect DefaultIRQHandler 37 /* Reload Timer 5 */
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220 #pragma intvect DefaultIRQHandler 38 /* Reload Timer 6 */
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221 #pragma intvect DefaultIRQHandler 39 /* Reload Timer 7 */
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222 #pragma intvect DefaultIRQHandler 40 /* Free Run Timer 0 */
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223 #pragma intvect DefaultIRQHandler 41 /* Free Run Timer 1 */
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224 #pragma intvect DefaultIRQHandler 42 /* Free Run Timer 2 */
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225 #pragma intvect DefaultIRQHandler 43 /* Free Run Timer 3 */
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226 #pragma intvect DefaultIRQHandler 44 /* Free Run Timer 4 */
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227 #pragma intvect DefaultIRQHandler 45 /* Free Run Timer 5 */
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228 #pragma intvect DefaultIRQHandler 46 /* Free Run Timer 6 */
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229 #pragma intvect DefaultIRQHandler 47 /* Free Run Timer 7 */
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230 #pragma intvect DefaultIRQHandler 48 /* CAN 0 */
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231 #pragma intvect DefaultIRQHandler 49 /* CAN 1 */
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232 #pragma intvect DefaultIRQHandler 50 /* CAN 2 */
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233 #pragma intvect DefaultIRQHandler 51 /* CAN 3 */
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234 #pragma intvect DefaultIRQHandler 52 /* CAN 4 */
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235 #pragma intvect DefaultIRQHandler 53 /* CAN 5 */
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236 #pragma intvect DefaultIRQHandler 54 /* USART (LIN) 0 RX */
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237 #pragma intvect DefaultIRQHandler 55 /* USART (LIN) 0 TX */
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238 #pragma intvect DefaultIRQHandler 56 /* USART (LIN) 1 RX */
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239 #pragma intvect DefaultIRQHandler 57 /* USART (LIN) 1 TX */
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241 #pragma intvect UART2_RxISR 58 /* USART (LIN) 2 RX */
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242 #pragma intvect UART2_TxISR 59 /* USART (LIN) 2 TX */
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244 #pragma intvect DefaultIRQHandler 60 /* USART (LIN) 3 RX */
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245 #pragma intvect DefaultIRQHandler 61 /* USART (LIN) 3 TX */
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246 #pragma intvect DefaultIRQHandler 62 /* System Reserved */
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248 #pragma intvect vPortYieldDelayed 63 /* Delayed Interrupt */
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250 #pragma intvect vPortYield 64 /* INT 64 */
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252 #pragma intvect DefaultIRQHandler 65 /* System Reserved */
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253 #pragma intvect DefaultIRQHandler 66 /* USART (LIN, FIFO) 4 RX */
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254 #pragma intvect DefaultIRQHandler 67 /* USART (LIN, FIFO) 4 TX */
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256 #pragma intvect UART5_RxISR 68 /* USART (LIN, FIFO) 5 RX */
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258 #pragma intvect DefaultIRQHandler 69 /* USART (LIN, FIFO) 5 TX */
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259 #pragma intvect DefaultIRQHandler 70 /* USART (LIN, FIFO) 6 RX */
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260 #pragma intvect DefaultIRQHandler 71 /* USART (LIN, FIFO) 6 TX */
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261 #pragma intvect DefaultIRQHandler 72 /* USART (LIN, FIFO) 7 RX */
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262 #pragma intvect DefaultIRQHandler 73 /* USART (LIN, FIFO) 7 TX */
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263 #pragma intvect DefaultIRQHandler 74 /* I2C 0 / I2C 2 */
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264 #pragma intvect DefaultIRQHandler 75 /* I2C 1 / I2C 3 */
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265 #pragma intvect DefaultIRQHandler 76 /* USART (LIN, FIFO) 8 RX */
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266 #pragma intvect DefaultIRQHandler 77 /* USART (LIN, FIFO) 8 TX */
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267 #pragma intvect DefaultIRQHandler 78 /* USART (LIN, FIFO) 9 RX */
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268 #pragma intvect DefaultIRQHandler 79 /* USART (LIN, FIFO) 9 TX */
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269 #pragma intvect DefaultIRQHandler 80 /* USART (LIN, FIFO) 10 RX */
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270 #pragma intvect DefaultIRQHandler 81 /* USART (LIN, FIFO) 10 TX */
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271 #pragma intvect DefaultIRQHandler 82 /* USART (LIN, FIFO) 11 RX */
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272 #pragma intvect DefaultIRQHandler 83 /* USART (LIN, FIFO) 11 TX */
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273 #pragma intvect DefaultIRQHandler 84 /* USART (LIN, FIFO) 12 RX */
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274 #pragma intvect DefaultIRQHandler 85 /* USART (LIN, FIFO) 12 TX */
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275 #pragma intvect DefaultIRQHandler 86 /* USART (LIN, FIFO) 13 RX */
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276 #pragma intvect DefaultIRQHandler 87 /* USART (LIN, FIFO) 13 TX */
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277 #pragma intvect DefaultIRQHandler 88 /* USART (LIN, FIFO) 14 RX */
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278 #pragma intvect DefaultIRQHandler 89 /* USART (LIN, FIFO) 14 TX */
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279 #pragma intvect DefaultIRQHandler 90 /* USART (LIN, FIFO) 15 RX */
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280 #pragma intvect DefaultIRQHandler 91 /* USART (LIN, FIFO) 15 TX */
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281 #pragma intvect DefaultIRQHandler 92 /* Input Capture 0 */
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282 #pragma intvect DefaultIRQHandler 93 /* Input Capture 1 */
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283 #pragma intvect DefaultIRQHandler 94 /* Input Capture 2 */
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284 #pragma intvect DefaultIRQHandler 95 /* Input Capture 3 */
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285 #pragma intvect DefaultIRQHandler 96 /* Input Capture 4 */
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286 #pragma intvect DefaultIRQHandler 97 /* Input Capture 5 */
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287 #pragma intvect DefaultIRQHandler 98 /* Input Capture 6 */
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288 #pragma intvect DefaultIRQHandler 99 /* Input Capture 7 */
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289 #pragma intvect DefaultIRQHandler 100 /* Output Compare 0 */
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290 #pragma intvect DefaultIRQHandler 101 /* Output Compare 1 */
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291 #pragma intvect DefaultIRQHandler 102 /* Output Compare 2 */
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292 #pragma intvect DefaultIRQHandler 103 /* Output Compare 3 */
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293 #pragma intvect DefaultIRQHandler 104 /* Output Compare 4 */
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294 #pragma intvect DefaultIRQHandler 105 /* Output Compare 5 */
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295 #pragma intvect DefaultIRQHandler 106 /* Output Compare 6 */
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296 #pragma intvect DefaultIRQHandler 107 /* Output Compare 7 */
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297 #pragma intvect DefaultIRQHandler 108 /* Sound Generator */
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298 #pragma intvect DefaultIRQHandler 109 /* Phase Frequ. Modulator */
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299 #pragma intvect DefaultIRQHandler 110 /* System Reserved */
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300 #pragma intvect DefaultIRQHandler 111 /* System Reserved */
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301 #pragma intvect DefaultIRQHandler 112 /* Prog. Pulse Gen. 0 */
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302 #pragma intvect DefaultIRQHandler 113 /* Prog. Pulse Gen. 1 */
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303 #pragma intvect DefaultIRQHandler 114 /* Prog. Pulse Gen. 2 */
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304 #pragma intvect DefaultIRQHandler 115 /* Prog. Pulse Gen. 3 */
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305 #pragma intvect DefaultIRQHandler 116 /* Prog. Pulse Gen. 4 */
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306 #pragma intvect DefaultIRQHandler 117 /* Prog. Pulse Gen. 5 */
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307 #pragma intvect DefaultIRQHandler 118 /* Prog. Pulse Gen. 6 */
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308 #pragma intvect DefaultIRQHandler 119 /* Prog. Pulse Gen. 7 */
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309 #pragma intvect DefaultIRQHandler 120 /* Prog. Pulse Gen. 8 */
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310 #pragma intvect DefaultIRQHandler 121 /* Prog. Pulse Gen. 9 */
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311 #pragma intvect DefaultIRQHandler 122 /* Prog. Pulse Gen. 10 */
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312 #pragma intvect DefaultIRQHandler 123 /* Prog. Pulse Gen. 11 */
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313 #pragma intvect DefaultIRQHandler 124 /* Prog. Pulse Gen. 12 */
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314 #pragma intvect DefaultIRQHandler 125 /* Prog. Pulse Gen. 13 */
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315 #pragma intvect DefaultIRQHandler 126 /* Prog. Pulse Gen. 14 */
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316 #pragma intvect DefaultIRQHandler 127 /* Prog. Pulse Gen. 15 */
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317 #pragma intvect DefaultIRQHandler 128 /* Up/Down Counter 0 */
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318 #pragma intvect DefaultIRQHandler 129 /* Up/Down Counter 1 */
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319 #pragma intvect DefaultIRQHandler 130 /* Up/Down Counter 2 */
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320 #pragma intvect DefaultIRQHandler 131 /* Up/Down Counter 3 */
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321 #pragma intvect DefaultIRQHandler 132 /* Real Time Clock */
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322 #pragma intvect DefaultIRQHandler 133 /* Calibration Unit */
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323 #pragma intvect DefaultIRQHandler 134 /* A/D Converter 0 */
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324 #pragma intvect DefaultIRQHandler 135 /* - */
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325 #pragma intvect DefaultIRQHandler 136 /* Alarm Comperator 0 */
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326 #pragma intvect DefaultIRQHandler 137 /* Alarm Comperator 1 */
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327 #pragma intvect DefaultIRQHandler 138 /* Low Volage Detector */
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328 #pragma intvect DefaultIRQHandler 139 /* SMC Zero Point 0-5 */
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329 #pragma intvect DefaultIRQHandler 140 /* Timebase Overflow */
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330 #pragma intvect DefaultIRQHandler 141 /* PLL Clock Gear */
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331 #pragma intvect DefaultIRQHandler 142 /* DMA Controller */
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332 #pragma intvect DefaultIRQHandler 143 /* Main/Sub OSC stability wait */
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333 #pragma intvect 0xFFFFFFFF 144 /* Boot Sec. Vector (MB91V460A) */
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335 /*------------------------------------------------------------------------
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336 DefaultIRQHandler()
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338 This function is a placeholder for all vector definitions. Either use
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339 your own placeholder or add necessary code here.
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340 -------------------------------------------------------------------------*/
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342 void DefaultIRQHandler (void)
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344 /* RB_SYNC; */ /* Synchronisation with R-Bus */
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345 /* May be required, if there is */
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346 /* no R-Bus access after the */
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347 /* reset of the interrupt flag */
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349 __DI(); /* disable interrupts */
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352 Kick_Watchdog(); /* feed hardware watchdog */
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projects / freertos / blob