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  31  * --/COPYRIGHT--*/\r
  32 //*****************************************************************************\r
  33 //\r
  34 // eusci_b_spi.c - Driver for the eusci_b_spi Module.\r
  35 //\r
  36 //*****************************************************************************\r
  37 \r
  38 //*****************************************************************************\r
  39 //\r
  40 //! \addtogroup eusci_b_spi_api eusci_b_spi\r
  41 //! @{\r
  42 //\r
  43 //*****************************************************************************\r
  44 \r
  45 #include "inc/hw_regaccess.h"\r
  46 #include "inc/hw_memmap.h"\r
  47 \r
  48 #ifdef __MSP430_HAS_EUSCI_Bx__\r
  49 #include "eusci_b_spi.h"\r
  50 \r
  51 #include <assert.h>\r
  52 \r
  53 void EUSCI_B_SPI_initMaster(uint16_t baseAddress,\r
  54                             EUSCI_B_SPI_initMasterParam *param)\r
  55 {\r
  56     //Disable the USCI Module\r
  57     HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
  58 \r
  59     //Reset OFS_UCBxCTLW0 values\r
  60     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +\r
  61                                               UCMST + UCMODE_3 + UCSYNC);\r
  62 \r
  63     //Reset OFS_UCBxCTLW0 values\r
  64     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3);\r
  65 \r
  66     //Select Clock\r
  67     HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource;\r
  68 \r
  69     HWREG16(baseAddress + OFS_UCBxBRW) =\r
  70         (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
  71 \r
  72     /*\r
  73      * Configure as SPI master mode.\r
  74      * Clock phase select, polarity, msb\r
  75      * UCMST = Master mode\r
  76      * UCSYNC = Synchronous mode\r
  77      * UCMODE_0 = 3-pin SPI\r
  78      */\r
  79     HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
  80         param->msbFirst +\r
  81         param->clockPhase +\r
  82         param->clockPolarity +\r
  83         UCMST +\r
  84         UCSYNC +\r
  85         param->spiMode\r
  86         );\r
  87 }\r
  88 \r
  89 void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,\r
  90                                          uint8_t select4PinFunctionality)\r
  91 {\r
  92     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM;\r
  93     HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality;\r
  94 }\r
  95 \r
  96 void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,\r
  97                                    EUSCI_B_SPI_changeMasterClockParam *param)\r
  98 {\r
  99     //Disable the USCI Module\r
 100     HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
 101 \r
 102     HWREG16(baseAddress + OFS_UCBxBRW) =\r
 103         (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
 104 \r
 105     //Reset the UCSWRST bit to enable the USCI Module\r
 106     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
 107 }\r
 108 \r
 109 void EUSCI_B_SPI_initSlave(uint16_t baseAddress,\r
 110                            EUSCI_B_SPI_initSlaveParam *param)\r
 111 {\r
 112     //Disable USCI Module\r
 113     HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
 114 \r
 115     //Reset OFS_UCBxCTLW0 register\r
 116     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB +\r
 117                                               UC7BIT +\r
 118                                               UCMST +\r
 119                                               UCCKPL +\r
 120                                               UCCKPH +\r
 121                                               UCMODE_3\r
 122                                               );\r
 123 \r
 124     //Clock polarity, phase select, msbFirst, SYNC, Mode0\r
 125     HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase +\r
 126                                              param->clockPolarity +\r
 127                                              param->msbFirst +\r
 128                                              UCSYNC +\r
 129                                              param->spiMode\r
 130                                              );\r
 131 }\r
 132 \r
 133 void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
 134                                           uint16_t clockPhase,\r
 135                                           uint16_t clockPolarity)\r
 136 {\r
 137     //Disable the USCI Module\r
 138     HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
 139 \r
 140     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL);\r
 141 \r
 142     HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
 143         clockPhase +\r
 144         clockPolarity\r
 145         );\r
 146 \r
 147     //Reset the UCSWRST bit to enable the USCI Module\r
 148     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
 149 }\r
 150 \r
 151 void EUSCI_B_SPI_transmitData(uint16_t baseAddress,\r
 152                               uint8_t transmitData)\r
 153 {\r
 154     HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData;\r
 155 }\r
 156 \r
 157 uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress)\r
 158 {\r
 159     return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
 160 }\r
 161 \r
 162 void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,\r
 163                                  uint8_t mask)\r
 164 {\r
 165     HWREG16(baseAddress + OFS_UCBxIE) |= mask;\r
 166 }\r
 167 \r
 168 void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,\r
 169                                   uint8_t mask)\r
 170 {\r
 171     HWREG16(baseAddress + OFS_UCBxIE) &= ~mask;\r
 172 }\r
 173 \r
 174 uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,\r
 175                                        uint8_t mask)\r
 176 {\r
 177     return (HWREG16(baseAddress + OFS_UCBxIFG) & mask);\r
 178 }\r
 179 \r
 180 void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,\r
 181                                 uint8_t mask)\r
 182 {\r
 183     HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask;\r
 184 }\r
 185 \r
 186 void EUSCI_B_SPI_enable(uint16_t baseAddress)\r
 187 {\r
 188     //Reset the UCSWRST bit to enable the USCI Module\r
 189     HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
 190 }\r
 191 \r
 192 void EUSCI_B_SPI_disable(uint16_t baseAddress)\r
 193 {\r
 194     //Set the UCSWRST bit to disable the USCI Module\r
 195     HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
 196 }\r
 197 \r
 198 uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress)\r
 199 {\r
 200     return (baseAddress + OFS_UCBxRXBUF);\r
 201 }\r
 202 \r
 203 uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress)\r
 204 {\r
 205     return (baseAddress + OFS_UCBxTXBUF);\r
 206 }\r
 207 \r
 208 uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress)\r
 209 {\r
 210     //Return the bus busy status.\r
 211     return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY);\r
 212 }\r
 213 \r
 214 #endif\r
 215 //*****************************************************************************\r
 216 //\r
 217 //! Close the doxygen group for eusci_b_spi_api\r
 218 //! @}\r
 219 //\r
 220 //*****************************************************************************\r