1 #ifndef XPARAMETERS_H /* prevent circular inclusions */
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2 #define XPARAMETERS_H /* by using protection macros */
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4 /* Definitions for bus frequencies */
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5 #define XPAR_CPU_M_AXI_DP_FREQ_HZ 100000000
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6 /******************************************************************/
\r
8 /* Canonical definitions for bus frequencies */
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9 /******************************************************************/
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11 #define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
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12 #define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 100000000
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14 /******************************************************************/
\r
17 /* Definitions for peripheral MICROBLAZE_0 */
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18 #define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15
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19 #define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
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20 #define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
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21 #define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
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22 #define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1
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23 #define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
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24 #define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000
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25 #define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
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26 #define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768
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27 #define XPAR_MICROBLAZE_0_DATA_SIZE 32
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28 #define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15
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29 #define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1
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30 #define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000
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31 #define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768
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32 #define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0
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33 #define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
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34 #define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF
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35 #define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8
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36 #define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1
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37 #define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8
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38 #define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32
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39 #define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
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40 #define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5
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41 #define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0
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42 #define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1
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43 #define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0
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44 #define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192
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45 #define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1
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46 #define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0
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47 #define XPAR_MICROBLAZE_0_D_AXI 1
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48 #define XPAR_MICROBLAZE_0_D_LMB 1
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49 #define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
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50 #define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
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51 #define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0
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52 #define XPAR_MICROBLAZE_0_ENDIANNESS 1
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53 #define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
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54 #define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1
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55 #define XPAR_MICROBLAZE_0_FREQ 100000000
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56 #define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
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57 #define XPAR_MICROBLAZE_0_FSL_LINKS 0
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58 #define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1
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59 #define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000
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60 #define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0
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61 #define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
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62 #define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF
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63 #define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8
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64 #define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1
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65 #define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8
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66 #define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1
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67 #define XPAR_MICROBLAZE_0_INTERCONNECT 2
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68 #define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
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69 #define XPAR_MICROBLAZE_0_I_AXI 0
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70 #define XPAR_MICROBLAZE_0_I_LMB 1
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71 #define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0
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72 #define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
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73 #define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
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74 #define XPAR_MICROBLAZE_0_M0_AXIS_PROTOCOL GENERIC
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75 #define XPAR_MICROBLAZE_0_M1_AXIS_DATA_WIDTH 32
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76 #define XPAR_MICROBLAZE_0_M1_AXIS_PROTOCOL GENERIC
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77 #define XPAR_MICROBLAZE_0_M2_AXIS_DATA_WIDTH 32
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78 #define XPAR_MICROBLAZE_0_M2_AXIS_PROTOCOL GENERIC
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79 #define XPAR_MICROBLAZE_0_M3_AXIS_DATA_WIDTH 32
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80 #define XPAR_MICROBLAZE_0_M3_AXIS_PROTOCOL GENERIC
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81 #define XPAR_MICROBLAZE_0_M4_AXIS_DATA_WIDTH 32
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82 #define XPAR_MICROBLAZE_0_M4_AXIS_PROTOCOL GENERIC
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83 #define XPAR_MICROBLAZE_0_M5_AXIS_DATA_WIDTH 32
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84 #define XPAR_MICROBLAZE_0_M5_AXIS_PROTOCOL GENERIC
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85 #define XPAR_MICROBLAZE_0_M6_AXIS_DATA_WIDTH 32
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86 #define XPAR_MICROBLAZE_0_M6_AXIS_PROTOCOL GENERIC
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87 #define XPAR_MICROBLAZE_0_M7_AXIS_DATA_WIDTH 32
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88 #define XPAR_MICROBLAZE_0_M7_AXIS_PROTOCOL GENERIC
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89 #define XPAR_MICROBLAZE_0_M8_AXIS_DATA_WIDTH 32
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90 #define XPAR_MICROBLAZE_0_M8_AXIS_PROTOCOL GENERIC
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91 #define XPAR_MICROBLAZE_0_M9_AXIS_DATA_WIDTH 32
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92 #define XPAR_MICROBLAZE_0_M9_AXIS_PROTOCOL GENERIC
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93 #define XPAR_MICROBLAZE_0_M10_AXIS_DATA_WIDTH 32
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94 #define XPAR_MICROBLAZE_0_M10_AXIS_PROTOCOL GENERIC
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95 #define XPAR_MICROBLAZE_0_M11_AXIS_DATA_WIDTH 32
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96 #define XPAR_MICROBLAZE_0_M11_AXIS_PROTOCOL GENERIC
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97 #define XPAR_MICROBLAZE_0_M12_AXIS_DATA_WIDTH 32
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98 #define XPAR_MICROBLAZE_0_M12_AXIS_PROTOCOL GENERIC
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99 #define XPAR_MICROBLAZE_0_M13_AXIS_DATA_WIDTH 32
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100 #define XPAR_MICROBLAZE_0_M13_AXIS_PROTOCOL GENERIC
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101 #define XPAR_MICROBLAZE_0_M14_AXIS_DATA_WIDTH 32
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102 #define XPAR_MICROBLAZE_0_M14_AXIS_PROTOCOL GENERIC
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103 #define XPAR_MICROBLAZE_0_M15_AXIS_DATA_WIDTH 32
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104 #define XPAR_MICROBLAZE_0_M15_AXIS_PROTOCOL GENERIC
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105 #define XPAR_MICROBLAZE_0_MMU_DTLB_SIZE 4
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106 #define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
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107 #define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
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108 #define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
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109 #define XPAR_MICROBLAZE_0_MMU_ZONES 2
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110 #define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
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111 #define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
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112 #define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
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113 #define XPAR_MICROBLAZE_0_M_AXI_DC_BUSER_WIDTH 1
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114 #define XPAR_MICROBLAZE_0_M_AXI_DC_DATA_WIDTH 32
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115 #define XPAR_MICROBLAZE_0_M_AXI_DC_EXCLUSIVE_ACCESS 0
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116 #define XPAR_MICROBLAZE_0_M_AXI_DC_RUSER_WIDTH 1
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117 #define XPAR_MICROBLAZE_0_M_AXI_DC_THREAD_ID_WIDTH 1
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118 #define XPAR_MICROBLAZE_0_M_AXI_DC_USER_SIGNALS 0
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119 #define XPAR_MICROBLAZE_0_M_AXI_DC_USER_VALUE 31
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120 #define XPAR_MICROBLAZE_0_M_AXI_DC_WUSER_WIDTH 1
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121 #define XPAR_MICROBLAZE_0_M_AXI_DP_ADDR_WIDTH 32
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122 #define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
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123 #define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
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124 #define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
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125 #define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1
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126 #define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
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127 #define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
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128 #define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
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129 #define XPAR_MICROBLAZE_0_M_AXI_IC_BUSER_WIDTH 1
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130 #define XPAR_MICROBLAZE_0_M_AXI_IC_DATA_WIDTH 32
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131 #define XPAR_MICROBLAZE_0_M_AXI_IC_RUSER_WIDTH 1
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132 #define XPAR_MICROBLAZE_0_M_AXI_IC_THREAD_ID_WIDTH 1
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133 #define XPAR_MICROBLAZE_0_M_AXI_IC_USER_SIGNALS 0
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134 #define XPAR_MICROBLAZE_0_M_AXI_IC_USER_VALUE 31
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135 #define XPAR_MICROBLAZE_0_M_AXI_IC_WUSER_WIDTH 1
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136 #define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
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137 #define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
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138 #define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
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139 #define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1
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140 #define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8
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141 #define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2
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142 #define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2
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143 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK 2
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144 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2
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145 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1
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146 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1
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147 #define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1
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148 #define XPAR_MICROBLAZE_0_OPTIMIZATION 0
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149 #define XPAR_MICROBLAZE_0_PC_WIDTH 32
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150 #define XPAR_MICROBLAZE_0_PVR 0
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151 #define XPAR_MICROBLAZE_0_PVR_USER1 0x00
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152 #define XPAR_MICROBLAZE_0_PVR_USER2 0x00000000
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153 #define XPAR_MICROBLAZE_0_RESET_MSR 0x00000000
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154 #define XPAR_MICROBLAZE_0_S0_AXIS_DATA_WIDTH 32
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155 #define XPAR_MICROBLAZE_0_S0_AXIS_PROTOCOL GENERIC
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156 #define XPAR_MICROBLAZE_0_S1_AXIS_DATA_WIDTH 32
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157 #define XPAR_MICROBLAZE_0_S1_AXIS_PROTOCOL GENERIC
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158 #define XPAR_MICROBLAZE_0_S2_AXIS_DATA_WIDTH 32
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159 #define XPAR_MICROBLAZE_0_S2_AXIS_PROTOCOL GENERIC
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160 #define XPAR_MICROBLAZE_0_S3_AXIS_DATA_WIDTH 32
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161 #define XPAR_MICROBLAZE_0_S3_AXIS_PROTOCOL GENERIC
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162 #define XPAR_MICROBLAZE_0_S4_AXIS_DATA_WIDTH 32
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163 #define XPAR_MICROBLAZE_0_S4_AXIS_PROTOCOL GENERIC
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164 #define XPAR_MICROBLAZE_0_S5_AXIS_DATA_WIDTH 32
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165 #define XPAR_MICROBLAZE_0_S5_AXIS_PROTOCOL GENERIC
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166 #define XPAR_MICROBLAZE_0_S6_AXIS_DATA_WIDTH 32
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167 #define XPAR_MICROBLAZE_0_S6_AXIS_PROTOCOL GENERIC
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168 #define XPAR_MICROBLAZE_0_S7_AXIS_DATA_WIDTH 32
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169 #define XPAR_MICROBLAZE_0_S7_AXIS_PROTOCOL GENERIC
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170 #define XPAR_MICROBLAZE_0_S8_AXIS_DATA_WIDTH 32
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171 #define XPAR_MICROBLAZE_0_S8_AXIS_PROTOCOL GENERIC
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172 #define XPAR_MICROBLAZE_0_S9_AXIS_DATA_WIDTH 32
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173 #define XPAR_MICROBLAZE_0_S9_AXIS_PROTOCOL GENERIC
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174 #define XPAR_MICROBLAZE_0_S10_AXIS_DATA_WIDTH 32
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175 #define XPAR_MICROBLAZE_0_S10_AXIS_PROTOCOL GENERIC
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176 #define XPAR_MICROBLAZE_0_S11_AXIS_DATA_WIDTH 32
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177 #define XPAR_MICROBLAZE_0_S11_AXIS_PROTOCOL GENERIC
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178 #define XPAR_MICROBLAZE_0_S12_AXIS_DATA_WIDTH 32
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179 #define XPAR_MICROBLAZE_0_S12_AXIS_PROTOCOL GENERIC
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180 #define XPAR_MICROBLAZE_0_S13_AXIS_DATA_WIDTH 32
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181 #define XPAR_MICROBLAZE_0_S13_AXIS_PROTOCOL GENERIC
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182 #define XPAR_MICROBLAZE_0_S14_AXIS_DATA_WIDTH 32
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183 #define XPAR_MICROBLAZE_0_S14_AXIS_PROTOCOL GENERIC
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184 #define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
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185 #define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
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186 #define XPAR_MICROBLAZE_0_SCO 0
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187 #define XPAR_MICROBLAZE_0_TRACE 1
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188 #define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1
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189 #define XPAR_MICROBLAZE_0_USE_BARREL 1
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190 #define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1
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191 #define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0
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192 #define XPAR_MICROBLAZE_0_USE_DCACHE 1
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193 #define XPAR_MICROBLAZE_0_USE_DIV 1
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194 #define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
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195 #define XPAR_MICROBLAZE_0_USE_EXT_BRK 0
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196 #define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0
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197 #define XPAR_MICROBLAZE_0_USE_FPU 2
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198 #define XPAR_MICROBLAZE_0_USE_HW_MUL 2
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199 #define XPAR_MICROBLAZE_0_USE_ICACHE 1
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200 #define XPAR_MICROBLAZE_0_USE_INTERRUPT 1
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201 #define XPAR_MICROBLAZE_0_USE_MMU 0
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202 #define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
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203 #define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
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204 #define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
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205 #define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1
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206 #define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0
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207 #define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR
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208 #define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze
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209 #define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2
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210 #define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1
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212 /******************************************************************/
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214 #define XPAR_CPU_ID 0
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215 #define XPAR_MICROBLAZE_ID 0
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216 #define XPAR_MICROBLAZE_ADDR_TAG_BITS 15
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217 #define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
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218 #define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
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219 #define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
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220 #define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
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221 #define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
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222 #define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000
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223 #define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
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224 #define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768
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225 #define XPAR_MICROBLAZE_DATA_SIZE 32
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226 #define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15
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227 #define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
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228 #define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
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229 #define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768
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230 #define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
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231 #define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
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232 #define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF
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233 #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8
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234 #define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
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235 #define XPAR_MICROBLAZE_DCACHE_VICTIMS 8
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236 #define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
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237 #define XPAR_MICROBLAZE_DEBUG_ENABLED 1
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238 #define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
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239 #define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
\r
240 #define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
\r
241 #define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
\r
242 #define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
\r
243 #define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
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244 #define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
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245 #define XPAR_MICROBLAZE_D_AXI 1
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246 #define XPAR_MICROBLAZE_D_LMB 1
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247 #define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
\r
248 #define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
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249 #define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
\r
250 #define XPAR_MICROBLAZE_ENDIANNESS 1
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251 #define XPAR_MICROBLAZE_FAULT_TOLERANT 0
\r
252 #define XPAR_MICROBLAZE_FPU_EXCEPTION 1
\r
253 #define XPAR_MICROBLAZE_FREQ 100000000
\r
254 #define XPAR_MICROBLAZE_FSL_EXCEPTION 0
\r
255 #define XPAR_MICROBLAZE_FSL_LINKS 0
\r
256 #define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
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257 #define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
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258 #define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
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259 #define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
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260 #define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF
\r
261 #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8
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262 #define XPAR_MICROBLAZE_ICACHE_STREAMS 1
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263 #define XPAR_MICROBLAZE_ICACHE_VICTIMS 8
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264 #define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
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265 #define XPAR_MICROBLAZE_INTERCONNECT 2
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266 #define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
\r
267 #define XPAR_MICROBLAZE_I_AXI 0
\r
268 #define XPAR_MICROBLAZE_I_LMB 1
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269 #define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
\r
270 #define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
\r
271 #define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
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272 #define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
\r
273 #define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
\r
274 #define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
\r
275 #define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
\r
276 #define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
\r
277 #define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
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278 #define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
\r
279 #define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
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280 #define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
\r
281 #define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
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282 #define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
\r
283 #define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
\r
284 #define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
\r
285 #define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
\r
286 #define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
\r
287 #define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
\r
288 #define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
\r
289 #define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
\r
290 #define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
\r
291 #define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
\r
292 #define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
\r
293 #define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
\r
294 #define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
\r
295 #define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
\r
296 #define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
\r
297 #define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
\r
298 #define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
\r
299 #define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
\r
300 #define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
\r
301 #define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
\r
302 #define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
\r
303 #define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
\r
304 #define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
\r
305 #define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
\r
306 #define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
\r
307 #define XPAR_MICROBLAZE_MMU_ZONES 2
\r
308 #define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
\r
309 #define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
\r
310 #define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
\r
311 #define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
\r
312 #define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
\r
313 #define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
\r
314 #define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
\r
315 #define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
\r
316 #define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
\r
317 #define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
\r
318 #define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
\r
319 #define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
\r
320 #define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
\r
321 #define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
\r
322 #define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
\r
323 #define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
\r
324 #define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
\r
325 #define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
\r
326 #define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
\r
327 #define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
\r
328 #define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
\r
329 #define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
\r
330 #define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
\r
331 #define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
\r
332 #define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
\r
333 #define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
\r
334 #define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
\r
335 #define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
\r
336 #define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
\r
337 #define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
\r
338 #define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8
\r
339 #define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2
\r
340 #define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2
\r
341 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
\r
342 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
\r
343 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
\r
344 #define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
\r
345 #define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
\r
346 #define XPAR_MICROBLAZE_OPTIMIZATION 0
\r
347 #define XPAR_MICROBLAZE_PC_WIDTH 32
\r
348 #define XPAR_MICROBLAZE_PVR 0
\r
349 #define XPAR_MICROBLAZE_PVR_USER1 0x00
\r
350 #define XPAR_MICROBLAZE_PVR_USER2 0x00000000
\r
351 #define XPAR_MICROBLAZE_RESET_MSR 0x00000000
\r
352 #define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
\r
353 #define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
\r
354 #define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
\r
355 #define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
\r
356 #define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
\r
357 #define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
\r
358 #define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
\r
359 #define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
\r
360 #define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
\r
361 #define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
\r
362 #define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
\r
363 #define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
\r
364 #define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
\r
365 #define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
\r
366 #define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
\r
367 #define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
\r
368 #define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
\r
369 #define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
\r
370 #define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
\r
371 #define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
\r
372 #define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
\r
373 #define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
\r
374 #define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
\r
375 #define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
\r
376 #define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
\r
377 #define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
\r
378 #define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
\r
379 #define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
\r
380 #define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
\r
381 #define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
\r
382 #define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
\r
383 #define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
\r
384 #define XPAR_MICROBLAZE_SCO 0
\r
385 #define XPAR_MICROBLAZE_TRACE 1
\r
386 #define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
\r
387 #define XPAR_MICROBLAZE_USE_BARREL 1
\r
388 #define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1
\r
389 #define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
\r
390 #define XPAR_MICROBLAZE_USE_DCACHE 1
\r
391 #define XPAR_MICROBLAZE_USE_DIV 1
\r
392 #define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
\r
393 #define XPAR_MICROBLAZE_USE_EXT_BRK 0
\r
394 #define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
\r
395 #define XPAR_MICROBLAZE_USE_FPU 2
\r
396 #define XPAR_MICROBLAZE_USE_HW_MUL 2
\r
397 #define XPAR_MICROBLAZE_USE_ICACHE 1
\r
398 #define XPAR_MICROBLAZE_USE_INTERRUPT 1
\r
399 #define XPAR_MICROBLAZE_USE_MMU 0
\r
400 #define XPAR_MICROBLAZE_USE_MSR_INSTR 1
\r
401 #define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
\r
402 #define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
\r
403 #define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
\r
404 #define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0
\r
405 #define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
\r
406 #define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
\r
407 #define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2
\r
408 #define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
\r
410 /******************************************************************/
\r
413 /******************************************************************/
\r
415 /* Definitions for driver BRAM */
\r
416 #define XPAR_XBRAM_NUM_INSTANCES 2
\r
418 /* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
\r
419 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 0
\r
420 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32
\r
421 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0
\r
422 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0
\r
423 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0
\r
424 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0
\r
425 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0
\r
426 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0
\r
427 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0
\r
428 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
\r
429 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
\r
430 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
\r
431 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
\r
432 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
\r
433 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
\r
436 /* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
\r
437 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 1
\r
438 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32
\r
439 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0
\r
440 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0
\r
441 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0
\r
442 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0
\r
443 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0
\r
444 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0
\r
445 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0
\r
446 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
\r
447 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
\r
448 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
\r
449 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
\r
450 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
\r
451 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
\r
454 /******************************************************************/
\r
456 /* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
\r
457 #define XPAR_BRAM_0_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
\r
458 #define XPAR_BRAM_0_DATA_WIDTH 32
\r
459 #define XPAR_BRAM_0_ECC 0
\r
460 #define XPAR_BRAM_0_FAULT_INJECT 0
\r
461 #define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
\r
462 #define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
\r
463 #define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
\r
464 #define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
\r
465 #define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
\r
466 #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
\r
467 #define XPAR_BRAM_0_WRITE_ACCESS 2
\r
468 #define XPAR_BRAM_0_BASEADDR 0x00000000
\r
469 #define XPAR_BRAM_0_HIGHADDR 0x0003FFFF
\r
471 /* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
\r
472 #define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
\r
473 #define XPAR_BRAM_1_DATA_WIDTH 32
\r
474 #define XPAR_BRAM_1_ECC 0
\r
475 #define XPAR_BRAM_1_FAULT_INJECT 0
\r
476 #define XPAR_BRAM_1_CE_FAILING_REGISTERS 0
\r
477 #define XPAR_BRAM_1_UE_FAILING_REGISTERS 0
\r
478 #define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0
\r
479 #define XPAR_BRAM_1_CE_COUNTER_WIDTH 0
\r
480 #define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0
\r
481 #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
\r
482 #define XPAR_BRAM_1_WRITE_ACCESS 2
\r
483 #define XPAR_BRAM_1_BASEADDR 0x00000000
\r
484 #define XPAR_BRAM_1_HIGHADDR 0x0003FFFF
\r
487 /******************************************************************/
\r
489 /* Definitions for driver EMACLITE */
\r
490 #define XPAR_XEMACLITE_NUM_INSTANCES 1
\r
492 /* Definitions for peripheral AXI_ETHERNETLITE_0 */
\r
493 #define XPAR_AXI_ETHERNETLITE_0_DEVICE_ID 0
\r
494 #define XPAR_AXI_ETHERNETLITE_0_BASEADDR 0x40E00000
\r
495 #define XPAR_AXI_ETHERNETLITE_0_HIGHADDR 0x40E0FFFF
\r
496 #define XPAR_AXI_ETHERNETLITE_0_TX_PING_PONG 1
\r
497 #define XPAR_AXI_ETHERNETLITE_0_RX_PING_PONG 1
\r
498 #define XPAR_AXI_ETHERNETLITE_0_INCLUDE_MDIO 1
\r
499 #define XPAR_AXI_ETHERNETLITE_0_INCLUDE_INTERNAL_LOOPBACK 0
\r
502 /******************************************************************/
\r
504 /* Canonical definitions for peripheral AXI_ETHERNETLITE_0 */
\r
505 #define XPAR_EMACLITE_0_DEVICE_ID XPAR_AXI_ETHERNETLITE_0_DEVICE_ID
\r
506 #define XPAR_EMACLITE_0_BASEADDR 0x40E00000
\r
507 #define XPAR_EMACLITE_0_HIGHADDR 0x40E0FFFF
\r
508 #define XPAR_EMACLITE_0_TX_PING_PONG 1
\r
509 #define XPAR_EMACLITE_0_RX_PING_PONG 1
\r
510 #define XPAR_EMACLITE_0_INCLUDE_MDIO 1
\r
511 #define XPAR_EMACLITE_0_INCLUDE_INTERNAL_LOOPBACK 0
\r
514 /******************************************************************/
\r
516 /* Definitions for driver GPIO */
\r
517 #define XPAR_XGPIO_NUM_INSTANCES 1
\r
519 /* Definitions for peripheral AXI_GPIO_0 */
\r
520 #define XPAR_AXI_GPIO_0_BASEADDR 0x40000000
\r
521 #define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF
\r
522 #define XPAR_AXI_GPIO_0_DEVICE_ID 0
\r
523 #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
\r
524 #define XPAR_AXI_GPIO_0_IS_DUAL 0
\r
527 /******************************************************************/
\r
529 /* Canonical definitions for peripheral AXI_GPIO_0 */
\r
530 #define XPAR_GPIO_0_BASEADDR 0x40000000
\r
531 #define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
\r
532 #define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
\r
533 #define XPAR_GPIO_0_INTERRUPT_PRESENT 0
\r
534 #define XPAR_GPIO_0_IS_DUAL 0
\r
537 /******************************************************************/
\r
539 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
\r
540 #define XPAR_XINTC_HAS_IPR 1
\r
541 #define XPAR_XINTC_HAS_SIE 1
\r
542 #define XPAR_XINTC_HAS_CIE 1
\r
543 #define XPAR_XINTC_HAS_IVR 1
\r
544 /* Definitions for driver INTC */
\r
545 #define XPAR_XINTC_NUM_INSTANCES 1
\r
547 /* Definitions for peripheral AXI_INTC_0 */
\r
548 #define XPAR_AXI_INTC_0_DEVICE_ID 0
\r
549 #define XPAR_AXI_INTC_0_BASEADDR 0x41200000
\r
550 #define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF
\r
551 #define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE
\r
552 #define XPAR_AXI_INTC_0_HAS_FAST 0
\r
553 #define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010
\r
554 #define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3
\r
557 /******************************************************************/
\r
559 #define XPAR_INTC_SINGLE_BASEADDR 0x41200000
\r
560 #define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
\r
561 #define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
\r
562 #define XPAR_AXI_INTC_0_TYPE 0
\r
563 #define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001
\r
564 #define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0
\r
565 #define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002
\r
566 #define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1
\r
567 #define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004
\r
568 #define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2
\r
570 /******************************************************************/
\r
572 /* Canonical definitions for peripheral AXI_INTC_0 */
\r
573 #define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
\r
574 #define XPAR_INTC_0_BASEADDR 0x41200000
\r
575 #define XPAR_INTC_0_HIGHADDR 0x4120FFFF
\r
576 #define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE
\r
577 #define XPAR_INTC_0_HAS_FAST 0
\r
578 #define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010
\r
579 #define XPAR_INTC_0_NUM_INTR_INPUTS 3
\r
580 #define XPAR_INTC_0_INTC_TYPE 0
\r
582 #define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
\r
583 #define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR
\r
584 #define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR
\r
586 /******************************************************************/
\r
588 /* Definitions for driver MIG_7SERIES */
\r
589 #define XPAR_XMIG7SERIES_NUM_INSTANCES 1
\r
591 /* Definitions for peripheral MIG_7SERIES_0 */
\r
592 #define XPAR_MIG_7SERIES_0_DEVICE_ID 0
\r
593 #define XPAR_MIG_7SERIES_0_DDR3_ROW_WIDTH 14
\r
594 #define XPAR_MIG_7SERIES_0_DDR3_COL_WIDTH 0
\r
595 #define XPAR_MIG_7SERIES_0_DDR3_BANK_WIDTH 3
\r
596 #define XPAR_MIG_7SERIES_0_DDR3_DQ_WIDTH 64
\r
599 /******************************************************************/
\r
602 /* Definitions for peripheral MIG_7SERIES_0 */
\r
603 #define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000
\r
604 #define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF
\r
607 /******************************************************************/
\r
609 /* Canonical definitions for peripheral MIG_7SERIES_0 */
\r
610 #define XPAR_MIG7SERIES_0_DEVICE_ID XPAR_MIG_7SERIES_0_DEVICE_ID
\r
611 #define XPAR_MIG7SERIES_0_DDR_ROW_WIDTH 14
\r
612 #define XPAR_MIG7SERIES_0_DDR_COL_WIDTH 0
\r
613 #define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3
\r
614 #define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64
\r
615 #define XPAR_MIG7SERIES_0_BASEADDR 0x80000000
\r
616 #define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF
\r
619 /******************************************************************/
\r
621 /* Definitions for driver TMRCTR */
\r
622 #define XPAR_XTMRCTR_NUM_INSTANCES 1
\r
624 /* Definitions for peripheral AXI_TIMER_0 */
\r
625 #define XPAR_AXI_TIMER_0_DEVICE_ID 0
\r
626 #define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000
\r
627 #define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF
\r
628 #define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000
\r
631 /******************************************************************/
\r
633 /* Canonical definitions for peripheral AXI_TIMER_0 */
\r
634 #define XPAR_TMRCTR_0_DEVICE_ID 0
\r
635 #define XPAR_TMRCTR_0_BASEADDR 0x41C00000
\r
636 #define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF
\r
637 #define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
\r
639 /******************************************************************/
\r
641 /* Definitions for driver UARTLITE */
\r
642 #define XPAR_XUARTLITE_NUM_INSTANCES 1
\r
644 /* Definitions for peripheral AXI_UARTLITE_0 */
\r
645 #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
\r
646 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF
\r
647 #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
\r
648 #define XPAR_AXI_UARTLITE_0_BAUDRATE 115200
\r
649 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0
\r
650 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
\r
651 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8
\r
654 /******************************************************************/
\r
656 /* Canonical definitions for peripheral AXI_UARTLITE_0 */
\r
657 #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
\r
658 #define XPAR_UARTLITE_0_BASEADDR 0x40600000
\r
659 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
\r
660 #define XPAR_UARTLITE_0_BAUDRATE 115200
\r
661 #define XPAR_UARTLITE_0_USE_PARITY 0
\r
662 #define XPAR_UARTLITE_0_ODD_PARITY 0
\r
663 #define XPAR_UARTLITE_0_DATA_BITS 8
\r
666 /******************************************************************/
\r
668 #endif /* end of protection macro */
\r
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