1 /******************************************************************************
3 * Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
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6 * of this software and associated documentation files (the "Software"), to deal
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12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This header file contains identifiers and driver functions (or
38 * macros) that can be used to access the device. The user should refer to the
39 * hardware device specification for more details of the device operation.
41 * The macros that are available in this file use a multiply to calculate the
42 * addresses of registers. The user can control whether that multiply is done
43 * at run time or at compile time. A constant passed as the channel parameter
44 * will cause the multiply to be done at compile time. A variable passed as the
45 * channel parameter will cause it to occur at run time.
48 * MODIFICATION HISTORY:
50 * Ver Who Date Changes
51 * ----- ---- -------- -----------------------------------------------
52 * 1.00a jhl 04/24/02 First release of low level driver
53 * 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
54 * change required the functions to be changed such that
55 * the interface is not compatible with previous versions.
56 * See the examples in the example directory for macros
57 * to help compile an application that was designed for
58 * previous versions of the driver. The interrupt registers
59 * are accessible using the ReadReg and WriteReg macros and
60 * a channel parameter was added to the other macros.
61 * 2.11a mta 03/21/07 Updated to new coding style
62 * 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
63 * 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
64 * XGpio_mReadReg to XGpio_ReadReg.
65 * Removed the macros XGpio_mSetDataDirection,
66 * XGpio_mGetDataReg and XGpio_mSetDataReg. Users
67 * should use XGpio_WriteReg/XGpio_ReadReg to achieve the
71 ******************************************************************************/
73 #ifndef XGPIO_L_H /* prevent circular inclusions */
74 #define XGPIO_L_H /* by using protection macros */
80 /***************************** Include Files *********************************/
82 #include "xil_types.h"
83 #include "xil_assert.h"
87 * XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is
88 * accessed through a DCR bus connected to a bridge
90 #define XPAR_XGPIO_USE_DCR_BRIDGE 0
93 #if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
97 /************************** Constant Definitions *****************************/
101 * Register offsets for this device.
104 #if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
106 #define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
107 #define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */
108 #define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */
109 #define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */
111 #define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */
112 #define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */
113 #define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */
117 #define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
118 #define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
119 #define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
120 #define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
122 #define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
123 #define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
124 #define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
130 /* The following constant describes the offset of each channels data and
131 * tristate register from the base address.
133 #define XGPIO_CHAN_OFFSET 8
135 /** @name Interrupt Status and Enable Register bitmaps and masks
137 * Bit definitions for the interrupt status register and interrupt enable
141 #define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
142 #define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
143 #define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
147 /** @name Global Interrupt Enable Register bitmaps and masks
149 * Bit definitions for the Global Interrupt Enable register
152 #define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
157 /**************************** Type Definitions *******************************/
160 /***************** Macros (Inline Functions) Definitions *********************/
163 * Define the appropriate I/O access method to memory mapped I/O or DCR.
165 #if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
167 #define XGpio_In32 XIo_DcrIn
168 #define XGpio_Out32 XIo_DcrOut
172 #define XGpio_In32 Xil_In32
173 #define XGpio_Out32 Xil_Out32
178 /****************************************************************************/
181 * Write a value to a GPIO register. A 32 bit write is performed. If the
182 * GPIO core is implemented in a smaller width, only the least significant data
185 * @param BaseAddress is the base address of the GPIO device.
186 * @param RegOffset is the register offset from the base to write to.
187 * @param Data is the data written to the register.
191 * @note C-style signature:
192 * void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
194 ****************************************************************************/
195 #define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
196 XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
198 /****************************************************************************/
201 * Read a value from a GPIO register. A 32 bit read is performed. If the
202 * GPIO core is implemented in a smaller width, only the least
203 * significant data is read from the register. The most significant data
206 * @param BaseAddress is the base address of the GPIO device.
207 * @param RegOffset is the register offset from the base to read from.
209 * @return Data read from the register.
211 * @note C-style signature:
212 * u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
214 ****************************************************************************/
215 #define XGpio_ReadReg(BaseAddress, RegOffset) \
216 XGpio_In32((BaseAddress) + (RegOffset))
218 /************************** Function Prototypes ******************************/
220 /************************** Variable Definitions *****************************/
226 #endif /* end of protection macro */