git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/mb_subsystem_wrapper.mmi

   1 <?xml version="1.0" encoding="UTF-8"?>\r
   2 <MemInfo Version="1" Minor="1">\r
   3   <Processor Endianness="Little" InstPath="mb_subsystem_i/microblaze_0">\r
   4     <AddressSpace Name="mb_subsystem_i_microblaze_0.mb_subsystem_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="65535">\r
   5       <BusBlock>\r
   6         <BitLane MemType="RAMB36" Placement="X2Y23">\r
   7           <DataWidth MSB="7" LSB="6"/>\r
   8           <AddressRange Begin="0" End="16383"/>\r
   9           <Parity ON="false" NumBits="0"/>\r
  10         </BitLane>\r
  11         <BitLane MemType="RAMB36" Placement="X3Y30">\r
  12           <DataWidth MSB="5" LSB="4"/>\r
  13           <AddressRange Begin="0" End="16383"/>\r
  14           <Parity ON="false" NumBits="0"/>\r
  15         </BitLane>\r
  16         <BitLane MemType="RAMB36" Placement="X2Y22">\r
  17           <DataWidth MSB="3" LSB="2"/>\r
  18           <AddressRange Begin="0" End="16383"/>\r
  19           <Parity ON="false" NumBits="0"/>\r
  20         </BitLane>\r
  21         <BitLane MemType="RAMB36" Placement="X3Y26">\r
  22           <DataWidth MSB="1" LSB="0"/>\r
  23           <AddressRange Begin="0" End="16383"/>\r
  24           <Parity ON="false" NumBits="0"/>\r
  25         </BitLane>\r
  26         <BitLane MemType="RAMB36" Placement="X3Y32">\r
  27           <DataWidth MSB="15" LSB="14"/>\r
  28           <AddressRange Begin="0" End="16383"/>\r
  29           <Parity ON="false" NumBits="0"/>\r
  30         </BitLane>\r
  31         <BitLane MemType="RAMB36" Placement="X1Y26">\r
  32           <DataWidth MSB="13" LSB="12"/>\r
  33           <AddressRange Begin="0" End="16383"/>\r
  34           <Parity ON="false" NumBits="0"/>\r
  35         </BitLane>\r
  36         <BitLane MemType="RAMB36" Placement="X3Y31">\r
  37           <DataWidth MSB="11" LSB="10"/>\r
  38           <AddressRange Begin="0" End="16383"/>\r
  39           <Parity ON="false" NumBits="0"/>\r
  40         </BitLane>\r
  41         <BitLane MemType="RAMB36" Placement="X2Y26">\r
  42           <DataWidth MSB="9" LSB="8"/>\r
  43           <AddressRange Begin="0" End="16383"/>\r
  44           <Parity ON="false" NumBits="0"/>\r
  45         </BitLane>\r
  46         <BitLane MemType="RAMB36" Placement="X2Y29">\r
  47           <DataWidth MSB="23" LSB="22"/>\r
  48           <AddressRange Begin="0" End="16383"/>\r
  49           <Parity ON="false" NumBits="0"/>\r
  50         </BitLane>\r
  51         <BitLane MemType="RAMB36" Placement="X2Y27">\r
  52           <DataWidth MSB="21" LSB="20"/>\r
  53           <AddressRange Begin="0" End="16383"/>\r
  54           <Parity ON="false" NumBits="0"/>\r
  55         </BitLane>\r
  56         <BitLane MemType="RAMB36" Placement="X4Y25">\r
  57           <DataWidth MSB="19" LSB="18"/>\r
  58           <AddressRange Begin="0" End="16383"/>\r
  59           <Parity ON="false" NumBits="0"/>\r
  60         </BitLane>\r
  61         <BitLane MemType="RAMB36" Placement="X2Y28">\r
  62           <DataWidth MSB="17" LSB="16"/>\r
  63           <AddressRange Begin="0" End="16383"/>\r
  64           <Parity ON="false" NumBits="0"/>\r
  65         </BitLane>\r
  66         <BitLane MemType="RAMB36" Placement="X2Y25">\r
  67           <DataWidth MSB="31" LSB="30"/>\r
  68           <AddressRange Begin="0" End="16383"/>\r
  69           <Parity ON="false" NumBits="0"/>\r
  70         </BitLane>\r
  71         <BitLane MemType="RAMB36" Placement="X2Y24">\r
  72           <DataWidth MSB="29" LSB="28"/>\r
  73           <AddressRange Begin="0" End="16383"/>\r
  74           <Parity ON="false" NumBits="0"/>\r
  75         </BitLane>\r
  76         <BitLane MemType="RAMB36" Placement="X3Y27">\r
  77           <DataWidth MSB="27" LSB="26"/>\r
  78           <AddressRange Begin="0" End="16383"/>\r
  79           <Parity ON="false" NumBits="0"/>\r
  80         </BitLane>\r
  81         <BitLane MemType="RAMB36" Placement="X3Y29">\r
  82           <DataWidth MSB="25" LSB="24"/>\r
  83           <AddressRange Begin="0" End="16383"/>\r
  84           <Parity ON="false" NumBits="0"/>\r
  85         </BitLane>\r
  86       </BusBlock>\r
  87     </AddressSpace>\r
  88   </Processor>\r
  89   <Config>\r
  90     <Option Name="Part" Val="xc7k325tffg900-2"/>\r
  91   </Config>\r
  92 </MemInfo>\r