git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.xml

   1
   2 <EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Wed Jul 27 11:49:37 2011">
   3
   4   <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
   5
   6   <EXTERNALPORTS>
   7     <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
   8     <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
   9     <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
  10     <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
  11     <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
  12     <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
  13     <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
  14     <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
  15     <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
  16     <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
  17     <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
  18     <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
  19     <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
  20     <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
  21     <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
  22     <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
  23     <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
  24     <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
  25     <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
  26     <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
  27     <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
  28     <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
  29     <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
  30     <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
  31     <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
  32     <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
  33     <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
  34     <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
  35     <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
  36     <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
  37     <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
  38     <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
  39     <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
  40     <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
  41     <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
  42     <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
  43     <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
  44     <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
  45   </EXTERNALPORTS>
  46
  47   <MODULES>
  48     <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
  49       <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
  50       <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
  51       <DOCUMENTATION>
  52         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
  53       </DOCUMENTATION>
  54       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
  55       <PARAMETERS>
  56         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
  57           <DESCRIPTION>Family</DESCRIPTION>
  58         </PARAMETER>
  59         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
  60           <DESCRIPTION>Base Family</DESCRIPTION>
  61         </PARAMETER>
  62         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
  63           <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
  64         </PARAMETER>
  65         <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
  66           <DESCRIPTION>Number of Master Slots </DESCRIPTION>
  67         </PARAMETER>
  68         <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
  69           <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
  70         </PARAMETER>
  71         <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
  72           <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
  73         </PARAMETER>
  74         <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
  75           <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
  76         </PARAMETER>
  77         <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
  78           <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
  79         </PARAMETER>
  80         <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
  81           <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
  82         </PARAMETER>
  83         <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
  84           <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
  85         </PARAMETER>
  86         <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
  87           <DESCRIPTION>AXI Protocol</DESCRIPTION>
  88         </PARAMETER>
  89         <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
  90           <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
  91         </PARAMETER>
  92         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000">
  93           <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
  94         </PARAMETER>
  95         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff">
  96           <DESCRIPTION>Master AXI High Address</DESCRIPTION>
  97         </PARAMETER>
  98         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
  99           <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
 100         </PARAMETER>
 101         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 102           <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
 103         </PARAMETER>
 104         <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 105           <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
 106         </PARAMETER>
 107         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
 108           <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
 109         </PARAMETER>
 110         <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 111           <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
 112         </PARAMETER>
 113         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
 114           <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
 115         </PARAMETER>
 116         <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 117           <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
 118         </PARAMETER>
 119         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
 120           <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
 121         </PARAMETER>
 122         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
 123           <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
 124         </PARAMETER>
 125         <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 126           <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
 127         </PARAMETER>
 128         <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 129           <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
 130         </PARAMETER>
 131         <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 132           <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
 133         </PARAMETER>
 134         <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
 135           <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
 136         </PARAMETER>
 137         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
 138           <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
 139         </PARAMETER>
 140         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
 141           <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
 142         </PARAMETER>
 143         <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 144           <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
 145         </PARAMETER>
 146         <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 147           <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
 148         </PARAMETER>
 149         <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 150           <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
 151         </PARAMETER>
 152         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003">
 153           <DESCRIPTION>AXI Connectivity</DESCRIPTION>
 154         </PARAMETER>
 155         <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 156           <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
 157         </PARAMETER>
 158         <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 159           <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
 160         </PARAMETER>
 161         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
 162           <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
 163         </PARAMETER>
 164         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
 165           <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
 166         </PARAMETER>
 167         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020">
 168           <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
 169         </PARAMETER>
 170         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002">
 171           <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
 172         </PARAMETER>
 173         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
 174           <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
 175         </PARAMETER>
 176         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
 177           <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
 178         </PARAMETER>
 179         <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 180           <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
 181         </PARAMETER>
 182         <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 183           <DESCRIPTION>Master AXI Secure</DESCRIPTION>
 184         </PARAMETER>
 185         <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 186           <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
 187         </PARAMETER>
 188         <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 189           <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
 190         </PARAMETER>
 191         <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 192           <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
 193         </PARAMETER>
 194         <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 195           <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
 196         </PARAMETER>
 197         <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 198           <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
 199         </PARAMETER>
 200         <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 201           <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
 202         </PARAMETER>
 203         <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 204           <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
 205         </PARAMETER>
 206         <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 207           <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
 208         </PARAMETER>
 209         <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 210           <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
 211         </PARAMETER>
 212         <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 213           <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
 214         </PARAMETER>
 215         <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 216           <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
 217         </PARAMETER>
 218         <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 219           <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
 220         </PARAMETER>
 221         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
 222           <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
 223         </PARAMETER>
 224         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
 225           <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
 226         </PARAMETER>
 227         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
 228           <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
 229         </PARAMETER>
 230         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
 231           <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
 232         </PARAMETER>
 233         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
 234           <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
 235         </PARAMETER>
 236         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 237           <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
 238         </PARAMETER>
 239         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 240           <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
 241         </PARAMETER>
 242         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 243           <DESCRIPTION>Master AXI W Register</DESCRIPTION>
 244         </PARAMETER>
 245         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 246           <DESCRIPTION>Master AXI R Register</DESCRIPTION>
 247         </PARAMETER>
 248         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 249           <DESCRIPTION>Master AXI B Register</DESCRIPTION>
 250         </PARAMETER>
 251         <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
 252           <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
 253         </PARAMETER>
 254         <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
 255           <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
 256         </PARAMETER>
 257         <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
 258           <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
 259         </PARAMETER>
 260         <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
 261           <DESCRIPTION>Generate Interrupts</DESCRIPTION>
 262         </PARAMETER>
 263         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
 264           <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
 265         </PARAMETER>
 266         <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
 267           <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
 268         </PARAMETER>
 269         <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
 270           <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
 271         </PARAMETER>
 272         <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
 273           <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
 274         </PARAMETER>
 275         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
 276           <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
 277         </PARAMETER>
 278         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
 279           <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
 280         </PARAMETER>
 281         <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
 282           <DESCRIPTION>Simulation debug</DESCRIPTION>
 283         </PARAMETER>
 284       </PARAMETERS>
 285       <PORTS>
 286         <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
 287         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
 288         <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 289         <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 290         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
 291         <PORT DEF_SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
 292           <SIGNALS>
 293             <SIGNAL NAME="clk_100_0000MHzPLL0"/>
 294             <SIGNAL NAME="clk_100_0000MHzPLL0"/>
 295           </SIGNALS>
 296         </PORT>
 297         <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 298         <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 299         <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
 300         <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 301         <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 302         <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 303         <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 304         <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 305         <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 306         <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
 307         <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 308         <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 309         <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 310         <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
 311         <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 312         <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
 313         <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 314         <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 315         <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 316         <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 317         <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
 318         <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 319         <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 320         <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 321         <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 322         <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
 323         <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 324         <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 325         <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 326         <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 327         <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 328         <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 329         <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
 330         <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 331         <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 332         <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 333         <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 334         <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 335         <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 336         <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
 337         <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 338         <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 339         <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 340         <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 341         <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 342         <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
 343         <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 344         <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 345         <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 346         <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 347         <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 348         <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 349         <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 350         <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
 351         <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 352         <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 353         <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 354         <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 355         <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
 356         <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 357         <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
 358         <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 359         <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 360         <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 361         <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 362         <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
 363         <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 364         <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 365         <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 366         <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 367         <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
 368         <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 369         <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 370         <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 371         <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 372         <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 373         <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 374         <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 375         <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
 376         <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 377         <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 378         <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 379         <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 380         <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 381         <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 382         <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
 383         <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 384         <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 385         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
 386         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
 387         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
 388         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
 389         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
 390         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
 391         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
 392         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
 393         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
 394         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
 395         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
 396         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
 397         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
 398         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
 399         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
 400         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
 401       </PORTS>
 402       <BUSINTERFACES>
 403         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
 404           <PORTMAPS>
 405             <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
 406             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
 407             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
 408             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
 409             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
 410             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
 411             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
 412             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
 413             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
 414             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
 415             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
 416             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
 417             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
 418             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
 419             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
 420             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
 421             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
 422           </PORTMAPS>
 423         </BUSINTERFACE>
 424       </BUSINTERFACES>
 425       <MEMORYMAP>
 426         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
 427           <SLAVES>
 428             <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
 429           </SLAVES>
 430         </MEMRANGE>
 431       </MEMORYMAP>
 432     </MODULE>
 433     <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
 434       <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
 435       <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
 436       <DOCUMENTATION>
 437         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
 438       </DOCUMENTATION>
 439       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
 440       <PARAMETERS>
 441         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
 442           <DESCRIPTION>Family</DESCRIPTION>
 443         </PARAMETER>
 444         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
 445           <DESCRIPTION>Base Family</DESCRIPTION>
 446         </PARAMETER>
 447         <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
 448           <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
 449         </PARAMETER>
 450         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7">
 451           <DESCRIPTION>Number of Master Slots </DESCRIPTION>
 452         </PARAMETER>
 453         <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
 454           <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
 455         </PARAMETER>
 456         <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
 457           <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
 458         </PARAMETER>
 459         <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
 460           <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
 461         </PARAMETER>
 462         <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
 463           <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
 464         </PARAMETER>
 465         <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
 466           <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
 467         </PARAMETER>
 468         <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
 469           <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
 470         </PARAMETER>
 471         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
 472           <DESCRIPTION>AXI Protocol</DESCRIPTION>
 473         </PARAMETER>
 474         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002">
 475           <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
 476         </PARAMETER>
 477         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000">
 478           <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
 479         </PARAMETER>
 480         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff">
 481           <DESCRIPTION>Master AXI High Address</DESCRIPTION>
 482         </PARAMETER>
 483         <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 484           <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
 485         </PARAMETER>
 486         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 487           <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
 488         </PARAMETER>
 489         <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 490           <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
 491         </PARAMETER>
 492         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
 493           <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
 494         </PARAMETER>
 495         <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 496           <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
 497         </PARAMETER>
 498         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080">
 499           <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
 500         </PARAMETER>
 501         <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 502           <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
 503         </PARAMETER>
 504         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
 505           <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
 506         </PARAMETER>
 507         <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 508           <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
 509         </PARAMETER>
 510         <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 511           <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
 512         </PARAMETER>
 513         <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 514           <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
 515         </PARAMETER>
 516         <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 517           <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
 518         </PARAMETER>
 519         <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
 520           <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
 521         </PARAMETER>
 522         <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 523           <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
 524         </PARAMETER>
 525         <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 526           <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
 527         </PARAMETER>
 528         <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 529           <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
 530         </PARAMETER>
 531         <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 532           <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
 533         </PARAMETER>
 534         <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
 535           <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
 536         </PARAMETER>
 537         <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
 538           <DESCRIPTION>AXI Connectivity</DESCRIPTION>
 539         </PARAMETER>
 540         <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 541           <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
 542         </PARAMETER>
 543         <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 544           <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
 545         </PARAMETER>
 546         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
 547           <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
 548         </PARAMETER>
 549         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111">
 550           <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
 551         </PARAMETER>
 552         <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
 553           <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
 554         </PARAMETER>
 555         <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
 556           <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
 557         </PARAMETER>
 558         <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
 559           <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
 560         </PARAMETER>
 561         <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
 562           <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
 563         </PARAMETER>
 564         <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 565           <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
 566         </PARAMETER>
 567         <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 568           <DESCRIPTION>Master AXI Secure</DESCRIPTION>
 569         </PARAMETER>
 570         <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 571           <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
 572         </PARAMETER>
 573         <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 574           <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
 575         </PARAMETER>
 576         <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 577           <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
 578         </PARAMETER>
 579         <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 580           <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
 581         </PARAMETER>
 582         <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 583           <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
 584         </PARAMETER>
 585         <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 586           <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
 587         </PARAMETER>
 588         <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 589           <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
 590         </PARAMETER>
 591         <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 592           <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
 593         </PARAMETER>
 594         <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 595           <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
 596         </PARAMETER>
 597         <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
 598           <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
 599         </PARAMETER>
 600         <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
 601           <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
 602         </PARAMETER>
 603         <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
 604           <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
 605         </PARAMETER>
 606         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 607           <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
 608         </PARAMETER>
 609         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 610           <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
 611         </PARAMETER>
 612         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 613           <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
 614         </PARAMETER>
 615         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 616           <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
 617         </PARAMETER>
 618         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
 619           <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
 620         </PARAMETER>
 621         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
 622           <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
 623         </PARAMETER>
 624         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
 625           <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
 626         </PARAMETER>
 627         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
 628           <DESCRIPTION>Master AXI W Register</DESCRIPTION>
 629         </PARAMETER>
 630         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
 631           <DESCRIPTION>Master AXI R Register</DESCRIPTION>
 632         </PARAMETER>
 633         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
 634           <DESCRIPTION>Master AXI B Register</DESCRIPTION>
 635         </PARAMETER>
 636         <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
 637           <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
 638         </PARAMETER>
 639         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
 640           <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
 641         </PARAMETER>
 642         <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
 643           <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
 644         </PARAMETER>
 645         <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
 646           <DESCRIPTION>Generate Interrupts</DESCRIPTION>
 647         </PARAMETER>
 648         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
 649           <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
 650         </PARAMETER>
 651         <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
 652           <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
 653         </PARAMETER>
 654         <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
 655           <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
 656         </PARAMETER>
 657         <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
 658           <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
 659         </PARAMETER>
 660         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
 661           <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
 662         </PARAMETER>
 663         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
 664           <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
 665         </PARAMETER>
 666         <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
 667           <DESCRIPTION>Simulation debug</DESCRIPTION>
 668         </PARAMETER>
 669       </PARAMETERS>
 670       <PORTS>
 671         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
 672         <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
 673         <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 674         <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 675         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
 676         <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 677         <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 678         <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 679         <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
 680         <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 681         <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 682         <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 683         <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 684         <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 685         <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 686         <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
 687         <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 688         <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 689         <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 690         <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
 691         <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 692         <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
 693         <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 694         <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 695         <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 696         <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 697         <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
 698         <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 699         <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 700         <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 701         <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 702         <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
 703         <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 704         <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 705         <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 706         <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 707         <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
 708         <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
 709         <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
 710         <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 711         <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 712         <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 713         <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 714         <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
 715         <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 716         <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
 717         <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 718         <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
 719         <PORT DEF_SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
 720           <SIGNALS>
 721             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 722             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 723             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 724             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 725             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 726             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 727             <SIGNAL NAME="clk_50_0000MHzPLL0"/>
 728           </SIGNALS>
 729         </PORT>
 730         <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 731         <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 732         <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
 733         <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 734         <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 735         <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 736         <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 737         <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 738         <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 739         <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 740         <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
 741         <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 742         <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 743         <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 744         <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 745         <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
 746         <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 747         <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
 748         <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 749         <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 750         <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 751         <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 752         <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
 753         <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 754         <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 755         <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 756         <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
 757         <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
 758         <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 759         <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 760         <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 761         <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 762         <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
 763         <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 764         <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
 765         <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
 766         <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 767         <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 768         <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
 769         <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
 770         <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
 771         <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 772         <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
 773         <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 774         <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
 775         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
 776         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
 777         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
 778         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
 779         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
 780         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
 781         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
 782         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
 783         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
 784         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
 785         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
 786         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
 787         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
 788         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
 789         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
 790         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
 791       </PORTS>
 792       <BUSINTERFACES>
 793         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
 794           <PORTMAPS>
 795             <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
 796             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
 797             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
 798             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
 799             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
 800             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
 801             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
 802             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
 803             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
 804             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
 805             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
 806             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
 807             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
 808             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
 809             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
 810             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
 811             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
 812           </PORTMAPS>
 813         </BUSINTERFACE>
 814       </BUSINTERFACES>
 815       <MEMORYMAP>
 816         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
 817           <SLAVES>
 818             <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
 819           </SLAVES>
 820         </MEMRANGE>
 821       </MEMORYMAP>
 822     </MODULE>
 823     <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
 824       <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
 825       <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
 826       <DOCUMENTATION>
 827         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
 828       </DOCUMENTATION>
 829       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
 830       <PARAMETERS>
 831         <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
 832         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
 833         <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
 834         <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
 835         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
 836         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
 837         <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
 838           <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
 839         </PARAMETER>
 840         <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
 841         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
 842         <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
 843           <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
 844         </PARAMETER>
 845         <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
 846         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
 847           <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
 848         </PARAMETER>
 849         <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
 850           <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
 851         </PARAMETER>
 852         <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
 853         <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
 854         <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
 855         <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
 856         <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
 857         <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
 858         <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
 859         <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
 860         <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
 861         <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
 862         <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
 863         <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
 864         <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
 865         <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
 866         <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
 867         <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
 868         <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
 869         <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
 870         <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
 871         <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
 872         <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
 873         <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
 874         <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
 875         <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
 876         <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
 877         <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
 878         <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
 879         <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
 880         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
 881         <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
 882         <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
 883         <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
 884         <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
 885         <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
 886         <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
 887           <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
 888         </PARAMETER>
 889         <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
 890           <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
 891         </PARAMETER>
 892         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
 893           <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
 894         </PARAMETER>
 895         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="1">
 896           <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
 897         </PARAMETER>
 898         <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
 899           <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
 900         </PARAMETER>
 901         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1">
 902           <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
 903         </PARAMETER>
 904         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
 905           <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
 906         </PARAMETER>
 907         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
 908           <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
 909         </PARAMETER>
 910         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="1">
 911           <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
 912         </PARAMETER>
 913         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1">
 914           <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
 915         </PARAMETER>
 916         <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
 917           <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
 918         </PARAMETER>
 919         <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
 920           <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
 921         </PARAMETER>
 922         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1">
 923           <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
 924         </PARAMETER>
 925         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1">
 926           <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
 927         </PARAMETER>
 928         <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
 929           <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
 930         </PARAMETER>
 931         <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
 932           <DESCRIPTION>&lt;qt&gt;Enable stack protection&lt;/qt&gt;</DESCRIPTION>
 933         </PARAMETER>
 934         <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0">
 935           <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
 936         </PARAMETER>
 937         <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
 938           <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
 939         </PARAMETER>
 940         <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
 941           <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
 942         </PARAMETER>
 943         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
 944           <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
 945         </PARAMETER>
 946         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7">
 947           <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
 948         </PARAMETER>
 949         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2">
 950           <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
 951         </PARAMETER>
 952         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2">
 953           <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
 954         </PARAMETER>
 955         <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
 956           <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
 957         </PARAMETER>
 958         <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
 959           <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
 960         </PARAMETER>
 961         <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
 962           <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
 963         </PARAMETER>
 964         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
 965           <DESCRIPTION>&lt;qt&gt;Generate Illegal Instruction Exception for NULL Instruction&lt;/qt&gt;</DESCRIPTION>
 966         </PARAMETER>
 967         <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
 968           <DESCRIPTION>Number of Stream Links </DESCRIPTION>
 969         </PARAMETER>
 970         <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
 971         <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
 972           <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
 973         </PARAMETER>
 974         <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 975         <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 976         <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 977         <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 978         <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 979         <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 980         <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 981         <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 982         <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 983         <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 984         <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 985         <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 986         <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 987         <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 988         <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 989         <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 990         <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 991         <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 992         <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 993         <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 994         <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 995         <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 996         <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 997         <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 998         <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
 999         <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1000         <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1001         <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1002         <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1003         <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1004         <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1005         <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
1006         <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1007         <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1008         <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1009         <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1010         <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1011         <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1012         <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1013         <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1014         <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1015         <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1016         <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1017         <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1018         <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1019         <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1020         <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1021         <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1022         <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1023         <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1024         <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1025         <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1026         <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1027         <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1028         <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1029         <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1030         <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1031         <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1032         <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1033         <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1034         <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1035         <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1036         <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1037         <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1038         <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
1039           <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
1040         </PARAMETER>
1041         <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
1042           <DESCRIPTION>I-Cache High Address </DESCRIPTION>
1043         </PARAMETER>
1044         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
1045           <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
1046         </PARAMETER>
1047         <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
1048           <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
1049         </PARAMETER>
1050         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="13"/>
1051         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
1052           <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
1053         </PARAMETER>
1054         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
1055         <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
1056           <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
1057         </PARAMETER>
1058         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
1059           <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
1060         </PARAMETER>
1061         <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
1062         <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
1063           <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
1064         </PARAMETER>
1065         <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
1066           <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
1067         </PARAMETER>
1068         <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
1069           <DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION>
1070         </PARAMETER>
1071         <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
1072         <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
1073         <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
1074         <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
1075         <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
1076         <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
1077         <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1078         <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
1079         <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
1080         <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
1081         <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
1082         <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
1083         <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
1084         <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
1085         <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
1086         <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
1087         <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
1088         <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
1089           <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
1090         </PARAMETER>
1091         <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
1092           <DESCRIPTION>D-Cache High Address</DESCRIPTION>
1093         </PARAMETER>
1094         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
1095           <DESCRIPTION>Enable Data Cache</DESCRIPTION>
1096         </PARAMETER>
1097         <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
1098           <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
1099         </PARAMETER>
1100         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="13"/>
1101         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
1102           <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
1103         </PARAMETER>
1104         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
1105         <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
1106           <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
1107         </PARAMETER>
1108         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
1109           <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
1110         </PARAMETER>
1111         <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
1112         <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
1113           <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
1114         </PARAMETER>
1115         <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
1116           <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
1117         </PARAMETER>
1118         <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
1119           <DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION>
1120         </PARAMETER>
1121         <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
1122         <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
1123         <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
1124         <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
1125         <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
1126         <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
1127         <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
1128         <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
1129         <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
1130         <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
1131         <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
1132         <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
1133         <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
1134         <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
1135         <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
1136         <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
1137         <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
1138         <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
1139         <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
1140         <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
1141           <DESCRIPTION>Memory Management</DESCRIPTION>
1142         </PARAMETER>
1143         <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
1144           <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
1145         </PARAMETER>
1146         <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
1147           <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
1148         </PARAMETER>
1149         <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
1150           <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
1151         </PARAMETER>
1152         <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
1153           <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
1154         </PARAMETER>
1155         <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
1156           <DESCRIPTION>Privileged Instructions</DESCRIPTION>
1157         </PARAMETER>
1158         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
1159         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
1160         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
1161         <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
1162           <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
1163         </PARAMETER>
1164         <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
1165           <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
1166         </PARAMETER>
1167         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
1168         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
1169         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
1170         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
1171         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
1172         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
1173         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
1174         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
1175         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
1176         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
1177         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
1178         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
1179         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
1180         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
1181         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
1182       </PARAMETERS>
1183       <PORTS>
1184         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
1185         <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
1186         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
1187         <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
1188         <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
1189         <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
1190         <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
1191         <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
1192         <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
1193         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
1194         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
1195         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
1196         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
1197         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
1198         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
1199         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
1200         <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
1201         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
1202         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1203         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1204         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
1205         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
1206         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
1207         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1208         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1209         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
1210         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
1211         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
1212         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
1213         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
1214         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
1215         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
1216         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
1217         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
1218         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
1219         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
1220         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
1221         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
1222         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
1223         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
1224         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
1225         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
1226         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
1227         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
1228         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
1229         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1230         <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
1231         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
1232         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
1233         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
1234         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
1235         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
1236         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
1237         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
1238         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
1239         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
1240         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
1241         <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
1242         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
1243         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1244         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1245         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
1246         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
1247         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
1248         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1249         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1250         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
1251         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
1252         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
1253         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
1254         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
1255         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
1256         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
1257         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
1258         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
1259         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
1260         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
1261         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
1262         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
1263         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
1264         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
1265         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
1266         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
1267         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
1268         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
1269         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
1270         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
1271         <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
1272         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
1273         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
1274         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
1275         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
1276         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
1277         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
1278         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
1279         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
1280         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
1281         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
1282         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
1283         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
1284         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
1285         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
1286         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
1287         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
1288         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
1289         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
1290         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
1291         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
1292         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
1293         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
1294         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
1295         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
1296         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
1297         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
1298         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
1299         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
1300         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
1301         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
1302         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
1303         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
1304         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
1305         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
1306         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
1307         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
1308         <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
1309         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
1310         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
1311         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
1312         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
1313         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
1314         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
1315         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
1316         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
1317         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
1318         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
1319         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
1320         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
1321         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
1322         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
1323         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
1324         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
1325         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
1326         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
1327         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
1328         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
1329         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
1330         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
1331         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
1332         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
1333         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
1334         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
1335         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
1336         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
1337         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
1338         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
1339         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
1340         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
1341         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
1342         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
1343         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
1344         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
1345         <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
1346         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
1347         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
1348         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
1349         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
1350         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
1351         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
1352         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
1353         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
1354         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
1355         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
1356         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
1357         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
1358         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
1359         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
1360         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
1361         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
1362         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
1363         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
1364         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
1365         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
1366         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
1367         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
1368         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
1369         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
1370         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
1371         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
1372         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
1373         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
1374         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
1375         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
1376         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
1377         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
1378         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
1379         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
1380         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
1381         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
1382         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
1383         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
1384         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
1385         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
1386         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
1387         <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
1388         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
1389         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
1390         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
1391         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
1392         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
1393         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
1394         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
1395         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
1396         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
1397         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
1398         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
1399         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
1400         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
1401         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
1402         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
1403         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
1404         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
1405         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
1406         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
1407         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
1408         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
1409         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
1410         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
1411         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
1412         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
1413         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
1414         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
1415         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
1416         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
1417         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
1418         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
1419         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
1420         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
1421         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
1422         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
1423         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
1424         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
1425         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
1426         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
1427         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
1428         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
1429         <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
1430         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
1431         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
1432         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
1433         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
1434         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
1435         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
1436         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
1437         <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
1438         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1439         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
1440         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1441         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
1442         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
1443         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
1444         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
1445         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1446         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
1447         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
1448         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
1449         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
1450         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1451         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
1452         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
1453         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
1454         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1455         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
1456         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
1457         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
1458         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
1459         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
1460         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
1461         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
1462         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
1463         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
1464         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
1465         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
1466         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
1467         <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
1468         <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1469         <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
1470         <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1471         <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
1472         <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
1473         <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1474         <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
1475         <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1476         <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
1477         <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
1478         <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1479         <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
1480         <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1481         <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
1482         <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
1483         <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1484         <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
1485         <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1486         <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
1487         <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
1488         <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1489         <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
1490         <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1491         <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
1492         <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
1493         <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1494         <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
1495         <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1496         <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
1497         <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
1498         <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1499         <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
1500         <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1501         <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
1502         <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
1503         <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1504         <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
1505         <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1506         <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
1507         <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
1508         <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1509         <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
1510         <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1511         <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
1512         <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
1513         <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1514         <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
1515         <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1516         <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
1517         <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
1518         <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1519         <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
1520         <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1521         <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
1522         <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
1523         <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1524         <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
1525         <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1526         <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
1527         <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
1528         <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1529         <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
1530         <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1531         <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
1532         <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
1533         <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1534         <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
1535         <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1536         <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
1537         <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
1538         <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1539         <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
1540         <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1541         <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
1542         <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
1543         <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1544         <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
1545         <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1546         <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
1547         <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
1548         <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1549         <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
1550         <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1551         <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
1552         <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
1553         <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1554         <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
1555         <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1556         <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
1557         <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
1558         <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1559         <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
1560         <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1561         <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
1562         <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
1563         <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1564         <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
1565         <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1566         <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
1567         <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
1568         <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1569         <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
1570         <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1571         <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
1572         <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
1573         <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1574         <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
1575         <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1576         <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
1577         <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
1578         <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1579         <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
1580         <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1581         <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
1582         <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
1583         <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1584         <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
1585         <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1586         <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
1587         <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
1588         <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1589         <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
1590         <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1591         <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
1592         <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
1593         <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1594         <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
1595         <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1596         <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
1597         <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
1598         <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1599         <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
1600         <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1601         <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
1602         <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
1603         <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1604         <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
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1606         <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
1607         <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
1608         <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1609         <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
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1611         <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
1612         <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
1613         <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1614         <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
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1616         <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
1617         <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
1618         <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1619         <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
1620         <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1621         <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
1622         <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
1623         <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1624         <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
1625         <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1626         <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
1627         <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
1628         <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
1629         <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
1630         <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
1631         <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
1632         <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
1633         <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
1634         <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
1635         <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
1636         <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
1637         <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
1638         <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
1639         <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
1640         <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
1641         <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
1642         <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
1643         <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
1644         <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
1645         <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
1646         <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
1647         <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
1648         <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
1649         <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
1650         <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
1651         <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
1652         <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
1653         <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
1654         <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
1655         <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
1656         <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
1657         <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
1658         <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
1659         <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
1660         <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
1661         <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
1662         <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
1663         <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
1664         <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
1665         <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
1666         <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
1667         <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
1668         <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
1669         <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
1670         <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
1671         <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
1672         <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
1673         <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
1674         <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
1675         <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
1676         <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
1677         <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
1678         <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
1679         <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
1680         <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
1681         <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
1682         <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
1683         <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
1684         <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
1685         <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
1686         <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
1687         <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
1688         <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
1689         <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
1690         <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
1691         <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
1692         <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
1693         <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
1694         <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
1695         <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
1696         <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
1697         <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
1698         <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
1699         <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
1700         <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
1701         <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
1702         <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
1703         <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
1704         <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
1705         <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
1706         <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
1707         <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
1708         <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
1709         <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
1710         <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
1711         <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
1712         <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
1713         <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
1714         <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
1715         <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
1716         <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
1717         <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
1718         <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
1719         <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
1720         <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
1721         <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
1722         <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
1723         <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
1724         <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
1725         <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
1726         <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
1727         <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
1728         <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
1729         <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
1730         <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
1731         <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
1732         <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
1733         <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
1734         <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
1735         <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
1736         <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
1737         <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
1738         <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
1739         <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
1740         <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
1741         <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
1742         <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
1743         <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
1744         <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
1745         <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
1746         <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
1747         <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
1748         <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
1749         <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
1750         <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
1751         <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
1752         <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
1753         <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
1754         <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
1755         <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
1756         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1757         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
1758         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1759         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
1760         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
1761         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1762         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
1763         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1764         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
1765         <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
1766         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1767         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
1768         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1769         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
1770         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
1771         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1772         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
1773         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1774         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
1775         <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
1776       </PORTS>
1777       <BUSINTERFACES>
1778         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
1779           <PORTMAPS>
1780             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1781             <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
1782             <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
1783             <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
1784             <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
1785             <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
1786             <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
1787             <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
1788             <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
1789             <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
1790             <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
1791             <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
1792             <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
1793             <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
1794             <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
1795             <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
1796             <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
1797             <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
1798             <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
1799             <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
1800             <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
1801             <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
1802             <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
1803             <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
1804             <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
1805             <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
1806             <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
1807             <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
1808             <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
1809             <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
1810             <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
1811           </PORTMAPS>
1812         </BUSINTERFACE>
1813         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
1814           <PORTMAPS>
1815             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1816             <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
1817             <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
1818             <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
1819             <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
1820             <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
1821             <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
1822             <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
1823             <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
1824             <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
1825             <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
1826             <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
1827             <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
1828             <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
1829             <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
1830             <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
1831             <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
1832             <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
1833             <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
1834             <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
1835             <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
1836             <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
1837             <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
1838             <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
1839             <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
1840             <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
1841             <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
1842             <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
1843             <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
1844             <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
1845             <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
1846           </PORTMAPS>
1847         </BUSINTERFACE>
1848         <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
1849           <PORTMAPS>
1850             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1851             <PORTMAP DIR="I" PHYSICAL="RESET"/>
1852             <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
1853             <PORTMAP DIR="I" PHYSICAL="DREADY"/>
1854             <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
1855             <PORTMAP DIR="I" PHYSICAL="DCE"/>
1856             <PORTMAP DIR="I" PHYSICAL="DUE"/>
1857             <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
1858             <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
1859             <PORTMAP DIR="O" PHYSICAL="D_AS"/>
1860             <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
1861             <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
1862             <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
1863           </PORTMAPS>
1864         </BUSINTERFACE>
1865         <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
1866           <PORTMAPS>
1867             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1868             <PORTMAP DIR="I" PHYSICAL="RESET"/>
1869             <PORTMAP DIR="I" PHYSICAL="INSTR"/>
1870             <PORTMAP DIR="I" PHYSICAL="IREADY"/>
1871             <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
1872             <PORTMAP DIR="I" PHYSICAL="ICE"/>
1873             <PORTMAP DIR="I" PHYSICAL="IUE"/>
1874             <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
1875             <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
1876             <PORTMAP DIR="O" PHYSICAL="I_AS"/>
1877           </PORTMAPS>
1878         </BUSINTERFACE>
1879         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
1880           <PORTMAPS>
1881             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1882             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
1883             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
1884             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
1885             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
1886             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
1887             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
1888             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
1889             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
1890             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
1891             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
1892             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
1893             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
1894             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
1895             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
1896             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
1897             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
1898             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
1899             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
1900             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
1901             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
1902             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
1903             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
1904             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
1905             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
1906             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
1907             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
1908             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
1909             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
1910             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
1911             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
1912             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
1913             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
1914             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
1915             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
1916             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
1917             <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
1918             <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
1919           </PORTMAPS>
1920         </BUSINTERFACE>
1921         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
1922           <PORTMAPS>
1923             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1924             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
1925             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
1926             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
1927             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
1928             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
1929             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
1930             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
1931             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
1932             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
1933             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
1934             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
1935             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
1936             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
1937             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
1938             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
1939             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
1940             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
1941             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
1942             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
1943             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
1944             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
1945             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
1946             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
1947             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
1948             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
1949             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
1950             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
1951             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
1952             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
1953             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
1954             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
1955             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
1956             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
1957             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
1958             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
1959             <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
1960             <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
1961           </PORTMAPS>
1962         </BUSINTERFACE>
1963         <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
1964           <PORTMAPS>
1965             <PORTMAP DIR="I" PHYSICAL="CLK"/>
1966             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
1967             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
1968             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
1969             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
1970             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
1971             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
1972             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
1973             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
1974             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
1975             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
1976             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
1977             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
1978             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
1979             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
1980             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
1981             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
1982             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
1983             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
1984             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
1985             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
1986             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
1987             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
1988             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
1989             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
1990             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
1991             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
1992             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
1993             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
1994             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
1995             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
1996             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
1997             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
1998             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
1999             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
2000             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
2001             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
2002             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
2003             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
2004             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
2005             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
2006             <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
2007             <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
2008           </PORTMAPS>
2009         </BUSINTERFACE>
2010         <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
2011           <PORTMAPS>
2012             <PORTMAP DIR="I" PHYSICAL="CLK"/>
2013             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
2014             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
2015             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
2016             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
2017             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
2018             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
2019             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
2020             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
2021             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
2022             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
2023             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
2024             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
2025             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
2026             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
2027             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
2028             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
2029             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
2030             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
2031             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
2032             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
2033             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
2034             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
2035             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
2036             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
2037             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
2038             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
2039             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
2040             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
2041             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
2042             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
2043             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
2044             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
2045             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
2046             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
2047             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
2048             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
2049             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
2050             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
2051             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
2052             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
2053             <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
2054             <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
2055           </PORTMAPS>
2056         </BUSINTERFACE>
2057         <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
2058           <PORTMAPS>
2059             <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
2060             <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
2061             <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
2062             <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
2063             <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
2064             <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
2065             <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
2066             <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
2067           </PORTMAPS>
2068         </BUSINTERFACE>
2069         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
2070           <PORTMAPS>
2071             <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
2072             <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
2073             <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
2074             <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
2075             <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
2076             <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
2077             <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
2078             <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
2079             <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
2080             <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
2081             <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
2082             <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
2083             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
2084             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
2085             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
2086             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
2087             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
2088             <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
2089             <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
2090             <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
2091             <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
2092             <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
2093             <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
2094             <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
2095             <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
2096             <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
2097             <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
2098             <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
2099             <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
2100             <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
2101           </PORTMAPS>
2102         </BUSINTERFACE>
2103         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
2104           <PORTMAPS>
2105             <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
2106             <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
2107             <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
2108             <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
2109             <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
2110           </PORTMAPS>
2111         </BUSINTERFACE>
2112         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
2113           <PORTMAPS>
2114             <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
2115             <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
2116             <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
2117             <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
2118             <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
2119           </PORTMAPS>
2120         </BUSINTERFACE>
2121         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
2122           <PORTMAPS>
2123             <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
2124             <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
2125             <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
2126             <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
2127             <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
2128           </PORTMAPS>
2129         </BUSINTERFACE>
2130         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
2131           <PORTMAPS>
2132             <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
2133             <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
2134             <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
2135             <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
2136             <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
2137           </PORTMAPS>
2138         </BUSINTERFACE>
2139         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
2140           <PORTMAPS>
2141             <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
2142             <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
2143             <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
2144             <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
2145             <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
2146           </PORTMAPS>
2147         </BUSINTERFACE>
2148         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
2149           <PORTMAPS>
2150             <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
2151             <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
2152             <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
2153             <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
2154             <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
2155           </PORTMAPS>
2156         </BUSINTERFACE>
2157         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
2158           <PORTMAPS>
2159             <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
2160             <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
2161             <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
2162             <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
2163             <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
2164           </PORTMAPS>
2165         </BUSINTERFACE>
2166         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
2167           <PORTMAPS>
2168             <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
2169             <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
2170             <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
2171             <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
2172             <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
2173           </PORTMAPS>
2174         </BUSINTERFACE>
2175         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
2176           <PORTMAPS>
2177             <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
2178             <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
2179             <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
2180             <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
2181             <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
2182           </PORTMAPS>
2183         </BUSINTERFACE>
2184         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
2185           <PORTMAPS>
2186             <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
2187             <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
2188             <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
2189             <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
2190             <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
2191           </PORTMAPS>
2192         </BUSINTERFACE>
2193         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
2194           <PORTMAPS>
2195             <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
2196             <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
2197             <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
2198             <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
2199             <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
2200           </PORTMAPS>
2201         </BUSINTERFACE>
2202         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
2203           <PORTMAPS>
2204             <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
2205             <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
2206             <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
2207             <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
2208             <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
2209           </PORTMAPS>
2210         </BUSINTERFACE>
2211         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
2212           <PORTMAPS>
2213             <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
2214             <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
2215             <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
2216             <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
2217             <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
2218           </PORTMAPS>
2219         </BUSINTERFACE>
2220         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
2221           <PORTMAPS>
2222             <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
2223             <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
2224             <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
2225             <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
2226             <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
2227           </PORTMAPS>
2228         </BUSINTERFACE>
2229         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
2230           <PORTMAPS>
2231             <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
2232             <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
2233             <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
2234             <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
2235             <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
2236           </PORTMAPS>
2237         </BUSINTERFACE>
2238         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
2239           <PORTMAPS>
2240             <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
2241             <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
2242             <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
2243             <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
2244             <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
2245           </PORTMAPS>
2246         </BUSINTERFACE>
2247         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
2248           <PORTMAPS>
2249             <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
2250             <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
2251             <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
2252             <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
2253             <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
2254           </PORTMAPS>
2255         </BUSINTERFACE>
2256         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
2257           <PORTMAPS>
2258             <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
2259             <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
2260             <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
2261             <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
2262             <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
2263           </PORTMAPS>
2264         </BUSINTERFACE>
2265         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
2266           <PORTMAPS>
2267             <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
2268             <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
2269             <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
2270             <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
2271             <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
2272           </PORTMAPS>
2273         </BUSINTERFACE>
2274         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
2275           <PORTMAPS>
2276             <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
2277             <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
2278             <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
2279             <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
2280             <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
2281           </PORTMAPS>
2282         </BUSINTERFACE>
2283         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
2284           <PORTMAPS>
2285             <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
2286             <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
2287             <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
2288             <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
2289             <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
2290           </PORTMAPS>
2291         </BUSINTERFACE>
2292         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
2293           <PORTMAPS>
2294             <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
2295             <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
2296             <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
2297             <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
2298             <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
2299           </PORTMAPS>
2300         </BUSINTERFACE>
2301         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
2302           <PORTMAPS>
2303             <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
2304             <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
2305             <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
2306             <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
2307             <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
2308           </PORTMAPS>
2309         </BUSINTERFACE>
2310         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
2311           <PORTMAPS>
2312             <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
2313             <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
2314             <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
2315             <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
2316             <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
2317           </PORTMAPS>
2318         </BUSINTERFACE>
2319         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
2320           <PORTMAPS>
2321             <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
2322             <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
2323             <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
2324             <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
2325             <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
2326           </PORTMAPS>
2327         </BUSINTERFACE>
2328         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
2329           <PORTMAPS>
2330             <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
2331             <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
2332             <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
2333             <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
2334             <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
2335           </PORTMAPS>
2336         </BUSINTERFACE>
2337         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
2338           <PORTMAPS>
2339             <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
2340             <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
2341             <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
2342             <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
2343             <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
2344           </PORTMAPS>
2345         </BUSINTERFACE>
2346         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
2347           <PORTMAPS>
2348             <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
2349             <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
2350             <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
2351             <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
2352             <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
2353           </PORTMAPS>
2354         </BUSINTERFACE>
2355         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
2356           <PORTMAPS>
2357             <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
2358             <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
2359             <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
2360             <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
2361             <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
2362           </PORTMAPS>
2363         </BUSINTERFACE>
2364         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
2365           <PORTMAPS>
2366             <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
2367             <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
2368             <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
2369             <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
2370             <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
2371           </PORTMAPS>
2372         </BUSINTERFACE>
2373         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
2374           <PORTMAPS>
2375             <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
2376             <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
2377             <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
2378             <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
2379             <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
2380           </PORTMAPS>
2381         </BUSINTERFACE>
2382         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
2383           <PORTMAPS>
2384             <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
2385             <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
2386             <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
2387             <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
2388             <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
2389           </PORTMAPS>
2390         </BUSINTERFACE>
2391         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
2392           <PORTMAPS>
2393             <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
2394             <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
2395             <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
2396             <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
2397             <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
2398           </PORTMAPS>
2399         </BUSINTERFACE>
2400         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
2401           <PORTMAPS>
2402             <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
2403             <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
2404             <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
2405             <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
2406             <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
2407           </PORTMAPS>
2408         </BUSINTERFACE>
2409         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
2410           <PORTMAPS>
2411             <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
2412             <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
2413             <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
2414             <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
2415             <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
2416           </PORTMAPS>
2417         </BUSINTERFACE>
2418         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
2419           <PORTMAPS>
2420             <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
2421             <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
2422             <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
2423             <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
2424             <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
2425           </PORTMAPS>
2426         </BUSINTERFACE>
2427         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
2428           <PORTMAPS>
2429             <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
2430             <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
2431             <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
2432             <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
2433             <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
2434           </PORTMAPS>
2435         </BUSINTERFACE>
2436         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
2437           <PORTMAPS>
2438             <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
2439             <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
2440             <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
2441             <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
2442             <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
2443           </PORTMAPS>
2444         </BUSINTERFACE>
2445         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
2446           <PORTMAPS>
2447             <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
2448             <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
2449             <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
2450             <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
2451             <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
2452           </PORTMAPS>
2453         </BUSINTERFACE>
2454         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
2455           <PORTMAPS>
2456             <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
2457             <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
2458             <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
2459             <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
2460             <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
2461           </PORTMAPS>
2462         </BUSINTERFACE>
2463         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
2464           <PORTMAPS>
2465             <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
2466             <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
2467             <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
2468             <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
2469             <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
2470           </PORTMAPS>
2471         </BUSINTERFACE>
2472         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
2473           <PORTMAPS>
2474             <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
2475             <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
2476             <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
2477             <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
2478             <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
2479           </PORTMAPS>
2480         </BUSINTERFACE>
2481         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
2482           <PORTMAPS>
2483             <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
2484             <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
2485             <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
2486             <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
2487             <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
2488           </PORTMAPS>
2489         </BUSINTERFACE>
2490         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
2491           <PORTMAPS>
2492             <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
2493             <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
2494             <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
2495             <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
2496             <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
2497           </PORTMAPS>
2498         </BUSINTERFACE>
2499         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
2500           <PORTMAPS>
2501             <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
2502             <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
2503             <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
2504             <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
2505             <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
2506           </PORTMAPS>
2507         </BUSINTERFACE>
2508         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
2509           <PORTMAPS>
2510             <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
2511             <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
2512             <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
2513             <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
2514             <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
2515           </PORTMAPS>
2516         </BUSINTERFACE>
2517         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
2518           <PORTMAPS>
2519             <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
2520             <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
2521             <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
2522             <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
2523             <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
2524           </PORTMAPS>
2525         </BUSINTERFACE>
2526         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
2527           <PORTMAPS>
2528             <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
2529             <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
2530             <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
2531             <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
2532             <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
2533           </PORTMAPS>
2534         </BUSINTERFACE>
2535         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
2536           <PORTMAPS>
2537             <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
2538             <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
2539             <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
2540             <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
2541             <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
2542           </PORTMAPS>
2543         </BUSINTERFACE>
2544         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
2545           <PORTMAPS>
2546             <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
2547             <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
2548             <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
2549             <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
2550             <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
2551           </PORTMAPS>
2552         </BUSINTERFACE>
2553         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
2554           <PORTMAPS>
2555             <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
2556             <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
2557             <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
2558             <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
2559             <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
2560           </PORTMAPS>
2561         </BUSINTERFACE>
2562         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
2563           <PORTMAPS>
2564             <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
2565             <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
2566             <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
2567             <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
2568             <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
2569           </PORTMAPS>
2570         </BUSINTERFACE>
2571         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
2572           <PORTMAPS>
2573             <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
2574             <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
2575             <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
2576             <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
2577             <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
2578           </PORTMAPS>
2579         </BUSINTERFACE>
2580         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
2581           <PORTMAPS>
2582             <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
2583             <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
2584             <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
2585             <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
2586             <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
2587           </PORTMAPS>
2588         </BUSINTERFACE>
2589         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
2590           <PORTMAPS>
2591             <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
2592             <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
2593             <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
2594             <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
2595             <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
2596           </PORTMAPS>
2597         </BUSINTERFACE>
2598         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
2599           <PORTMAPS>
2600             <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
2601             <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
2602             <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
2603             <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
2604             <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
2605           </PORTMAPS>
2606         </BUSINTERFACE>
2607         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
2608           <PORTMAPS>
2609             <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
2610             <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
2611             <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
2612             <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
2613             <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
2614           </PORTMAPS>
2615         </BUSINTERFACE>
2616         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
2617           <PORTMAPS>
2618             <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
2619             <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
2620             <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
2621             <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
2622             <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
2623           </PORTMAPS>
2624         </BUSINTERFACE>
2625         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
2626           <PORTMAPS>
2627             <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
2628             <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
2629             <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
2630             <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
2631             <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
2632           </PORTMAPS>
2633         </BUSINTERFACE>
2634         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
2635           <PORTMAPS>
2636             <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
2637             <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
2638             <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
2639             <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
2640             <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
2641           </PORTMAPS>
2642         </BUSINTERFACE>
2643         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
2644           <PORTMAPS>
2645             <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
2646             <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
2647             <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
2648             <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
2649             <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
2650           </PORTMAPS>
2651         </BUSINTERFACE>
2652         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
2653           <PORTMAPS>
2654             <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
2655             <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
2656             <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
2657             <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
2658             <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
2659           </PORTMAPS>
2660         </BUSINTERFACE>
2661         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
2662           <PORTMAPS>
2663             <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
2664             <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
2665             <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
2666             <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
2667             <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
2668           </PORTMAPS>
2669         </BUSINTERFACE>
2670         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
2671           <PORTMAPS>
2672             <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
2673             <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
2674             <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
2675             <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
2676             <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
2677           </PORTMAPS>
2678         </BUSINTERFACE>
2679         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2680           <PORTMAPS>
2681             <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
2682             <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
2683             <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
2684             <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
2685           </PORTMAPS>
2686         </BUSINTERFACE>
2687         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2688           <PORTMAPS>
2689             <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
2690             <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
2691             <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
2692             <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
2693           </PORTMAPS>
2694         </BUSINTERFACE>
2695         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2696           <PORTMAPS>
2697             <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
2698             <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
2699             <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
2700             <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
2701           </PORTMAPS>
2702         </BUSINTERFACE>
2703         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2704           <PORTMAPS>
2705             <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
2706             <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
2707             <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
2708             <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
2709           </PORTMAPS>
2710         </BUSINTERFACE>
2711         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2712           <PORTMAPS>
2713             <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
2714             <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
2715             <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
2716             <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
2717           </PORTMAPS>
2718         </BUSINTERFACE>
2719         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2720           <PORTMAPS>
2721             <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
2722             <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
2723             <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
2724             <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
2725           </PORTMAPS>
2726         </BUSINTERFACE>
2727         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2728           <PORTMAPS>
2729             <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
2730             <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
2731             <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
2732             <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
2733           </PORTMAPS>
2734         </BUSINTERFACE>
2735         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2736           <PORTMAPS>
2737             <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
2738             <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
2739             <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
2740             <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
2741           </PORTMAPS>
2742         </BUSINTERFACE>
2743         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2744           <PORTMAPS>
2745             <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
2746             <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
2747             <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
2748             <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
2749           </PORTMAPS>
2750         </BUSINTERFACE>
2751         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2752           <PORTMAPS>
2753             <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
2754             <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
2755             <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
2756             <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
2757           </PORTMAPS>
2758         </BUSINTERFACE>
2759         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2760           <PORTMAPS>
2761             <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
2762             <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
2763             <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
2764             <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
2765           </PORTMAPS>
2766         </BUSINTERFACE>
2767         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2768           <PORTMAPS>
2769             <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
2770             <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
2771             <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
2772             <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
2773           </PORTMAPS>
2774         </BUSINTERFACE>
2775         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2776           <PORTMAPS>
2777             <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
2778             <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
2779             <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
2780             <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
2781           </PORTMAPS>
2782         </BUSINTERFACE>
2783         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2784           <PORTMAPS>
2785             <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
2786             <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
2787             <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
2788             <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
2789           </PORTMAPS>
2790         </BUSINTERFACE>
2791         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2792           <PORTMAPS>
2793             <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
2794             <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
2795             <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
2796             <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
2797           </PORTMAPS>
2798         </BUSINTERFACE>
2799         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2800           <PORTMAPS>
2801             <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
2802             <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
2803             <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
2804             <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
2805           </PORTMAPS>
2806         </BUSINTERFACE>
2807         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2808           <PORTMAPS>
2809             <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
2810             <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
2811             <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
2812             <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
2813           </PORTMAPS>
2814         </BUSINTERFACE>
2815         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2816           <PORTMAPS>
2817             <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
2818             <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
2819             <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
2820             <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
2821           </PORTMAPS>
2822         </BUSINTERFACE>
2823         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2824           <PORTMAPS>
2825             <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
2826             <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
2827             <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
2828             <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
2829           </PORTMAPS>
2830         </BUSINTERFACE>
2831         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2832           <PORTMAPS>
2833             <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
2834             <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
2835             <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
2836             <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
2837           </PORTMAPS>
2838         </BUSINTERFACE>
2839         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2840           <PORTMAPS>
2841             <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
2842             <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
2843             <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
2844             <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
2845           </PORTMAPS>
2846         </BUSINTERFACE>
2847         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2848           <PORTMAPS>
2849             <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
2850             <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
2851             <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
2852             <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
2853           </PORTMAPS>
2854         </BUSINTERFACE>
2855         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2856           <PORTMAPS>
2857             <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
2858             <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
2859             <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
2860             <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
2861           </PORTMAPS>
2862         </BUSINTERFACE>
2863         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2864           <PORTMAPS>
2865             <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
2866             <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
2867             <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
2868             <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
2869           </PORTMAPS>
2870         </BUSINTERFACE>
2871         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2872           <PORTMAPS>
2873             <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
2874             <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
2875             <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
2876             <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
2877           </PORTMAPS>
2878         </BUSINTERFACE>
2879         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2880           <PORTMAPS>
2881             <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
2882             <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
2883             <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
2884             <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
2885           </PORTMAPS>
2886         </BUSINTERFACE>
2887         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2888           <PORTMAPS>
2889             <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
2890             <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
2891             <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
2892             <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
2893           </PORTMAPS>
2894         </BUSINTERFACE>
2895         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2896           <PORTMAPS>
2897             <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
2898             <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
2899             <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
2900             <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
2901           </PORTMAPS>
2902         </BUSINTERFACE>
2903         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2904           <PORTMAPS>
2905             <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
2906             <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
2907             <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
2908             <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
2909           </PORTMAPS>
2910         </BUSINTERFACE>
2911         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2912           <PORTMAPS>
2913             <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
2914             <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
2915             <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
2916             <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
2917           </PORTMAPS>
2918         </BUSINTERFACE>
2919         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2920           <PORTMAPS>
2921             <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
2922             <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
2923             <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
2924             <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
2925           </PORTMAPS>
2926         </BUSINTERFACE>
2927         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2928           <PORTMAPS>
2929             <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
2930             <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
2931             <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
2932             <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
2933           </PORTMAPS>
2934         </BUSINTERFACE>
2935         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
2936           <PORTMAPS>
2937             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
2938             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
2939             <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
2940             <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
2941             <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
2942             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
2943             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
2944             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
2945             <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
2946             <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
2947           </PORTMAPS>
2948         </BUSINTERFACE>
2949         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
2950           <PORTMAPS>
2951             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
2952             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
2953             <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
2954             <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
2955             <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
2956             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
2957             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
2958             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
2959             <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
2960             <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
2961           </PORTMAPS>
2962         </BUSINTERFACE>
2963       </BUSINTERFACES>
2964       <MEMORYMAP>
2965         <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
2966           <ACCESSROUTE>
2967             <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
2968           </ACCESSROUTE>
2969         </MEMRANGE>
2970         <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
2971           <ACCESSROUTE>
2972             <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
2973           </ACCESSROUTE>
2974         </MEMRANGE>
2975         <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2976           <ACCESSROUTE>
2977             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2978           </ACCESSROUTE>
2979         </MEMRANGE>
2980         <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2981           <ACCESSROUTE>
2982             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2983           </ACCESSROUTE>
2984         </MEMRANGE>
2985         <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2986           <ACCESSROUTE>
2987             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2988           </ACCESSROUTE>
2989         </MEMRANGE>
2990         <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2991           <ACCESSROUTE>
2992             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2993           </ACCESSROUTE>
2994         </MEMRANGE>
2995         <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2996           <ACCESSROUTE>
2997             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2998           </ACCESSROUTE>
2999         </MEMRANGE>
3000         <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
3001           <ACCESSROUTE>
3002             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
3003           </ACCESSROUTE>
3004         </MEMRANGE>
3005         <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
3006           <ACCESSROUTE>
3007             <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
3008           </ACCESSROUTE>
3009         </MEMRANGE>
3010         <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
3011           <ACCESSROUTE>
3012             <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
3013           </ACCESSROUTE>
3014         </MEMRANGE>
3015       </MEMORYMAP>
3016       <PERIPHERALS>
3017         <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
3018         <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
3019         <PERIPHERAL INSTANCE="debug_module"/>
3020         <PERIPHERAL INSTANCE="RS232_Uart_1"/>
3021         <PERIPHERAL INSTANCE="LEDs_4Bits"/>
3022         <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
3023         <PERIPHERAL INSTANCE="Ethernet_Lite"/>
3024         <PERIPHERAL INSTANCE="axi_timer_0"/>
3025         <PERIPHERAL INSTANCE="microblaze_0_intc"/>
3026         <PERIPHERAL INSTANCE="MCB_DDR3"/>
3027       </PERIPHERALS>
3028       <INTERRUPTINFO TYPE="TARGET">
3029         <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
3030       </INTERRUPTINFO>
3031     </MODULE>
3032     <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
3033       <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
3034       <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
3035       <DOCUMENTATION>
3036         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
3037       </DOCUMENTATION>
3038       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3039       <PARAMETERS>
3040         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
3041           <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
3042         </PARAMETER>
3043         <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
3044           <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
3045         </PARAMETER>
3046         <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
3047           <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
3048         </PARAMETER>
3049         <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
3050           <DESCRIPTION>Active High External Reset</DESCRIPTION>
3051         </PARAMETER>
3052       </PARAMETERS>
3053       <PORTS>
3054         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
3055         <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
3056         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
3057         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3058         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
3059         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
3060         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
3061         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3062         <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
3063         <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
3064         <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3065         <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3066         <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3067         <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3068         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3069         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
3070         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
3071         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
3072         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3073         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3074         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
3075         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
3076         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
3077         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
3078         <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
3079       </PORTS>
3080       <BUSINTERFACES/>
3081       <IOINTERFACES>
3082         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
3083       </IOINTERFACES>
3084     </MODULE>
3085     <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
3086       <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
3087       <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
3088       <DOCUMENTATION>
3089         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
3090       </DOCUMENTATION>
3091       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3092       <PARAMETERS>
3093         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
3094           <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
3095         </PARAMETER>
3096         <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
3097           <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
3098         </PARAMETER>
3099         <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
3100           <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
3101         </PARAMETER>
3102         <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
3103           <DESCRIPTION>Active High External Reset</DESCRIPTION>
3104         </PARAMETER>
3105       </PARAMETERS>
3106       <PORTS>
3107         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
3108         <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
3109         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
3110         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3111         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
3112         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
3113         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
3114         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3115         <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
3116         <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
3117         <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3118         <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3119         <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3120         <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
3121         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3122         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
3123         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
3124         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
3125         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3126         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3127         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
3128         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
3129         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
3130         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
3131         <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
3132       </PORTS>
3133       <BUSINTERFACES/>
3134       <IOINTERFACES>
3135         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
3136       </IOINTERFACES>
3137     </MODULE>
3138     <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
3139       <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
3140       <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
3141       <DOCUMENTATION>
3142         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
3143       </DOCUMENTATION>
3144       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3145       <PARAMETERS>
3146         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3147           <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
3148         </PARAMETER>
3149         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
3150           <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
3151         </PARAMETER>
3152         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
3153         <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
3154           <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
3155         </PARAMETER>
3156         <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
3157           <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
3158         </PARAMETER>
3159         <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
3160           <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
3161         </PARAMETER>
3162         <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
3163           <DESCRIPTION>Error Correction Code </DESCRIPTION>
3164         </PARAMETER>
3165         <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
3166           <DESCRIPTION>Select Interconnect </DESCRIPTION>
3167         </PARAMETER>
3168         <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
3169           <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
3170         </PARAMETER>
3171         <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
3172           <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
3173         </PARAMETER>
3174         <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
3175           <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
3176         </PARAMETER>
3177         <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
3178           <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
3179         </PARAMETER>
3180         <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
3181           <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
3182         </PARAMETER>
3183         <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
3184           <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
3185         </PARAMETER>
3186         <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
3187           <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
3188         </PARAMETER>
3189         <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
3190           <DESCRIPTION>Write Access setting </DESCRIPTION>
3191         </PARAMETER>
3192         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
3193           <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
3194         </PARAMETER>
3195         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3196           <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
3197         </PARAMETER>
3198         <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
3199           <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
3200         </PARAMETER>
3201         <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
3202           <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
3203         </PARAMETER>
3204         <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
3205           <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
3206         </PARAMETER>
3207         <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
3208           <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
3209         </PARAMETER>
3210         <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
3211           <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
3212         </PARAMETER>
3213         <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
3214           <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
3215         </PARAMETER>
3216         <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
3217           <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
3218         </PARAMETER>
3219         <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
3220           <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
3221         </PARAMETER>
3222         <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
3223           <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
3224         </PARAMETER>
3225         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
3226           <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
3227         </PARAMETER>
3228         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3229           <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
3230         </PARAMETER>
3231         <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
3232           <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
3233         </PARAMETER>
3234         <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
3235           <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
3236         </PARAMETER>
3237         <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
3238           <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
3239         </PARAMETER>
3240       </PARAMETERS>
3241       <PORTS>
3242         <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
3243         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
3244         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3245         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3246         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
3247         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
3248         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
3249         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
3250         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3251         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
3252         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
3253         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
3254         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
3255         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3256         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3257         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3258         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
3259         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3260         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
3261         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
3262         <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
3263         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3264         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
3265         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
3266         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
3267         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
3268         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3269         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
3270         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
3271         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
3272         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3273         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
3274         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
3275         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
3276         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
3277         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
3278         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
3279         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
3280         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3281         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3282         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3283         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3284         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
3285         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
3286         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
3287         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
3288         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
3289         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3290         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
3291         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
3292         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
3293         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
3294         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
3295         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3296         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3297         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3298         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
3299         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
3300         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3301         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
3302         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3303         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
3304         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
3305         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
3306         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
3307         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
3308         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
3309         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
3310         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
3311         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
3312         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
3313         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
3314         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
3315         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
3316         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
3317         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
3318         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
3319         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
3320         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
3321         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
3322       </PORTS>
3323       <BUSINTERFACES>
3324         <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
3325           <PORTMAPS>
3326             <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
3327             <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
3328             <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
3329             <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
3330             <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
3331             <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
3332             <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
3333             <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
3334             <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
3335             <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
3336             <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
3337             <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
3338             <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
3339           </PORTMAPS>
3340         </BUSINTERFACE>
3341         <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
3342           <PORTMAPS>
3343             <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
3344             <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
3345             <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
3346             <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
3347             <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
3348             <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
3349             <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
3350           </PORTMAPS>
3351         </BUSINTERFACE>
3352         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
3353           <PORTMAPS>
3354             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
3355             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
3356             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
3357             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
3358             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
3359             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
3360             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
3361             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
3362             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
3363             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
3364             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
3365             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
3366             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
3367             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
3368             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
3369             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
3370             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
3371             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
3372             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
3373             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
3374             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
3375             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
3376             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
3377             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
3378             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
3379             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
3380             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
3381             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
3382             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
3383             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
3384             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
3385             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
3386             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
3387             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
3388             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
3389             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
3390             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
3391             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
3392             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
3393             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
3394           </PORTMAPS>
3395         </BUSINTERFACE>
3396         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3397           <PORTMAPS>
3398             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
3399             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
3400             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
3401             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
3402             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
3403             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
3404             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
3405             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
3406             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
3407             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
3408             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
3409             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
3410             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
3411             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
3412             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
3413             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
3414             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
3415             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
3416             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
3417           </PORTMAPS>
3418         </BUSINTERFACE>
3419       </BUSINTERFACES>
3420       <MEMORYMAP>
3421         <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
3422           <SLAVES>
3423             <SLAVE BUSINTERFACE="SLMB"/>
3424           </SLAVES>
3425         </MEMRANGE>
3426         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3427           <SLAVES>
3428             <SLAVE BUSINTERFACE="SPLB_CTRL"/>
3429           </SLAVES>
3430         </MEMRANGE>
3431         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3432           <SLAVES>
3433             <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
3434           </SLAVES>
3435         </MEMRANGE>
3436       </MEMORYMAP>
3437     </MODULE>
3438     <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
3439       <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
3440       <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
3441       <DOCUMENTATION>
3442         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
3443       </DOCUMENTATION>
3444       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3445       <PARAMETERS>
3446         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3447           <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
3448         </PARAMETER>
3449         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
3450           <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
3451         </PARAMETER>
3452         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
3453         <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
3454           <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
3455         </PARAMETER>
3456         <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
3457           <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
3458         </PARAMETER>
3459         <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
3460           <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
3461         </PARAMETER>
3462         <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
3463           <DESCRIPTION>Error Correction Code </DESCRIPTION>
3464         </PARAMETER>
3465         <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
3466           <DESCRIPTION>Select Interconnect </DESCRIPTION>
3467         </PARAMETER>
3468         <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
3469           <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
3470         </PARAMETER>
3471         <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
3472           <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
3473         </PARAMETER>
3474         <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
3475           <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
3476         </PARAMETER>
3477         <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
3478           <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
3479         </PARAMETER>
3480         <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
3481           <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
3482         </PARAMETER>
3483         <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
3484           <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
3485         </PARAMETER>
3486         <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
3487           <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
3488         </PARAMETER>
3489         <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
3490           <DESCRIPTION>Write Access setting </DESCRIPTION>
3491         </PARAMETER>
3492         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
3493           <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
3494         </PARAMETER>
3495         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3496           <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
3497         </PARAMETER>
3498         <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
3499           <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
3500         </PARAMETER>
3501         <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
3502           <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
3503         </PARAMETER>
3504         <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
3505           <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
3506         </PARAMETER>
3507         <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
3508           <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
3509         </PARAMETER>
3510         <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
3511           <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
3512         </PARAMETER>
3513         <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
3514           <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
3515         </PARAMETER>
3516         <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
3517           <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
3518         </PARAMETER>
3519         <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
3520           <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
3521         </PARAMETER>
3522         <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
3523           <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
3524         </PARAMETER>
3525         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
3526           <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
3527         </PARAMETER>
3528         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
3529           <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
3530         </PARAMETER>
3531         <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
3532           <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
3533         </PARAMETER>
3534         <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
3535           <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
3536         </PARAMETER>
3537         <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
3538           <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
3539         </PARAMETER>
3540       </PARAMETERS>
3541       <PORTS>
3542         <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
3543         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
3544         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3545         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3546         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
3547         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
3548         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
3549         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
3550         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
3551         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
3552         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
3553         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
3554         <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
3555         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3556         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3557         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3558         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
3559         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
3560         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
3561         <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
3562         <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
3563         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3564         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
3565         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
3566         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
3567         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
3568         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3569         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
3570         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
3571         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
3572         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3573         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
3574         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
3575         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
3576         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
3577         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
3578         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
3579         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
3580         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3581         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3582         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3583         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3584         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
3585         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
3586         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
3587         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
3588         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
3589         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3590         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
3591         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
3592         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
3593         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
3594         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
3595         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3596         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3597         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3598         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
3599         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
3600         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3601         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
3602         <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
3603         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
3604         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
3605         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
3606         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
3607         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
3608         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
3609         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
3610         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
3611         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
3612         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
3613         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
3614         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
3615         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
3616         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
3617         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
3618         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
3619         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
3620         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
3621         <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
3622       </PORTS>
3623       <BUSINTERFACES>
3624         <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
3625           <PORTMAPS>
3626             <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
3627             <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
3628             <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
3629             <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
3630             <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
3631             <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
3632             <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
3633             <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
3634             <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
3635             <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
3636             <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
3637             <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
3638             <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
3639           </PORTMAPS>
3640         </BUSINTERFACE>
3641         <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
3642           <PORTMAPS>
3643             <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
3644             <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
3645             <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
3646             <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
3647             <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
3648             <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
3649             <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
3650           </PORTMAPS>
3651         </BUSINTERFACE>
3652         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
3653           <PORTMAPS>
3654             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
3655             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
3656             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
3657             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
3658             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
3659             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
3660             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
3661             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
3662             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
3663             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
3664             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
3665             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
3666             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
3667             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
3668             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
3669             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
3670             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
3671             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
3672             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
3673             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
3674             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
3675             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
3676             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
3677             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
3678             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
3679             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
3680             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
3681             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
3682             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
3683             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
3684             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
3685             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
3686             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
3687             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
3688             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
3689             <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
3690             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
3691             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
3692             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
3693             <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
3694           </PORTMAPS>
3695         </BUSINTERFACE>
3696         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3697           <PORTMAPS>
3698             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
3699             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
3700             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
3701             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
3702             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
3703             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
3704             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
3705             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
3706             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
3707             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
3708             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
3709             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
3710             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
3711             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
3712             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
3713             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
3714             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
3715             <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
3716             <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
3717           </PORTMAPS>
3718         </BUSINTERFACE>
3719       </BUSINTERFACES>
3720       <MEMORYMAP>
3721         <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
3722           <SLAVES>
3723             <SLAVE BUSINTERFACE="SLMB"/>
3724           </SLAVES>
3725         </MEMRANGE>
3726         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3727           <SLAVES>
3728             <SLAVE BUSINTERFACE="SPLB_CTRL"/>
3729           </SLAVES>
3730         </MEMRANGE>
3731         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3732           <SLAVES>
3733             <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
3734           </SLAVES>
3735         </MEMRANGE>
3736       </MEMORYMAP>
3737     </MODULE>
3738     <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
3739       <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
3740       <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
3741       <DOCUMENTATION>
3742         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
3743       </DOCUMENTATION>
3744       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3745       <PARAMETERS>
3746         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
3747           <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
3748         </PARAMETER>
3749         <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
3750           <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
3751         </PARAMETER>
3752         <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
3753           <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
3754         </PARAMETER>
3755         <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
3756           <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
3757         </PARAMETER>
3758         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
3759           <DESCRIPTION>Device Family</DESCRIPTION>
3760         </PARAMETER>
3761       </PARAMETERS>
3762       <PORTS>
3763         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3764         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3765         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3766         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
3767         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
3768         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3769         <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3770         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3771         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3772         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3773         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
3774         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
3775         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3776         <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3777       </PORTS>
3778       <BUSINTERFACES>
3779         <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
3780           <PORTMAPS>
3781             <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
3782             <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
3783             <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
3784             <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
3785             <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
3786             <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
3787             <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
3788           </PORTMAPS>
3789         </BUSINTERFACE>
3790         <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
3791           <PORTMAPS>
3792             <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
3793             <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
3794             <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
3795             <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
3796             <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
3797             <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
3798             <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
3799           </PORTMAPS>
3800         </BUSINTERFACE>
3801       </BUSINTERFACES>
3802     </MODULE>
3803     <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
3804       <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
3805       <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
3806       <DOCUMENTATION>
3807         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
3808       </DOCUMENTATION>
3809       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3810       <PARAMETERS>
3811         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
3812           <DESCRIPTION>Device Subfamily</DESCRIPTION>
3813         </PARAMETER>
3814         <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
3815           <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
3816         </PARAMETER>
3817         <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
3818           <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
3819         </PARAMETER>
3820         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
3821           <DESCRIPTION>External Reset Active High </DESCRIPTION>
3822         </PARAMETER>
3823         <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
3824           <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
3825         </PARAMETER>
3826         <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
3827           <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
3828         </PARAMETER>
3829         <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
3830           <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
3831         </PARAMETER>
3832         <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
3833           <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
3834         </PARAMETER>
3835         <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
3836           <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
3837         </PARAMETER>
3838         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
3839           <DESCRIPTION>Device Family</DESCRIPTION>
3840         </PARAMETER>
3841       </PARAMETERS>
3842       <PORTS>
3843         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
3844         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
3845         <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3846         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
3847         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
3848         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
3849         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
3850         <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
3851         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3852         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3853         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3854         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3855         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3856         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3857         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
3858         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
3859         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
3860         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
3861         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
3862         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
3863         <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
3864         <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
3865       </PORTS>
3866       <BUSINTERFACES>
3867         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
3868           <PORTMAPS>
3869             <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
3870             <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
3871             <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
3872             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
3873             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
3874             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
3875           </PORTMAPS>
3876         </BUSINTERFACE>
3877         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
3878           <PORTMAPS>
3879             <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
3880             <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
3881             <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
3882             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
3883             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
3884             <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
3885           </PORTMAPS>
3886         </BUSINTERFACE>
3887       </BUSINTERFACES>
3888       <IOINTERFACES>
3889         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
3890       </IOINTERFACES>
3891     </MODULE>
3892     <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
3893       <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
3894       <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
3895       <DOCUMENTATION>
3896         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
3897       </DOCUMENTATION>
3898       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3899       <PARAMETERS>
3900         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
3901           <DESCRIPTION>Family</DESCRIPTION>
3902         </PARAMETER>
3903         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
3904           <DESCRIPTION>Device</DESCRIPTION>
3905         </PARAMETER>
3906         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
3907           <DESCRIPTION>Package</DESCRIPTION>
3908         </PARAMETER>
3909         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
3910           <DESCRIPTION>Speed Grade</DESCRIPTION>
3911         </PARAMETER>
3912         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
3913           <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
3914         </PARAMETER>
3915         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000">
3916           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3917         </PARAMETER>
3918         <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
3919           <DESCRIPTION>Required Phase </DESCRIPTION>
3920         </PARAMETER>
3921         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
3922           <DESCRIPTION>Required Group</DESCRIPTION>
3923         </PARAMETER>
3924         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
3925           <DESCRIPTION>Buffered </DESCRIPTION>
3926         </PARAMETER>
3927         <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
3928           <DESCRIPTION>Variable Phase</DESCRIPTION>
3929         </PARAMETER>
3930         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000">
3931           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3932         </PARAMETER>
3933         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
3934           <DESCRIPTION>Required Phase</DESCRIPTION>
3935         </PARAMETER>
3936         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
3937           <DESCRIPTION>Required Group </DESCRIPTION>
3938         </PARAMETER>
3939         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
3940           <DESCRIPTION>Buffered</DESCRIPTION>
3941         </PARAMETER>
3942         <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
3943           <DESCRIPTION>Variable Phase</DESCRIPTION>
3944         </PARAMETER>
3945         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000">
3946           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3947         </PARAMETER>
3948         <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
3949           <DESCRIPTION>Required Phase</DESCRIPTION>
3950         </PARAMETER>
3951         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
3952           <DESCRIPTION>Required Group </DESCRIPTION>
3953         </PARAMETER>
3954         <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
3955           <DESCRIPTION>Buffered</DESCRIPTION>
3956         </PARAMETER>
3957         <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
3958           <DESCRIPTION>Varaible Phase</DESCRIPTION>
3959         </PARAMETER>
3960         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000">
3961           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3962         </PARAMETER>
3963         <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
3964           <DESCRIPTION>Required Phase</DESCRIPTION>
3965         </PARAMETER>
3966         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0">
3967           <DESCRIPTION>Required Group</DESCRIPTION>
3968         </PARAMETER>
3969         <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
3970           <DESCRIPTION>Buffered</DESCRIPTION>
3971         </PARAMETER>
3972         <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
3973           <DESCRIPTION>Variable Phase</DESCRIPTION>
3974         </PARAMETER>
3975         <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
3976           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3977         </PARAMETER>
3978         <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
3979           <DESCRIPTION>Required Phase</DESCRIPTION>
3980         </PARAMETER>
3981         <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
3982           <DESCRIPTION>Required Group </DESCRIPTION>
3983         </PARAMETER>
3984         <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
3985           <DESCRIPTION>Buffered</DESCRIPTION>
3986         </PARAMETER>
3987         <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
3988           <DESCRIPTION>Variable Phase</DESCRIPTION>
3989         </PARAMETER>
3990         <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
3991           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
3992         </PARAMETER>
3993         <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
3994           <DESCRIPTION>Required Phase</DESCRIPTION>
3995         </PARAMETER>
3996         <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
3997           <DESCRIPTION>Required Group</DESCRIPTION>
3998         </PARAMETER>
3999         <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4000           <DESCRIPTION>Buffered</DESCRIPTION>
4001         </PARAMETER>
4002         <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4003           <DESCRIPTION>Variable Phase</DESCRIPTION>
4004         </PARAMETER>
4005         <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
4006           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4007         </PARAMETER>
4008         <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
4009           <DESCRIPTION>Required Phase </DESCRIPTION>
4010         </PARAMETER>
4011         <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
4012           <DESCRIPTION>Required Group</DESCRIPTION>
4013         </PARAMETER>
4014         <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4015           <DESCRIPTION>Buffered</DESCRIPTION>
4016         </PARAMETER>
4017         <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4018           <DESCRIPTION>Variable Phase</DESCRIPTION>
4019         </PARAMETER>
4020         <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
4021           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4022         </PARAMETER>
4023         <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
4024           <DESCRIPTION>Required Phase</DESCRIPTION>
4025         </PARAMETER>
4026         <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
4027           <DESCRIPTION>Required Group</DESCRIPTION>
4028         </PARAMETER>
4029         <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4030           <DESCRIPTION>Buffered</DESCRIPTION>
4031         </PARAMETER>
4032         <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4033           <DESCRIPTION>Variable Phase</DESCRIPTION>
4034         </PARAMETER>
4035         <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
4036           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4037         </PARAMETER>
4038         <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
4039           <DESCRIPTION>Required Phase</DESCRIPTION>
4040         </PARAMETER>
4041         <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
4042           <DESCRIPTION>Required Group</DESCRIPTION>
4043         </PARAMETER>
4044         <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4045           <DESCRIPTION>Buffered</DESCRIPTION>
4046         </PARAMETER>
4047         <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4048           <DESCRIPTION>Variable Phase</DESCRIPTION>
4049         </PARAMETER>
4050         <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
4051           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4052         </PARAMETER>
4053         <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
4054           <DESCRIPTION>Required Phase</DESCRIPTION>
4055         </PARAMETER>
4056         <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
4057           <DESCRIPTION>Required Group</DESCRIPTION>
4058         </PARAMETER>
4059         <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4060           <DESCRIPTION>Buffered</DESCRIPTION>
4061         </PARAMETER>
4062         <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4063           <DESCRIPTION> Varaible Phase</DESCRIPTION>
4064         </PARAMETER>
4065         <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
4066           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4067         </PARAMETER>
4068         <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
4069           <DESCRIPTION>Required Phase</DESCRIPTION>
4070         </PARAMETER>
4071         <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
4072           <DESCRIPTION>Required Group</DESCRIPTION>
4073         </PARAMETER>
4074         <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4075           <DESCRIPTION>Buffered</DESCRIPTION>
4076         </PARAMETER>
4077         <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4078           <DESCRIPTION>Variable Phase</DESCRIPTION>
4079         </PARAMETER>
4080         <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
4081           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4082         </PARAMETER>
4083         <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
4084           <DESCRIPTION>Required Phase</DESCRIPTION>
4085         </PARAMETER>
4086         <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
4087           <DESCRIPTION>Required Group</DESCRIPTION>
4088         </PARAMETER>
4089         <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4090           <DESCRIPTION>Buffered</DESCRIPTION>
4091         </PARAMETER>
4092         <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4093           <DESCRIPTION>Variable Phase</DESCRIPTION>
4094         </PARAMETER>
4095         <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
4096           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4097         </PARAMETER>
4098         <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
4099           <DESCRIPTION>Required Phase</DESCRIPTION>
4100         </PARAMETER>
4101         <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
4102           <DESCRIPTION>Required Group</DESCRIPTION>
4103         </PARAMETER>
4104         <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4105           <DESCRIPTION>Buffered</DESCRIPTION>
4106         </PARAMETER>
4107         <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4108           <DESCRIPTION> Variable Phase</DESCRIPTION>
4109         </PARAMETER>
4110         <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
4111           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4112         </PARAMETER>
4113         <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
4114           <DESCRIPTION>Required Phase</DESCRIPTION>
4115         </PARAMETER>
4116         <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
4117           <DESCRIPTION>Required Group</DESCRIPTION>
4118         </PARAMETER>
4119         <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4120           <DESCRIPTION>Buffered</DESCRIPTION>
4121         </PARAMETER>
4122         <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4123           <DESCRIPTION>Variable Phase</DESCRIPTION>
4124         </PARAMETER>
4125         <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
4126           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4127         </PARAMETER>
4128         <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
4129           <DESCRIPTION>Required Phase</DESCRIPTION>
4130         </PARAMETER>
4131         <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
4132           <DESCRIPTION>Required Group</DESCRIPTION>
4133         </PARAMETER>
4134         <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4135           <DESCRIPTION>Buffered</DESCRIPTION>
4136         </PARAMETER>
4137         <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4138           <DESCRIPTION>Variable Phase</DESCRIPTION>
4139         </PARAMETER>
4140         <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
4141           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4142         </PARAMETER>
4143         <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
4144           <DESCRIPTION>Required Phase</DESCRIPTION>
4145         </PARAMETER>
4146         <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
4147           <DESCRIPTION>Required Group</DESCRIPTION>
4148         </PARAMETER>
4149         <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4150           <DESCRIPTION>Buffered</DESCRIPTION>
4151         </PARAMETER>
4152         <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
4153           <DESCRIPTION> Variable Phase</DESCRIPTION>
4154         </PARAMETER>
4155         <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
4156           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4157         </PARAMETER>
4158         <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
4159           <DESCRIPTION>Clock Deskew</DESCRIPTION>
4160         </PARAMETER>
4161         <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
4162           <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
4163         </PARAMETER>
4164         <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
4165           <DESCRIPTION>Required Phase</DESCRIPTION>
4166         </PARAMETER>
4167         <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
4168           <DESCRIPTION>Required Group</DESCRIPTION>
4169         </PARAMETER>
4170         <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
4171           <DESCRIPTION>Buffered</DESCRIPTION>
4172         </PARAMETER>
4173         <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
4174           <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
4175         </PARAMETER>
4176         <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
4177         <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
4178           <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
4179         </PARAMETER>
4180         <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
4181       </PARAMETERS>
4182       <PORTS>
4183         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
4184         <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
4185         <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
4186         <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4187         <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
4188         <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
4189         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
4190         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
4191         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
4192         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
4193         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
4194         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
4195         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
4196         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
4197         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
4198         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
4199         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
4200         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
4201         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
4202         <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
4203         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
4204         <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
4205         <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
4206         <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
4207         <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
4208       </PORTS>
4209       <BUSINTERFACES/>
4210     </MODULE>
4211     <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
4212       <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
4213       <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
4214       <DOCUMENTATION>
4215         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
4216       </DOCUMENTATION>
4217       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4218       <PARAMETERS>
4219         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
4220           <DESCRIPTION>Device Family</DESCRIPTION>
4221         </PARAMETER>
4222         <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
4223           <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
4224         </PARAMETER>
4225         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
4226           <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
4227         </PARAMETER>
4228         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000">
4229           <DESCRIPTION>Base Address</DESCRIPTION>
4230         </PARAMETER>
4231         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff">
4232           <DESCRIPTION>High Address</DESCRIPTION>
4233         </PARAMETER>
4234         <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
4235           <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
4236         </PARAMETER>
4237         <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
4238           <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
4239         </PARAMETER>
4240         <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
4241           <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
4242         </PARAMETER>
4243         <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
4244           <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
4245         </PARAMETER>
4246         <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
4247           <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
4248         </PARAMETER>
4249         <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
4250           <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
4251         </PARAMETER>
4252         <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
4253           <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
4254         </PARAMETER>
4255         <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
4256           <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
4257         </PARAMETER>
4258         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
4259           <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
4260         </PARAMETER>
4261         <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
4262           <DESCRIPTION>AXI Address Width</DESCRIPTION>
4263         </PARAMETER>
4264         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
4265           <DESCRIPTION>AXI Data Width</DESCRIPTION>
4266         </PARAMETER>
4267         <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
4268           <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
4269         </PARAMETER>
4270         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4271         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4272         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4273         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4274         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4275       </PARAMETERS>
4276       <PORTS>
4277         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4278         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
4279         <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
4280         <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
4281         <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
4282         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4283         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4284         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4285         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4286         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4287         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
4288         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4289         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4290         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4291         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4292         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4293         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4294         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4295         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4296         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4297         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4298         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4299         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4300         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
4301         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
4302         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
4303         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
4304         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
4305         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
4306         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
4307         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
4308         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
4309         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
4310         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
4311         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
4312         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
4313         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
4314         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
4315         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
4316         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
4317         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
4318         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
4319         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
4320         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
4321         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
4322         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
4323         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
4324         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
4325         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
4326         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
4327         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
4328         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
4329         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
4330         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
4331         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
4332         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
4333         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
4334         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
4335         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
4336         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
4337         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
4338         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
4339         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
4340         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
4341         <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
4342         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
4343         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
4344         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
4345         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
4346         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
4347         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
4348         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
4349         <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
4350         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
4351         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
4352         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
4353         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4354         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
4355         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
4356         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
4357         <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
4358         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
4359         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
4360         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
4361         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4362         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
4363         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
4364         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
4365         <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
4366         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
4367         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
4368         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
4369         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4370         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
4371         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
4372         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
4373         <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
4374         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
4375         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
4376         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
4377         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4378         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
4379         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
4380         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
4381         <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
4382         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
4383         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
4384         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
4385         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4386         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
4387         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
4388         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
4389         <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
4390         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
4391         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
4392         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
4393         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4394         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
4395         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
4396         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
4397         <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
4398         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
4399         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
4400         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
4401         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
4402         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
4403         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
4404         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
4405         <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
4406         <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
4407         <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
4408         <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
4409         <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
4410         <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
4411         <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
4412         <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
4413         <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
4414         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
4415         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
4416         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
4417         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
4418         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
4419         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
4420         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
4421         <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
4422       </PORTS>
4423       <BUSINTERFACES>
4424         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4425           <PORTMAPS>
4426             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4427             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4428             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4429             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4430             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4431             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4432             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4433             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4434             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4435             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4436             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4437             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4438             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4439             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4440             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4441             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4442             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4443             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4444             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4445           </PORTMAPS>
4446         </BUSINTERFACE>
4447         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
4448           <PORTMAPS>
4449             <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
4450             <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
4451             <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
4452             <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
4453             <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
4454             <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
4455             <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
4456             <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
4457             <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
4458             <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
4459             <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
4460             <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
4461             <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
4462             <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
4463             <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
4464             <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
4465             <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
4466             <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
4467             <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
4468             <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
4469             <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
4470             <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
4471             <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
4472             <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
4473             <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
4474             <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
4475             <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
4476             <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
4477             <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
4478             <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
4479             <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
4480             <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
4481             <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
4482             <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
4483             <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
4484             <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
4485             <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
4486             <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
4487             <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
4488             <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
4489             <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
4490             <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
4491           </PORTMAPS>
4492         </BUSINTERFACE>
4493         <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
4494           <PORTMAPS>
4495             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
4496             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
4497             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
4498             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
4499             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
4500             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
4501             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
4502             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
4503           </PORTMAPS>
4504         </BUSINTERFACE>
4505         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
4506           <PORTMAPS>
4507             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
4508             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
4509             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
4510             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
4511             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
4512             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
4513             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
4514             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
4515           </PORTMAPS>
4516         </BUSINTERFACE>
4517         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
4518           <PORTMAPS>
4519             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
4520             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
4521             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
4522             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
4523             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
4524             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
4525             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
4526             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
4527           </PORTMAPS>
4528         </BUSINTERFACE>
4529         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
4530           <PORTMAPS>
4531             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
4532             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
4533             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
4534             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
4535             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
4536             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
4537             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
4538             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
4539           </PORTMAPS>
4540         </BUSINTERFACE>
4541         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
4542           <PORTMAPS>
4543             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
4544             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
4545             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
4546             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
4547             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
4548             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
4549             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
4550             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
4551           </PORTMAPS>
4552         </BUSINTERFACE>
4553         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
4554           <PORTMAPS>
4555             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
4556             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
4557             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
4558             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
4559             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
4560             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
4561             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
4562             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
4563           </PORTMAPS>
4564         </BUSINTERFACE>
4565         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
4566           <PORTMAPS>
4567             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
4568             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
4569             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
4570             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
4571             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
4572             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
4573             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
4574             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
4575           </PORTMAPS>
4576         </BUSINTERFACE>
4577         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
4578           <PORTMAPS>
4579             <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
4580             <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
4581             <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
4582             <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
4583             <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
4584             <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
4585             <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
4586             <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
4587           </PORTMAPS>
4588         </BUSINTERFACE>
4589         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
4590           <PORTMAPS>
4591             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
4592             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
4593             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
4594             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
4595             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
4596             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
4597             <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
4598             <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
4599           </PORTMAPS>
4600         </BUSINTERFACE>
4601       </BUSINTERFACES>
4602       <MEMORYMAP>
4603         <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
4604           <SLAVES>
4605             <SLAVE BUSINTERFACE="SPLB"/>
4606             <SLAVE BUSINTERFACE="S_AXI"/>
4607           </SLAVES>
4608         </MEMRANGE>
4609       </MEMORYMAP>
4610     </MODULE>
4611     <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
4612       <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
4613       <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
4614       <DOCUMENTATION>
4615         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
4616       </DOCUMENTATION>
4617       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4618       <PARAMETERS>
4619         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
4620           <DESCRIPTION>Device Family</DESCRIPTION>
4621         </PARAMETER>
4622         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
4623           <DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
4624         </PARAMETER>
4625         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000">
4626           <DESCRIPTION>AXI Base Address </DESCRIPTION>
4627         </PARAMETER>
4628         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff">
4629           <DESCRIPTION>AXI High Address</DESCRIPTION>
4630         </PARAMETER>
4631         <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
4632           <DESCRIPTION>AXI Address Width</DESCRIPTION>
4633         </PARAMETER>
4634         <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
4635           <DESCRIPTION>AXI Data Width</DESCRIPTION>
4636         </PARAMETER>
4637         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200">
4638           <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
4639           <DESCRIPTION>Baud Rate</DESCRIPTION>
4640         </PARAMETER>
4641         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
4642           <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
4643           <DESCRIPTION>Data Bits</DESCRIPTION>
4644         </PARAMETER>
4645         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
4646           <DESCRIPTION>Use Parity </DESCRIPTION>
4647         </PARAMETER>
4648         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1">
4649           <DESCRIPTION>Parity Type </DESCRIPTION>
4650         </PARAMETER>
4651         <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
4652           <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
4653         </PARAMETER>
4654         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4655         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4656         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4657         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4658         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4659       </PARAMETERS>
4660       <PORTS>
4661         <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
4662           <DESCRIPTION>Serial Data Out</DESCRIPTION>
4663         </PORT>
4664         <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
4665           <DESCRIPTION>Serial Data In</DESCRIPTION>
4666         </PORT>
4667         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4668         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
4669         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4670         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4671         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4672         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4673         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4674         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4675         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4676         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4677         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4678         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4679         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4680         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4681         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4682         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4683         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4684         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4685         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4686         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4687       </PORTS>
4688       <BUSINTERFACES>
4689         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4690           <PORTMAPS>
4691             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4692             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4693             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4694             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4695             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4696             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4697             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4698             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4699             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4700             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4701             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4702             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4703             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4704             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4705             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4706             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4707             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4708             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4709             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4710           </PORTMAPS>
4711         </BUSINTERFACE>
4712       </BUSINTERFACES>
4713       <IOINTERFACES>
4714         <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
4715           <PORTMAPS>
4716             <PORTMAP DIR="O" PHYSICAL="TX"/>
4717             <PORTMAP DIR="I" PHYSICAL="RX"/>
4718           </PORTMAPS>
4719         </IOINTERFACE>
4720       </IOINTERFACES>
4721       <MEMORYMAP>
4722         <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
4723           <SLAVES>
4724             <SLAVE BUSINTERFACE="S_AXI"/>
4725           </SLAVES>
4726         </MEMRANGE>
4727       </MEMORYMAP>
4728       <INTERRUPTINFO TYPE="SOURCE">
4729         <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
4730       </INTERRUPTINFO>
4731     </MODULE>
4732     <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
4733       <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
4734       <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
4735       <DOCUMENTATION>
4736         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
4737       </DOCUMENTATION>
4738       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4739       <PARAMETERS>
4740         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
4741           <DESCRIPTION>Device Family</DESCRIPTION>
4742         </PARAMETER>
4743         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000">
4744           <DESCRIPTION>AXI Base Address </DESCRIPTION>
4745         </PARAMETER>
4746         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff">
4747           <DESCRIPTION>AXI High Address</DESCRIPTION>
4748         </PARAMETER>
4749         <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
4750           <DESCRIPTION>AXI Address Width</DESCRIPTION>
4751         </PARAMETER>
4752         <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
4753           <DESCRIPTION>AXI Data Width</DESCRIPTION>
4754         </PARAMETER>
4755         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
4756           <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
4757           <DESCRIPTION>GPIO Data Width</DESCRIPTION>
4758         </PARAMETER>
4759         <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
4760           <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
4761         </PARAMETER>
4762         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
4763           <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
4764         </PARAMETER>
4765         <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
4766           <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
4767         </PARAMETER>
4768         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
4769           <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
4770         </PARAMETER>
4771         <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
4772           <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
4773         </PARAMETER>
4774         <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
4775           <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
4776         </PARAMETER>
4777         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
4778           <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
4779         </PARAMETER>
4780         <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
4781           <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
4782         </PARAMETER>
4783         <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
4784           <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
4785         </PARAMETER>
4786         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
4787           <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
4788         </PARAMETER>
4789         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4790         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4791         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4792         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4793         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4794       </PARAMETERS>
4795       <PORTS>
4796         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4797         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4798         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4799         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4800         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4801         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4802         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4803         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4804         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4805         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4806         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4807         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4808         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4809         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4810         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4811         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4812         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4813         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4814         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4815         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4816         <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
4817         <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4818         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4819         <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4820         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4821         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4822         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
4823           <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
4824         </PORT>
4825         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
4826           <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
4827         </PORT>
4828       </PORTS>
4829       <BUSINTERFACES>
4830         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4831           <PORTMAPS>
4832             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4833             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4834             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4835             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4836             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4837             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4838             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4839             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4840             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4841             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4842             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4843             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4844             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4845             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4846             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4847             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4848             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4849             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4850             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4851           </PORTMAPS>
4852         </BUSINTERFACE>
4853       </BUSINTERFACES>
4854       <IOINTERFACES>
4855         <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
4856           <PORTMAPS>
4857             <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
4858             <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
4859             <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
4860             <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
4861             <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
4862             <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
4863             <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
4864             <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
4865           </PORTMAPS>
4866         </IOINTERFACE>
4867       </IOINTERFACES>
4868       <MEMORYMAP>
4869         <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
4870           <SLAVES>
4871             <SLAVE BUSINTERFACE="S_AXI"/>
4872           </SLAVES>
4873         </MEMRANGE>
4874       </MEMORYMAP>
4875     </MODULE>
4876     <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
4877       <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
4878       <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
4879       <DOCUMENTATION>
4880         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
4881       </DOCUMENTATION>
4882       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4883       <PARAMETERS>
4884         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
4885           <DESCRIPTION>Device Family</DESCRIPTION>
4886         </PARAMETER>
4887         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
4888           <DESCRIPTION>AXI Base Address </DESCRIPTION>
4889         </PARAMETER>
4890         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff">
4891           <DESCRIPTION>AXI High Address</DESCRIPTION>
4892         </PARAMETER>
4893         <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
4894           <DESCRIPTION>AXI Address Width</DESCRIPTION>
4895         </PARAMETER>
4896         <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
4897           <DESCRIPTION>AXI Data Width</DESCRIPTION>
4898         </PARAMETER>
4899         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
4900           <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
4901           <DESCRIPTION>GPIO Data Width</DESCRIPTION>
4902         </PARAMETER>
4903         <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
4904           <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
4905         </PARAMETER>
4906         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
4907           <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
4908         </PARAMETER>
4909         <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
4910           <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
4911         </PARAMETER>
4912         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1">
4913           <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
4914         </PARAMETER>
4915         <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
4916           <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
4917         </PARAMETER>
4918         <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
4919           <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
4920         </PARAMETER>
4921         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
4922           <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
4923         </PARAMETER>
4924         <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
4925           <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
4926         </PARAMETER>
4927         <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
4928           <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
4929         </PARAMETER>
4930         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
4931           <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
4932         </PARAMETER>
4933         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4934         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4935         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4936         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4937         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4938       </PARAMETERS>
4939       <PORTS>
4940         <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4941         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4942         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
4943         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4944         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4945         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4946         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4947         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4948         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4949         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4950         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4951         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4952         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4953         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4954         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4955         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4956         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4957         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4958         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4959         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4960         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4961         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4962         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
4963         <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4964         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4965         <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4966         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
4967           <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
4968         </PORT>
4969         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
4970           <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
4971         </PORT>
4972       </PORTS>
4973       <BUSINTERFACES>
4974         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4975           <PORTMAPS>
4976             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4977             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4978             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4979             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4980             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4981             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4982             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4983             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4984             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4985             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4986             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4987             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4988             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4989             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4990             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4991             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4992             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4993             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4994             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4995           </PORTMAPS>
4996         </BUSINTERFACE>
4997       </BUSINTERFACES>
4998       <IOINTERFACES>
4999         <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
5000           <PORTMAPS>
5001             <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
5002             <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
5003             <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
5004             <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
5005             <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
5006             <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
5007             <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
5008             <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
5009           </PORTMAPS>
5010         </IOINTERFACE>
5011       </IOINTERFACES>
5012       <MEMORYMAP>
5013         <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
5014           <SLAVES>
5015             <SLAVE BUSINTERFACE="S_AXI"/>
5016           </SLAVES>
5017         </MEMRANGE>
5018       </MEMORYMAP>
5019       <INTERRUPTINFO TYPE="SOURCE">
5020         <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
5021       </INTERRUPTINFO>
5022     </MODULE>
5023     <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
5024       <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
5025       <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
5026       <DOCUMENTATION>
5027         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
5028       </DOCUMENTATION>
5029       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
5030       <PARAMETERS>
5031         <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
5032         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
5033         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
5034         <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
5035         <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
5036         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/>
5037         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/>
5038         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
5039         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
5040         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
5041         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
5042         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
5043         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
5044         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
5045         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
5046         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
5047         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
5048         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
5049         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
5050         <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
5051         <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
5052         <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
5053         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
5054         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
5055         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
5056         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
5057         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
5058         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
5059         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
5060         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
5061         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
5062         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
5063         <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
5064         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
5065         <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
5066         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="3333"/>
5067         <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
5068         <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
5069         <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
5070         <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
5071         <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
5072         <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
5073         <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
5074         <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
5075         <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
5076         <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
5077         <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
5078         <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
5079         <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
5080         <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
5081         <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
5082         <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
5083         <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
5084         <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
5085         <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
5086         <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
5087         <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
5088         <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
5089         <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
5090         <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
5091         <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
5092         <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
5093         <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
5094         <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
5095         <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
5096         <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
5097         <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
5098         <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
5099         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
5100         <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5101         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
5102         <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5103         <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5104         <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
5105         <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
5106         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
5107         <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
5108         <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5109         <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5110         <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5111         <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5112         <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5113         <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
5114         <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5115         <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
5116         <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5117         <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5118         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
5119         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
5120         <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
5121         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
5122         <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5123         <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5124         <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5125         <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5126         <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5127         <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
5128         <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5129         <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
5130         <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5131         <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5132         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
5133         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
5134         <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
5135         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
5136         <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5137         <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5138         <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5139         <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5140         <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5141         <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
5142         <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5143         <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
5144         <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5145         <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5146         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
5147         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
5148         <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
5149         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
5150         <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5151         <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5152         <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5153         <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5154         <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5155         <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
5156         <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5157         <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
5158         <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5159         <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5160         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
5161         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
5162         <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
5163         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
5164         <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5165         <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5166         <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5167         <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5168         <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5169         <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
5170         <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
5171         <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
5172         <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
5173         <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
5174         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
5175         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
5176         <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
5177         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
5178         <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
5179         <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
5180         <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
5181         <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5182         <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
5183         <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
5184         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
5185         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC &amp; microblaze_0.M_AXI_IC"/>
5186         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
5187         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
5188         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
5189         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
5190         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
5191       </PARAMETERS>
5192       <PORTS>
5193         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
5194         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
5195         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
5196         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
5197         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
5198         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
5199         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
5200         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
5201         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
5202         <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
5203         <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
5204         <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
5205         <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
5206         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
5207         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
5208         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
5209         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
5210         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
5211         <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
5212         <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
5213         <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
5214         <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
5215         <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
5216         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
5217         <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
5218         <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
5219         <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
5220         <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
5221         <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
5222         <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
5223         <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
5224         <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
5225         <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
5226         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
5227         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
5228         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
5229         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
5230         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
5231         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
5232         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
5233         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
5234         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
5235         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
5236         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
5237         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
5238         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
5239         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
5240         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
5241         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
5242         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
5243         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
5244         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
5245         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
5246         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
5247         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
5248         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
5249         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
5250         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="axi4_0_M_arsize" VECFORMULA="[2:0]"/>
5251         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="axi4_0_M_arburst" VECFORMULA="[1:0]"/>
5252         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="axi4_0_M_arlock" VECFORMULA="[0:0]"/>
5253         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="axi4_0_M_arcache" VECFORMULA="[3:0]"/>
5254         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="axi4_0_M_arprot" VECFORMULA="[2:0]"/>
5255         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="axi4_0_M_arqos" VECFORMULA="[3:0]"/>
5256         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="axi4_0_M_arvalid"/>
5257         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="axi4_0_M_arready"/>
5258         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="axi4_0_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
5259         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="axi4_0_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
5260         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="axi4_0_M_rresp" VECFORMULA="[1:0]"/>
5261         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="axi4_0_M_rlast"/>
5262         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="axi4_0_M_rvalid"/>
5263         <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="axi4_0_M_rready"/>
5264         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
5265         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
5266         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="73" MSB="3" NAME="s1_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
5267         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
5268         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5269         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5270         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5271         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
5272         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5273         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5274         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5275         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="__NOC__"/>
5276         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="__NOC__"/>
5277         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
5278         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
5279         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="__NOC__"/>
5280         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="__NOC__"/>
5281         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="__NOC__"/>
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5284         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="__NOC__"/>
5285         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="__NOC__"/>
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5288         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5289         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
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5291         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
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5293         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5294         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5295         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="__NOC__"/>
5296         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="__NOC__"/>
5297         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="s1_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
5298         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
5299         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5300         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="__NOC__"/>
5301         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="__NOC__"/>
5302         <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="__NOC__"/>
5303         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
5304         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
5305         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="112" MSB="3" NAME="s2_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
5306         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
5307         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5308         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5309         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5310         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
5311         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5312         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5313         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5314         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="__NOC__"/>
5315         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="__NOC__"/>
5316         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
5317         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
5318         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="__NOC__"/>
5319         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="__NOC__"/>
5320         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="__NOC__"/>
5321         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="128" MSB="3" NAME="s2_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
5322         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5323         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="__NOC__"/>
5324         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="__NOC__"/>
5325         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="132" MSB="3" NAME="s2_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
5326         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
5327         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5328         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5329         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5330         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
5331         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5332         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5333         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5334         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="__NOC__"/>
5335         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="__NOC__"/>
5336         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="143" MSB="3" NAME="s2_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
5337         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
5338         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5339         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="__NOC__"/>
5340         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="__NOC__"/>
5341         <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="__NOC__"/>
5342         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
5343         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
5344         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
5345         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
5346         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5347         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5348         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5349         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
5350         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5351         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
5352         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
5353         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
5354         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
5355         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
5356         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
5357         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
5358         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
5359         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
5360         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
5361         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5362         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
5363         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
5364         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
5365         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
5366         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
5367         <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
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5392         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
5393         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
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5396         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
5397         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
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5412         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
5413         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
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5418         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
5419         <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
5420         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
5421         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
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5431         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
5432         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
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5434         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
5435         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
5436         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
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5440         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
5441         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
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5443         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
5444         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
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5447         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
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5451         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
5452         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
5453         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
5454         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
5455         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
5456         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
5457         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
5458         <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
5459       </PORTS>
5460       <BUSINTERFACES>
5461         <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5462           <PORTMAPS>
5463             <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
5464             <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
5465             <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
5466             <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
5467             <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
5468             <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
5469             <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
5470             <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
5471             <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
5472             <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
5473             <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
5474             <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
5475             <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
5476             <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
5477             <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
5478             <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
5479             <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
5480             <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
5481             <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
5482             <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
5483             <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
5484             <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
5485             <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
5486             <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
5487             <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
5488             <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
5489             <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
5490             <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
5491             <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
5492             <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
5493             <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
5494             <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
5495             <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
5496             <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
5497             <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
5498             <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
5499             <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
5500             <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
5501             <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
5502           </PORTMAPS>
5503           <MASTERS>
5504             <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
5505             <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
5506           </MASTERS>
5507         </BUSINTERFACE>
5508         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5509           <PORTMAPS>
5510             <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
5511             <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
5512             <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
5513             <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
5514             <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
5515             <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
5516             <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
5517             <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
5518             <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
5519             <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
5520             <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
5521             <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
5522             <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
5523             <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
5524             <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
5525             <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
5526             <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
5527             <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
5528             <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
5529             <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
5530             <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
5531             <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
5532             <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
5533             <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
5534             <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
5535             <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
5536             <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
5537             <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
5538             <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
5539             <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
5540             <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
5541             <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
5542             <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
5543             <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
5544             <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
5545             <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
5546             <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
5547             <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
5548             <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
5549           </PORTMAPS>
5550         </BUSINTERFACE>
5551         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5552           <PORTMAPS>
5553             <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
5554             <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
5555             <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
5556             <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
5557             <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
5558             <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
5559             <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
5560             <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
5561             <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
5562             <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
5563             <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
5564             <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
5565             <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
5566             <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
5567             <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
5568             <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
5569             <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
5570             <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
5571             <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
5572             <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
5573             <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
5574             <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
5575             <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
5576             <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
5577             <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
5578             <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
5579             <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
5580             <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
5581             <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
5582             <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
5583             <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
5584             <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
5585             <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
5586             <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
5587             <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
5588             <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
5589             <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
5590             <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
5591             <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
5592           </PORTMAPS>
5593         </BUSINTERFACE>
5594         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5595           <PORTMAPS>
5596             <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
5597             <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
5598             <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
5599             <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
5600             <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
5601             <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
5602             <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
5603             <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
5604             <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
5605             <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
5606             <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
5607             <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
5608             <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
5609             <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
5610             <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
5611             <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
5612             <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
5613             <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
5614             <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
5615             <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
5616             <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
5617             <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
5618             <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
5619             <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
5620             <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
5621             <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
5622             <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
5623             <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
5624             <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
5625             <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
5626             <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
5627             <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
5628             <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
5629             <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
5630             <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
5631             <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
5632             <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
5633             <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
5634             <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
5635           </PORTMAPS>
5636         </BUSINTERFACE>
5637         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5638           <PORTMAPS>
5639             <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
5640             <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
5641             <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
5642             <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
5643             <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
5644             <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
5645             <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
5646             <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
5647             <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
5648             <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
5649             <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
5650             <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
5651             <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
5652             <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
5653             <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
5654             <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
5655             <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
5656             <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
5657             <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
5658             <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
5659             <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
5660             <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
5661             <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
5662             <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
5663             <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
5664             <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
5665             <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
5666             <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
5667             <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
5668             <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
5669             <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
5670             <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
5671             <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
5672             <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
5673             <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
5674             <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
5675             <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
5676             <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
5677             <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
5678           </PORTMAPS>
5679         </BUSINTERFACE>
5680         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
5681           <PORTMAPS>
5682             <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
5683             <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
5684             <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
5685             <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
5686             <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
5687             <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
5688             <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
5689             <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
5690             <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
5691             <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
5692             <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
5693             <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
5694             <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
5695             <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
5696             <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
5697             <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
5698             <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
5699             <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
5700             <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
5701             <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
5702             <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
5703             <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
5704             <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
5705             <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
5706             <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
5707             <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
5708             <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
5709             <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
5710             <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
5711             <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
5712             <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
5713             <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
5714             <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
5715             <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
5716             <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
5717             <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
5718             <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
5719             <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
5720             <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
5721           </PORTMAPS>
5722         </BUSINTERFACE>
5723       </BUSINTERFACES>
5724       <IOINTERFACES>
5725         <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
5726           <PORTMAPS>
5727             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
5728             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
5729             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
5730             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
5731             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
5732             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
5733             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
5734             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
5735             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
5736             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
5737             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
5738             <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
5739             <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
5740             <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
5741             <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
5742             <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
5743             <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
5744             <PORTMAP DIR="IO" PHYSICAL="rzq"/>
5745             <PORTMAP DIR="IO" PHYSICAL="zio"/>
5746           </PORTMAPS>
5747         </IOINTERFACE>
5748       </IOINTERFACES>
5749       <MEMORYMAP>
5750         <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
5751           <SLAVES>
5752             <SLAVE BUSINTERFACE="S0_AXI"/>
5753           </SLAVES>
5754         </MEMRANGE>
5755         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
5756           <SLAVES>
5757             <SLAVE BUSINTERFACE="S1_AXI"/>
5758           </SLAVES>
5759         </MEMRANGE>
5760         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
5761           <SLAVES>
5762             <SLAVE BUSINTERFACE="S2_AXI"/>
5763           </SLAVES>
5764         </MEMRANGE>
5765         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
5766           <SLAVES>
5767             <SLAVE BUSINTERFACE="S3_AXI"/>
5768           </SLAVES>
5769         </MEMRANGE>
5770         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
5771           <SLAVES>
5772             <SLAVE BUSINTERFACE="S4_AXI"/>
5773           </SLAVES>
5774         </MEMRANGE>
5775         <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
5776           <SLAVES>
5777             <SLAVE BUSINTERFACE="S5_AXI"/>
5778           </SLAVES>
5779         </MEMRANGE>
5780       </MEMORYMAP>
5781     </MODULE>
5782     <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
5783       <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
5784       <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
5785       <DOCUMENTATION>
5786         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
5787       </DOCUMENTATION>
5788       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
5789       <PARAMETERS>
5790         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE">
5791           <DESCRIPTION>AXI protocol selection </DESCRIPTION>
5792         </PARAMETER>
5793         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
5794           <DESCRIPTION>Device Family</DESCRIPTION>
5795         </PARAMETER>
5796         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000">
5797           <DESCRIPTION>Ethernetlite Base Address </DESCRIPTION>
5798         </PARAMETER>
5799         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff">
5800           <DESCRIPTION>Ethernetlite High Address </DESCRIPTION>
5801         </PARAMETER>
5802         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000">
5803           <DESCRIPTION>AXI System Clock Period </DESCRIPTION>
5804         </PARAMETER>
5805         <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
5806           <DESCRIPTION>AXI Interface Addresses Width </DESCRIPTION>
5807         </PARAMETER>
5808         <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
5809           <DESCRIPTION>AXI Interface Data Width </DESCRIPTION>
5810         </PARAMETER>
5811         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
5812           <DESCRIPTION>Width of ID Bus on AXI4 </DESCRIPTION>
5813         </PARAMETER>
5814         <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1">
5815           <DESCRIPTION>Include MII Management Module</DESCRIPTION>
5816         </PARAMETER>
5817         <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0">
5818           <DESCRIPTION>Include Global Buffers for PHY clocks</DESCRIPTION>
5819         </PARAMETER>
5820         <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0">
5821           <DESCRIPTION>Include Internal Loopback</DESCRIPTION>
5822         </PARAMETER>
5823         <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1">
5824           <DESCRIPTION>Duplex Mode </DESCRIPTION>
5825         </PARAMETER>
5826         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="1">
5827           <DESCRIPTION>Include Second Transmitter Buffer </DESCRIPTION>
5828         </PARAMETER>
5829         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="1">
5830           <DESCRIPTION>Include Second Receiver Buffer </DESCRIPTION>
5831         </PARAMETER>
5832         <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1">
5833           <DESCRIPTION>Include PHY I/O Constraints </DESCRIPTION>
5834         </PARAMETER>
5835         <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
5836           <DESCRIPTION>Interconnect write acceptance </DESCRIPTION>
5837         </PARAMETER>
5838         <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
5839           <DESCRIPTION>Interconnect read acceptance </DESCRIPTION>
5840         </PARAMETER>
5841         <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
5842           <DESCRIPTION>Support Narrow Burst on AXI4 </DESCRIPTION>
5843         </PARAMETER>
5844         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
5845         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
5846         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
5847         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
5848         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
5849       </PARAMETERS>
5850       <PORTS>
5851         <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
5852           <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
5853         </PORT>
5854         <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
5855           <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
5856         </PORT>
5857         <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
5858           <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
5859         </PORT>
5860         <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
5861           <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
5862         </PORT>
5863         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
5864           <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
5865         </PORT>
5866         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
5867           <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
5868         </PORT>
5869         <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
5870           <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
5871         </PORT>
5872         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
5873           <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
5874         </PORT>
5875         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
5876           <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
5877         </PORT>
5878         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
5879           <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
5880         </PORT>
5881         <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
5882           <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
5883         </PORT>
5884         <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
5885           <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
5886         </PORT>
5887         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
5888         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
5889         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
5890         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
5891         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
5892         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
5893         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
5894         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
5895         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
5896         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
5897         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
5898         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
5899         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
5900         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
5901         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
5902         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
5903         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
5904         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
5905         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
5906         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
5907         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
5908         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
5909         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
5910         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
5911         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
5912         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
5913         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
5914         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
5915         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
5916         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
5917         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
5918         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
5919         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
5920         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
5921         <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
5922         <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
5923         <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
5924       </PORTS>
5925       <BUSINTERFACES>
5926         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
5927           <PORTMAPS>
5928             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
5929             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
5930             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
5931             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
5932             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
5933             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
5934             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
5935             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
5936             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
5937             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
5938             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
5939             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
5940             <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
5941             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
5942             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
5943             <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
5944             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
5945             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
5946             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
5947             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
5948             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
5949             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
5950             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
5951             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
5952             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
5953             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
5954             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
5955             <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
5956             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
5957             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
5958             <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
5959             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
5960             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
5961           </PORTMAPS>
5962         </BUSINTERFACE>
5963       </BUSINTERFACES>
5964       <IOINTERFACES>
5965         <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
5966           <PORTMAPS>
5967             <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
5968             <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
5969             <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
5970             <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
5971             <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
5972             <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
5973             <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
5974             <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
5975             <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
5976             <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
5977             <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
5978             <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
5979             <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
5980             <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
5981             <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
5982           </PORTMAPS>
5983         </IOINTERFACE>
5984       </IOINTERFACES>
5985       <MEMORYMAP>
5986         <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
5987           <SLAVES>
5988             <SLAVE BUSINTERFACE="S_AXI"/>
5989           </SLAVES>
5990         </MEMRANGE>
5991       </MEMORYMAP>
5992       <INTERRUPTINFO TYPE="SOURCE">
5993         <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
5994       </INTERRUPTINFO>
5995     </MODULE>
5996     <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
5997       <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
5998       <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
5999       <DOCUMENTATION>
6000         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
6001       </DOCUMENTATION>
6002       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
6003       <PARAMETERS>
6004         <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
6005           <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
6006         </PARAMETER>
6007         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
6008           <DESCRIPTION>Device Family</DESCRIPTION>
6009         </PARAMETER>
6010         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
6011           <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
6012           <DESCRIPTION>Count Width</DESCRIPTION>
6013         </PARAMETER>
6014         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
6015           <DESCRIPTION>Only One Timer is present</DESCRIPTION>
6016         </PARAMETER>
6017         <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
6018           <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
6019         </PARAMETER>
6020         <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
6021           <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
6022         </PARAMETER>
6023         <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
6024           <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
6025         </PARAMETER>
6026         <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
6027           <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
6028         </PARAMETER>
6029         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000">
6030           <DESCRIPTION>AXI Base Address </DESCRIPTION>
6031         </PARAMETER>
6032         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff">
6033           <DESCRIPTION>AXI High Address</DESCRIPTION>
6034         </PARAMETER>
6035         <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
6036           <DESCRIPTION>AXI Address Width</DESCRIPTION>
6037         </PARAMETER>
6038         <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
6039           <DESCRIPTION>AXI Data Width</DESCRIPTION>
6040         </PARAMETER>
6041         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
6042         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
6043         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
6044         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
6045         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
6046       </PARAMETERS>
6047       <PORTS>
6048         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
6049         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
6050         <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
6051           <DESCRIPTION>Capture Trig 0</DESCRIPTION>
6052         </PORT>
6053         <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
6054           <DESCRIPTION>Capture Trig 1</DESCRIPTION>
6055         </PORT>
6056         <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
6057           <DESCRIPTION>Generate Out 0</DESCRIPTION>
6058         </PORT>
6059         <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
6060           <DESCRIPTION>Generate Out 1</DESCRIPTION>
6061         </PORT>
6062         <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
6063           <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
6064         </PORT>
6065         <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
6066         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
6067         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
6068         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
6069         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
6070         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
6071         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
6072         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
6073         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
6074         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
6075         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
6076         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
6077         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
6078         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
6079         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
6080         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
6081         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
6082         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
6083         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
6084       </PORTS>
6085       <BUSINTERFACES>
6086         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
6087           <PORTMAPS>
6088             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
6089             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
6090             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
6091             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
6092             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
6093             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
6094             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
6095             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
6096             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
6097             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
6098             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
6099             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
6100             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
6101             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
6102             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
6103             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
6104             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
6105             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
6106             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
6107           </PORTMAPS>
6108         </BUSINTERFACE>
6109       </BUSINTERFACES>
6110       <MEMORYMAP>
6111         <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
6112           <SLAVES>
6113             <SLAVE BUSINTERFACE="S_AXI"/>
6114           </SLAVES>
6115         </MEMRANGE>
6116       </MEMORYMAP>
6117       <INTERRUPTINFO TYPE="SOURCE">
6118         <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
6119       </INTERRUPTINFO>
6120     </MODULE>
6121     <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
6122       <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
6123       <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
6124       <DOCUMENTATION>
6125         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
6126       </DOCUMENTATION>
6127       <LICENSEINFO ICON_NAME="ps_core_preferred"/>
6128       <PARAMETERS>
6129         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
6130           <DESCRIPTION>Device Family</DESCRIPTION>
6131         </PARAMETER>
6132         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
6133           <DESCRIPTION>AXI Base Address </DESCRIPTION>
6134         </PARAMETER>
6135         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
6136           <DESCRIPTION>AXI High Address</DESCRIPTION>
6137         </PARAMETER>
6138         <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
6139           <DESCRIPTION>AXI Address Width</DESCRIPTION>
6140         </PARAMETER>
6141         <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
6142           <DESCRIPTION>AXI Data Width</DESCRIPTION>
6143         </PARAMETER>
6144         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="4">
6145           <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
6146         </PARAMETER>
6147         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111110111">
6148           <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
6149         </PARAMETER>
6150         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
6151           <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
6152         </PARAMETER>
6153         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
6154           <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
6155         </PARAMETER>
6156         <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
6157           <DESCRIPTION>Support IPR </DESCRIPTION>
6158         </PARAMETER>
6159         <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
6160           <DESCRIPTION>Support SIE </DESCRIPTION>
6161         </PARAMETER>
6162         <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
6163           <DESCRIPTION>Support CIE </DESCRIPTION>
6164         </PARAMETER>
6165         <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
6166           <DESCRIPTION>Support IVR </DESCRIPTION>
6167         </PARAMETER>
6168         <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
6169           <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
6170         </PARAMETER>
6171         <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
6172           <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
6173         </PARAMETER>
6174         <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
6175           <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
6176         </PARAMETER>
6177         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
6178         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
6179         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
6180         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
6181         <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
6182       </PARAMETERS>
6183       <PORTS>
6184         <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
6185           <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
6186         </PORT>
6187         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
6188         <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="3" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt &amp; Ethernet_Lite_IP2INTC_Irpt &amp; axi_timer_0_Interrupt &amp; RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
6189           <SIGNALS>
6190             <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
6191             <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
6192             <SIGNAL NAME="axi_timer_0_Interrupt"/>
6193             <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
6194           </SIGNALS>
6195           <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
6196         </PORT>
6197         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
6198         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
6199         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
6200         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
6201         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
6202         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
6203         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
6204         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
6205         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
6206         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
6207         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
6208         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
6209         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
6210         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
6211         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
6212         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
6213         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
6214         <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
6215       </PORTS>
6216       <BUSINTERFACES>
6217         <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
6218           <PORTMAPS>
6219             <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
6220             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
6221             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
6222             <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
6223             <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
6224             <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
6225             <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
6226             <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
6227             <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
6228             <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
6229             <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
6230             <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
6231             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
6232             <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
6233             <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
6234             <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
6235             <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
6236             <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
6237             <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
6238           </PORTMAPS>
6239         </BUSINTERFACE>
6240       </BUSINTERFACES>
6241       <MEMORYMAP>
6242         <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
6243           <SLAVES>
6244             <SLAVE BUSINTERFACE="S_AXI"/>
6245           </SLAVES>
6246         </MEMRANGE>
6247       </MEMORYMAP>
6248       <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
6249         <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
6250         <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
6251         <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
6252         <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
6253         <TARGET INSTANCE="microblaze_0"/>
6254       </INTERRUPTINFO>
6255     </MODULE>
6256   </MODULES>
6257
6258 </EDKSYSTEM>