git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport

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   3  <header>
   4   <DateModified>2011-07-27T13:20:02</DateModified>
   5   <ModuleName>system</ModuleName>
   6   <SummaryTimeStamp>2011-07-27T13:20:02</SummaryTimeStamp>
   7   <SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
   8   <FilterFile>filter.filter</FilterFile>
   9   <SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>
  10   <DateInitialized>2011-05-30T21:44:59</DateInitialized>
  11   <EnableMessageFiltering>false</EnableMessageFiltering>
  12  </header>
  13  <body>
  14   <viewgroup label="Design Overview" >
  15    <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="implementation\system_summary.html" label="Summary" >
  16     <toc-item title="Design Overview" target="Design Overview" />
  17     <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
  18     <toc-item title="Performance Summary" target="Performance Summary" />
  19     <toc-item title="Failing Constraints" target="Failing Constraints" />
  20     <toc-item title="Detailed Reports" target="Detailed Reports" />
  21    </view>
  22    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="implementation\system_envsettings.html" label="System Settings" />
  23    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="implementation\system_map.xrpt" label="IOB Properties" />
  24    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="implementation\system_map.xrpt" label="Control Set Information" />
  25    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="implementation\system_map.xrpt" label="Module Level Utilization" />
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  27    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="implementation\system_par.xrpt" label="Pinout Report" />
  28    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="implementation\system_par.xrpt" label="Clock Report" />
  29    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="implementation\system.twx" label="Static Timing" />
  30    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/fit/report.htm" label="CPLD Fitter Report" />
  31    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/tim/report.htm" label="CPLD Timing Report" />
  32   </viewgroup>
  33   <viewgroup label="XPS Errors and Warnings" >
  34    <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
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  38   </viewgroup>
  39   <viewgroup label="XPS Reports" >
  40    <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
  41    <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
  42    <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
  43    <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
  44    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="system.log" label="System Log File" />
  45   </viewgroup>
  46   <viewgroup label="Errors and Warnings" >
  47    <view program="pn" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered, New" file="implementation\_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
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  49    <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
  50    <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/map.xmsgs" label="Map Messages" />
  51    <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/par.xmsgs" label="Place and Route Messages" />
  52    <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/trce.xmsgs" label="Timing Messages" />
  53    <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/xpwr.xmsgs" label="Power Messages" />
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  58   </viewgroup>
  59   <viewgroup label="Detailed Reports" >
  60    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.syr" label="Synthesis Report" >
  61     <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
  62     <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
  63     <toc-item title="HDL Compilation" target="   HDL Compilation   " />
  64     <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
  65     <toc-item title="HDL Analysis" target="   HDL Analysis   " />
  66     <toc-item title="HDL Parsing" target="   HDL Parsing   " />
  67     <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
  68     <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
  69     <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
  70     <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
  71     <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
  72     <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
  73     <toc-item title="Partition Report" target="   Partition Report     " />
  74     <toc-item title="Final Report" target="   Final Report   " />
  75     <toc-item title="Design Summary" target="   Design Summary   " />
  76     <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
  77     <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
  78     <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
  79     <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
  80     <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
  81     <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
  82     <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
  83     <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
  84     <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
  85    </view>
  86    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.srr" label="Synplify Report" />
  87    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.prec_log" label="Precision Report" />
  88    <view inputState="Synthesized" program="ngdbuild" type="Report" file="implementation\system.bld" label="Translation Report" >
  89     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
  90     <toc-item title="Command Line" target="Command Line:" />
  91     <toc-item title="Partition Status" target="Partition Implementation Status" />
  92     <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
  93    </view>
  94    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="implementation\system_map.mrp" label="Map Report" >
  95     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
  96     <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
  97     <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
  98     <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
  99     <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
 100     <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
 101     <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
 102     <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
 103     <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
 104     <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
 105     <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
 106     <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
 107     <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
 108     <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
 109    </view>
 110    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="implementation\system.par" label="Place and Route Report" >
 111     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 112     <toc-item title="Device Utilization" target="Device Utilization Summary:" />
 113     <toc-item title="Router Information" target="Starting Router" />
 114     <toc-item title="Partition Status" target="Partition Implementation Status" />
 115     <toc-item title="Clock Report" target="Generating Clock Report" />
 116     <toc-item title="Timing Results" target="Timing Score:" />
 117     <toc-item title="Final Summary" target="Peak Memory Usage:" />
 118    </view>
 119    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="implementation\system.twr" label="Post-PAR Static Timing Report" >
 120     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 121     <toc-item title="Timing Report Description" target="Device,package,speed:" />
 122     <toc-item title="Informational Messages" target="INFO:" />
 123     <toc-item title="Warning Messages" target="WARNING:" />
 124     <toc-item title="Timing Constraints" target="Timing constraint:" />
 125     <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
 126     <toc-item title="Data Sheet Report" target="Data Sheet report:" />
 127     <toc-item title="Timing Summary" target="Timing summary:" />
 128     <toc-item title="Trace Settings" target="Trace Settings:" />
 129    </view>
 130    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.rpt" label="CPLD Fitter Report (Text)" >
 131     <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
 132     <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
 133     <toc-item title="Pin Resources" target="** Pin Resources **" />
 134     <toc-item title="Global Resources" target="** Global Control Resources **" />
 135    </view>
 136    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.tim" label="CPLD Timing Report (Text)" >
 137     <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
 138     <toc-item title="Performance Summary" target="Performance Summary:" />
 139    </view>
 140    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="Report" file="implementation\system.pwr" label="Power Report" >
 141     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 142     <toc-item title="Power summary" target="Power summary" />
 143     <toc-item title="Thermal summary" target="Thermal summary" />
 144    </view>
 145    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="implementation\system.bgn" label="Bitgen Report" >
 146     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 147     <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
 148     <toc-item title="Final Summary" target="DRC detected" />
 149    </view>
 150   </viewgroup>
 151   <viewgroup label="Secondary Reports" >
 152    <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="implementation\isim.log" label="ISIM Simulator Log" />
 153    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/synthesis/system_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
 154     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 155    </view>
 156    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/translate/system_translate.nlf" label="Post-Translate Simulation Model Report" >
 157     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 158    </view>
 159    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
 160    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system_map.map" label="Map Log File" >
 161     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 162     <toc-item title="Design Information" target="Design Information" />
 163     <toc-item title="Design Summary" target="Design Summary" />
 164    </view>
 165    <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
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 167     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 168     <toc-item title="Timing Report Description" target="Device,package,speed:" />
 169     <toc-item title="Informational Messages" target="INFO:" />
 170     <toc-item title="Warning Messages" target="WARNING:" />
 171     <toc-item title="Timing Constraints" target="Timing constraint:" />
 172     <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
 173     <toc-item title="Data Sheet Report" target="Data Sheet report:" />
 174     <toc-item title="Timing Summary" target="Timing summary:" />
 175     <toc-item title="Trace Settings" target="Trace Settings:" />
 176    </view>
 177    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/map/system_map.nlf" label="Post-Map Simulation Model Report" />
 178    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_map.psr" label="Physical Synthesis Report" >
 179     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 180    </view>
 181    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="implementation\system_pad.txt" label="Pad Report" >
 182     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 183    </view>
 184    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system.unroutes" label="Unroutes Report" >
 185     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 186    </view>
 187    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.tsi" label="Post-Map Constraints Interaction Report" >
 188     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 189    </view>
 190    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.grf" label="Guide Results Report" />
 191    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.dly" label="Asynchronous Delay Report" />
 192    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.clk_rgn" label="Clock Region Report" />
 193    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.tsi" label="Post-Place and Route Constraints Interaction Report" >
 194     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 195    </view>
 196    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
 197    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/par/system_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
 198    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_sta.nlf" label="Primetime Netlist Report" >
 199     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 200    </view>
 201    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="implementation\system.ibs" label="IBIS Model" >
 202     <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
 203     <toc-item title="Component" target="Component " />
 204    </view>
 205    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lck" label="Back-annotate Pin Report" >
 206     <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
 207     <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
 208    </view>
 209    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lpc" label="Locked Pin Constraints" >
 210     <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
 211     <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
 212    </view>
 213    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Secondary_Report" file="implementation\netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
 214    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="implementation\usage_statistics_webtalk.html" label="WebTalk Report" />
 215    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\webtalk.log" label="WebTalk Log File" />
 216   </viewgroup>
 217  </body>
 218 </report-views>